URL
https://opencores.org/ocsvn/wb_z80/wb_z80/trunk
Subversion Repositories wb_z80
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/trunk/rtl/inst_exec.v
71,10 → 71,10
// |
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0 |
// |
// $Id: inst_exec.v,v 1.3 2004-04-19 05:09:11 bporcella Exp $ |
// $Id: inst_exec.v,v 1.4 2004-04-19 19:13:27 bporcella Exp $ |
// |
// $Date: 2004-04-19 05:09:11 $ |
// $Revision: 1.3 $ |
// $Date: 2004-04-19 19:13:27 $ |
// $Revision: 1.4 $ |
// $Author: bporcella $ |
// $Locker: $ |
// $State: Exp $ |
81,6 → 81,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2004/04/19 05:09:11 bporcella |
// fixed some lint problems -- |
// |
// Revision 1.2 2004/04/18 18:50:08 bporcella |
// fixed some lint problems -- |
// |
128,7 → 131,7
|
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0 |
|
wire [7:0] src_pqr; // arithmetic sources gven by ir2[2:0] |
//wire [7:0] src_pqr; // arithmetic sources gven by ir2[2:0] |
wire [7:0] src_hr ; |
wire [7:0] src_lr ; |
//wire [7:0] alu_out; // {CF. 8bit_result} |
152,7 → 155,7
wire [7:0] alu8_fr ; |
wire alu8_nf ; |
wire c_8out7 ; |
wire alu8_cry ; |
//wire alu8_cry ; |
wire alu8_hcry ; |
wire [7:0] alu8_out ; |
wire add16_ofl ; |
237,7 → 240,7
{8{ir2[2:0]==REG8_E }} & er | |
{8{ir2[2:0]==REG8_H }} & src_hr | |
{8{ir2[2:0]==REG8_L }} & src_lr | |
{8{ir2[2:0]==REG8_MEM}} & nn[7:0] | |
{8{ir2[2:0]==REG8_MEM}} & nn[15:8] | |
{8{ir2[2:0]==REG8_A }} & ar ; |
|
assign src_pqr53 = {8{ir2[5:3]==REG8_B }} & br | |
246,7 → 249,7
{8{ir2[5:3]==REG8_E }} & er | |
{8{ir2[5:3]==REG8_H }} & src_hr | |
{8{ir2[5:3]==REG8_L }} & src_lr | |
{8{ir2[5:3]==REG8_MEM}} & nn[7:0] | |
{8{ir2[5:3]==REG8_MEM}} & nn[15:8] | |
{8{ir2[5:3]==REG8_A }} & ar ; |
|
|
255,10 → 258,10
{16{ir2[5:4]==2'b10}} & src_dblhr | // HL, ixr, iyr |
{16{ir2[5:4]==2'b11}} & sp ; |
|
|
|
|
|
assign sh_src = ir2[8] & dd_grp ? nn[15:8] : |
ir2[8] & fd_grp ? nn[15:8] : |
ir2 ? src_pqr20 : |
ar ; |
// I wonder how well the synthesizer can reduce this??? - It is probably worth spending |
// some time during physical design to see if a more low level description would help -- |
// there is somebody out there who knows - and there is probably a good low level description. |
324,22 → 327,22
// making ed_blk_cp high priority kind of negates the origional idea of making the |
// decodes fast here --- course when all is included this can't be too fast. |
// Just note for syntheses that this is a slow path that could be improved with some thought. |
// |
// 1 1 8 8 1 |
assign {alu8_cry, alu8_hcry, alu8_out, src_pqri, c_8in0 }= |
|
ed_blk_cp ? {c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} : //CPI CPIR CPD CPDR |
|
{14{ir2[7:3]==5'b10000}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'b0} ) |// a+src |
{14{ir2[7:3]==5'b10001}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, cf} ) |// a+src+cf |
{14{ir2[7:3]==5'b10010}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} ) |// a-src |
{14{ir2[7:3]==5'b10011}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, ~cf } ) |// a-src-cf |
{14{ir2[7:3]==5'b10100}} & ({1'b0 ,1'b1 , ar & src_pqr, src_pqr20, 1'b0} ) |// a&src |
{14{ir2[7:3]==5'b10101}} & ({1'b0 ,1'b0 , ar ^ src_pqr, src_pqr20, 1'b0} ) |// a^src |
{14{ir2[7:3]==5'b10110}} & ({1'b0 ,1'b0 , ar | src_pqr, src_pqr20, 1'b0} ) |// a|src |
{14{ir2[7:3]==5'b10111}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'h1}) |// a-src |
{14{(ir2[7:6]==2'b00)& ~ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h1}) |// inc_r main |
{14{(ir2[7:6]==2'b00)& ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h0}) |// dec_r |
{14{(ir2[7:6]==2'b01) }}& ({c_8out7,c_8out3, add_8bit, ~ar, 1'h1}) ;// ed44 -a |
{19{ir2[7:3]==5'b10000}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'b0} ) |// a+src |
{19{ir2[7:3]==5'b10001}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, cf} ) |// a+src+cf |
{19{ir2[7:3]==5'b10010}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} ) |// a-src |
{19{ir2[7:3]==5'b10011}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, ~cf } ) |// a-src-cf |
{19{ir2[7:3]==5'b10100}} & ({1'b0 ,1'b1 , ar & src_pqr20, src_pqr20, 1'b0} ) |// a&src |
{19{ir2[7:3]==5'b10101}} & ({1'b0 ,1'b0 , ar ^ src_pqr20, src_pqr20, 1'b0} ) |// a^src |
{19{ir2[7:3]==5'b10110}} & ({1'b0 ,1'b0 , ar | src_pqr20, src_pqr20, 1'b0} ) |// a|src |
{19{ir2[7:3]==5'b10111}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'h1}) |// a-src |
{19{(ir2[7:6]==2'b00)& ~ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h1}) |// inc_r main |
{19{(ir2[7:6]==2'b00)& ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h0}) |// dec_r |
{19{(ir2[7:6]==2'b01) }}& ({c_8out7,c_8out3, add_8bit, ~ar, 1'h1}) ;// ed44 -a |
|
|
// do some hand decoding here |
355,7 → 358,7
// ---------------- 16 bit adder with bit 11 carrry out and bit 8 carry in ------------------ |
// |
assign add16_ofl = (src_a[15] == src_b[15]) & (src_a[15] != add16[15]); |
|
///tmp/lint/wb_z80/rtl/inst_exec.v(363): Warning 22014: synchronous loop without set/reset detected on signal "src_b[11:8]" (OC) |
assign {c_16out7, add16[7:0]} = {1'b0, src_a[7:0]} + {1'b0, src_b[7:0] } + {8'b0, c_16in0}; |
assign {c_16out11, add16[11:8]} = {1'b0, src_a[11:8]} + {1'b0, src_b[11:8] } + {4'b0, c_16out7}; |
assign {c_16out15, add16[15:12]} = {1'b0, src_a[15:12]} + {1'b0, src_b[15:12]} + {4'b0, c_16out11}; |
505,7 → 508,7
LDsA_6DE7 == ir2 | // LD A,(DE) ; 1A |
LDsA_6NN7 == ir2 | // LD A,(NN) ; 3A XX XX |
INsA_6N7 == ir2 | // IN A,(N) ; DB XX |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_A) ; |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_A) ; |
|
|
//EXsAF_AFp = 10'h08,// EX AF,AF' ; 08 |
514,7 → 517,7
//CPL = 10'h2F,// CPL ; 2F a <= ~a |
//POPsAF = 10'hF1,// POP AF ; F1 |
// don't forget these beauties not affected by prefixes |
//ED_RRD = 'h67// RRD ; compair with {ir2[9:6],ir2[3:0]} all |
//ED_RRD = 'h67// RRD ; |
//ED_RLD = 'h6F// RLD ; ED 6F nibble roates A (HL) |
//ED_NEG = 5'b01___100, // A<= -A compair with {ir2[9:6],ir2[2:0]} |
|
523,7 → 526,7
assign upd_ar = upd_a_alu8 | up_a_sh_alu | up_a_src_pqr | up_a_n | ir2 == EXsAF_AFp | |
ir2 == EXX | ir2 == DAA | ir2 == CPL | ir2 == POPsAF | |
ir2[2:0] == REG8_A & bit_alu_act | ir2[2:0] == REG8_A & sh_alu_act | |
{ir2[9:6], ir2[3:0]} == ED_RRD | {ir2[9:6], ir2[2:0]} == ED_NEG | |
{ir2== ED_RRD | {ir2[9:6], ir2[2:0]} == ED_NEG | |
ir2 == ED_LDsA_I ; |
|
always @(posedge clk) |
530,7 → 533,7
begin |
if (upd_a_alu8 & exec_ir2) ar <= alu8_out; |
if (up_a_sh_alu & exec_ir2) ar <= sh_alu; |
if (up_a_src_pqr & exec_ir2) ar <= src_pqr; |
if (up_a_src_pqr & exec_ir2) ar <= src_pqr20; |
if (up_a_n & exec_ir2) ar <= nn[7:0]; |
if (ir2 == EXsAF_AFp & exec_ir2) ar <= ap; |
if (ir2 == EXX & exec_ir2) ar <= ap; |
541,8 → 544,8
bit_alu_act & exec_ir2) ar <= bit_alu; |
if (ir2[2:0] == REG8_A & |
sh_alu_act & exec_ir2) ar <= sh_alu; |
if ({ir2[9:6], ir2[3:0]} == ED_RRD & exec_ir2) ar[3:0] <= nn[3:0]; |
if ({ir2[9:6], ir2[3:0]} == ED_RLD & exec_ir2) ar[3:0] <= nn[7:4]; |
if (ir2 == ED_RRD & exec_ir2) ar[3:0] <= nn[3:0]; |
if (ir2 == ED_RLD & exec_ir2) ar[3:0] <= nn[7:4]; |
if ({ir2[9:6], ir2[2:0]} == ED_NEG & exec_ir2) ar <= alu8_out; // ED44 this done by alu8 for flags |
if (ir2 == ED_LDsA_I & exec_ir2) ar <= ir2[7:0] ; |
end |
603,13 → 606,13
assign upd_br = upd_b_alu8 | up_b_src_pqr | up_b_add16 | LDsBC_NN == ir2 | |
POPsBC == ir2 | EXX == ir2 | LDsB_N == ir2 | |
ir2[2:0] == REG8_B & bit_alu_act | ir2[2:0] == REG8_B & sh_alu_act | |
DJNZs$t2 == ir2 | (ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_B); |
DJNZs$t2 == ir2 | (ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_B); |
|
|
always @(posedge clk) |
begin |
if ( upd_b_alu8 & exec_ir2) br <= alu8_out; |
if ( up_b_src_pqr & exec_ir2) br <= src_pqr; |
if ( up_b_src_pqr & exec_ir2) br <= src_pqr20; |
if ( up_b_add16 & exec_ir2) br <= add16[15:8]; |
if ( LDsBC_NN == ir2 & exec_ir2) br <= nn[15:8]; |
if ( POPsBC == ir2 & exec_ir2) br <= nn[15:8]; |
651,13 → 654,13
//LDsBC_NN = 10'h01,// LD BC,NN ; 01 XX XX |
//POPsBC = 10'hC1,// POP BC ; C1 |
//EXX = 10'hD9,// EXX ; D9 |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[9:6],ir2[2:0]} really (BCio) |
|
//------------------------------- cr ----------------------------------------- |
assign upd_cr = upd_c_alu8 | up_c_src_pqr | up_c_add16 | LDsBC_NN == ir2 | |
POPsBC == ir2 | EXX == ir2 | LDsC_N == ir2 | |
ir2[2:0] == REG8_C & bit_alu_act | ir2[2:0] == REG8_C & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_C); |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_C); |
|
|
|
664,7 → 667,7
always @(posedge clk) |
begin |
if ( upd_c_alu8 & exec_ir2) cr <= alu8_out; |
if ( up_c_src_pqr & exec_ir2) cr <= src_pqr; |
if ( up_c_src_pqr & exec_ir2) cr <= src_pqr20; |
if ( up_c_add16 & exec_ir2) cr <= add16[7:0]; |
if ( LDsBC_NN == ir2 & exec_ir2) cr <= nn[7:0]; |
if ( POPsBC == ir2 & exec_ir2) cr <= nn[7:0]; |
675,7 → 678,7
if (ir2[2:0] == REG8_C & |
sh_alu_act & exec_ir2) cr <= sh_alu; |
if ( exec_decbc) cr <= decc_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_C) & exec_ir2) |
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_C) & exec_ir2) |
cr <= nn[7:0]; |
|
end |
683,12 → 686,12
|
// update dr |
assign up_d_add16 = |
INCsDE == 10'h13 | // INC DE ; 13 |
DECsDE == 10'h1B ; // DEC DE ; 1B |
INCsDE == ir2 | // INC DE ; 13 |
DECsDE == ir2 ; // DEC DE ; 1B |
|
assign upd_d_alu8 = |
INCsD == 10'h14 | // INC D ; 14 |
DECsD == 10'h15 ; // DEC D ; 15 |
INCsD == ir2 | // INC D ; 14 |
DECsD == ir2 ; // DEC D ; 15 |
assign up_d_src_pqr = |
LDsD_B == ir2 | //LD D,B ; 50 |
LDsD_C == ir2 | //LD D,C ; 51 |
705,7 → 708,7
//POPsDE = 10'hD1,// POP DE ; D1 |
//EXX = 10'hD9,// EXX ; D9 |
//EXsDE_HL = 10'hEB,// EX DE,HL ; EB |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[9:6],ir2[2:0]} really (BCio) |
|
//---------------------------------- dr ------------------------------------ |
|
712,7 → 715,7
assign upd_dr = upd_d_alu8 | up_d_src_pqr | up_d_add16 | LDsDE_NN == ir2 | |
POPsDE == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsD_N == ir2 | |
ir2[2:0] == REG8_D & bit_alu_act | ir2[2:0] == REG8_D & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_D); |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_D); |
|
|
|
722,7 → 725,7
always @(posedge clk) |
begin |
if ( upd_d_alu8 & exec_ir2) dr <= alu8_out; |
if ( up_d_src_pqr & exec_ir2) dr <= src_pqr; |
if ( up_d_src_pqr & exec_ir2) dr <= src_pqr20; |
if ( up_d_add16 & exec_ir2) dr <= add16[15:8]; |
if ( LDsDE_NN == ir2 & exec_ir2) dr <= nn[15:8]; |
if ( POPsDE == ir2 & exec_ir2) dr <= nn[15:8]; |
733,7 → 736,7
bit_alu_act & exec_ir2) dr <= bit_alu; |
if (ir2[2:0] == REG8_D & |
sh_alu_act & exec_ir2) dr <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) |
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) |
& (ir2[5:3] == REG8_D) & exec_ir2) |
dr <= nn[7:0]; |
|
761,7 → 764,7
//POPsDE = 10'hD1,// POP DE ; D1 |
//EXX = 10'hD9,// EXX ; D9 |
//EXsDE_HL = 10'hEB,// EX DE,HL ; EB |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[9:6],ir2[2:0]} really (BCio) |
|
//---------------------------------- er ------------------------------------ |
|
769,7 → 772,7
assign upd_er = upd_e_alu8 | up_e_src_pqr | up_e_add16 | LDsDE_NN == ir2 | |
POPsDE == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsD_N == ir2 | |
ir2[2:0] == REG8_E & bit_alu_act | ir2[2:0] == REG8_E & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_E); |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_E); |
|
|
|
782,7 → 785,7
always @(posedge clk) |
begin |
if ( upd_e_alu8 & exec_ir2) er <= alu8_out; |
if ( up_e_src_pqr & exec_ir2) er <= src_pqr; |
if ( up_e_src_pqr & exec_ir2) er <= src_pqr20; |
if ( up_e_add16 & exec_ir2) er <= add16[7:0]; |
if ( LDsDE_NN == ir2 & exec_ir2) er <= nn[7:0]; |
if ( POPsDE == ir2 & exec_ir2) er <= nn[7:0]; |
793,7 → 796,7
bit_alu_act & exec_ir2) er <= bit_alu; |
if (ir2[2:0] == REG8_E & |
sh_alu_act & exec_ir2) er <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_E) & exec_ir2) |
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_E) & exec_ir2) |
er <= nn[7:0]; |
|
end |
819,7 → 822,7
LDsH_L == ir2 | // LD H,L ; 65 |
LDsH_6HL7 == ir2 | // LD H,(HL) ; 66 |
LDsH_A == ir2 ; // LD H,A ; 67 |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio) |
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[9:6],ir2[2:0]} really (BCio) |
|
//POPsHL = 10'hE1,// POP HL ; E1 |
//EXs6SP7_HL = 10'hE3,// EX (SP),HL ; E3 |
839,7 → 842,7
assign upd_hr = upd_h_alu8 | upd_h_src_pqr | up_h_add16 | LDsHL_NN == ir2 | LDsHL_6NN7== ir2 | |
POPsHL == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsH_N == ir2 | |
ir2[2:0] == REG8_H & bit_alu_act | ir2[2:0] == REG8_H & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_H); |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_H); |
|
|
|
849,7 → 852,7
always @(posedge clk) |
begin |
if ( upd_h_alu8 & exec_hlir2) hr <= alu8_out; |
if ( upd_h_src_pqr & exec_hlir2) hr <= src_pqr; |
if ( upd_h_src_pqr & exec_hlir2) hr <= src_pqr20; |
if ( up_h_add16 & exec_hlir2) hr <= add16[15:8]; |
if ( LDsHL_NN == ir2 & exec_hlir2) hr <= nn[15:8]; |
if ( LDsHL_6NN7== ir2 & exec_hlir2) hr <= nn[15:8]; |
862,7 → 865,7
bit_alu_act & exec_hlir2) hr <= bit_alu; |
if (ir2[2:0] == REG8_H & |
sh_alu_act & exec_hlir2) hr <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_H) & exec_ir2) |
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_H) & exec_ir2) |
hr <= nn[7:0]; |
|
end |
902,7 → 905,7
assign upd_lr = upd_l_alu8 | upd_l_src_pqr | up_l_add16 | LDsHL_NN == ir2 | LDsHL_6NN7== ir2 | |
POPsHL == ir2 | EXX == ir2 | EXsDE_HL == ir2 | LDsL_N == ir2 | |
ir2[2:0] == REG8_L & bit_alu_act | ir2[2:0] == REG8_L & sh_alu_act | |
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_L); |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_L); |
|
|
|
909,7 → 912,7
always @(posedge clk) |
begin |
if ( upd_l_alu8 & exec_hlir2) lr <= alu8_out; |
if ( upd_l_src_pqr & exec_hlir2) lr <= src_pqr; |
if ( upd_l_src_pqr & exec_hlir2) lr <= src_pqr20; |
if ( up_l_add16 & exec_hlir2) lr <= add16[7:0]; |
if ( LDsHL_NN == ir2 & exec_hlir2) lr <= nn[7:0]; |
if ( LDsHL_6NN7== ir2 & exec_hlir2) lr <= nn[7:0]; |
922,7 → 925,7
bit_alu_act & exec_hlir2) lr <= bit_alu; |
if (ir2[2:0] == REG8_L & |
sh_alu_act & exec_hlir2) lr <= sh_alu; |
if ((ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_L) & exec_ir2) |
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_L) & exec_ir2) |
lr <= nn[7:0]; |
|
end |
931,7 → 934,7
always @(posedge clk) |
begin |
if ( upd_l_alu8 & exec_ixir2) ixr[7:0] <= alu8_out; |
if ( upd_l_src_pqr & exec_ixir2) ixr[7:0] <= src_pqr; |
if ( upd_l_src_pqr & exec_ixir2) ixr[7:0] <= src_pqr20; |
if ( up_l_add16 & exec_ixir2) ixr[7:0] <= add16[7:0]; |
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0]; |
949,7 → 952,7
always @(posedge clk) |
begin |
if ( upd_h_alu8 & exec_ixir2) ixr[15:8] <= alu8_out; |
if ( upd_h_src_pqr & exec_ixir2) ixr[15:8] <= src_pqr; |
if ( upd_h_src_pqr & exec_ixir2) ixr[15:8] <= src_pqr20; |
if ( up_h_add16 & exec_ixir2) ixr[15:8] <= add16[15:8]; |
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8]; |
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8]; |
969,7 → 972,7
always @(posedge clk) |
begin |
if ( upd_l_alu8 & exec_iyir2) iyr[7:0] <= alu8_out; |
if ( upd_l_src_pqr & exec_iyir2) iyr[7:0] <= src_pqr; |
if ( upd_l_src_pqr & exec_iyir2) iyr[7:0] <= src_pqr20; |
if ( up_l_add16 & exec_iyir2) iyr[7:0] <= add16[7:0]; |
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0]; |
987,7 → 990,7
always @(posedge clk) |
begin |
if ( upd_h_alu8 & exec_iyir2) iyr[15:8] <= alu8_out; |
if ( upd_h_src_pqr & exec_iyir2) iyr[15:8] <= src_pqr; |
if ( upd_h_src_pqr & exec_iyir2) iyr[15:8] <= src_pqr20; |
if ( up_h_add16 & exec_iyir2) iyr[15:8] <= add16[15:8]; |
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8]; |
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8]; |
1082,8 → 1085,8
|
// update all flags from alu16 |
assign upd_fr_edadd16 = |
ED_SBCsHL_REG == {ir2[7:6],ir2[3:0]} | // compair with {ir2[7:6],ir2[3:0]} |
ED_ADCsHL_REG == {ir2[7:6],ir2[3:0]} ; // compair with {ir2[7:6],ir2[3:0]} |
ED_SBCsHL_REG == {ir2[9:6],ir2[3:0]} | // compair with {ir2[9:6],ir2[3:0]} |
ED_ADCsHL_REG == {ir2[9:6],ir2[3:0]} ; // compair with {ir2[9:6],ir2[3:0]} |
|
|
// the shifts probably muck with all flags (some operations are |
1114,13 → 1117,13
//INCs6HL7 = 'h34,// INC (HL) ; 34 |
//DECs6HL7 = 'h35,// DEC (HL) ; 35 |
|
// ED Block Move messyness upd_b_decbc |
// ED Block Move messyness upd_b_decbc 4/19/2004 not used - probably not needed |
// hf and nf <= 0 pnf<= BC==0 |
assign eb_blk_mv = |
ED_LDI == ir2 | // LDI ; ED A0 (DE++) <= (HL++) , BC-- |
ED_LDD == ir2 | // LDD ; ED A8 (DE--) <= (HL--) , BC-- |
ED_LDIR == ir2 | // LDIR ; ED B0 (DE++) <= (HL++) , BC-- Repeat til BC==0 |
ED_LDDR == ir2 ;// LDDR ; ED B8 (DE--) <= (HL--) , BC-- Repeat til BC==0 |
//assign eb_blk_mv = |
// ED_LDI == ir2 | // LDI ; ED A0 (DE++) <= (HL++) , BC-- |
// ED_LDD == ir2 | // LDD ; ED A8 (DE--) <= (HL--) , BC-- |
// ED_LDIR == ir2 | // LDIR ; ED B0 (DE++) <= (HL++) , BC-- Repeat til BC==0 |
// ED_LDDR == ir2 ;// LDDR ; ED B8 (DE--) <= (HL--) , BC-- Repeat til BC==0 |
// only c not affected - nf<=1 ? |
assign ed_blk_cp = |
ED_CPI == ir2 | // CPI ; ED A1 A - (HL++) , BC-- |
1174,10 → 1177,12
(SCF == ir2 ) | |
(ED_RRD == ir2) | |
(ED_RLD == ir2) | |
(ED_LDsA_I == ir2) ) ; |
(ED_LDsA_I == ir2) | |
(ir2 == EXsAF_AFp ) | |
(ir2 == EXX ) ); |
|
|
|
|
|
wire iff2 = 1'b0; // this is supposed to be int ff #2 which is not (yet) implmented |
always @(posedge clk) |
begin |
1206,7 → 1211,10
if (ED_RLD == ir2) fr <= { sf, ~|{ar[7:4],nn[7:4]}, ar[5], 1'b0, |
ar[3], ~^{ar[7:4],nn[7:4]}, 1'b0 , cf }; |
if (ED_LDsA_I == ir2) fr <= { ir2[7], ~|ir2, ir2[5], 1'b0, ir2[3], iff2, 1'b0, cf }; // iff2 ? |
|
if (ir2 == EXsAF_AFp) fr <= fp; |
if (ir2 == EXX ) fr <= fp; |
|
|
end |
// in the case of blk_cp the update above is executed 2nd - and so these are don't cares. |
if (exec_decb ) fr <= {decb_alu[7], ~|decb_alu, decb_alu[5], hf, |
/trunk/rtl/memstate2.v
109,10 → 109,10
// complete before starting the ir1 operation |
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0 |
// |
// $Id: memstate2.v,v 1.7 2004-04-19 05:09:11 bporcella Exp $ |
// $Id: memstate2.v,v 1.8 2004-04-19 19:13:28 bporcella Exp $ |
// |
// $Date: 2004-04-19 05:09:11 $ |
// $Revision: 1.7 $ |
// $Date: 2004-04-19 19:13:28 $ |
// $Revision: 1.8 $ |
// $Author: bporcella $ |
// $Locker: $ |
// $State: Exp $ |
119,6 → 119,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2004/04/19 05:09:11 bporcella |
// fixed some lint problems -- |
// |
// Revision 1.6 2004/04/18 18:50:09 bporcella |
// fixed some lint problems -- |
// |
141,7 → 144,7
// |
// |
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0 |
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_lock, wb_tga_io, wb_dat_o, |
module memstate2(wb_adr, wb_we, wb_cyc, wb_stb, wb_tga_io, wb_dat_o, |
exec_ir2, ir1, ir2, ir1dd, ir1fd, ir2dd, ir2fd, nn, sp, |
|
upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr, |
164,7 → 167,7
output wb_we; |
output wb_cyc; |
output wb_stb; |
output wb_lock; // bit set and clear insts should be atomic - could matter sometime |
//output wb_lock; // bit set and clear insts should be atomic - could matter sometime |
output [1:0] wb_tga_io; |
output [7:0] wb_dat_o; // from nn |
//output [15:0] add_out; (may not wb_adr) 4/18/2004?? why? |
197,7 → 200,7
|
parameter TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to |
TAG_INT = 2'b10; // document this. |
// 12na |
// 12na // 1 is ir1 2 is ir2 n is nn gets memory a is activate ir2 |
parameter IPIPE_NOP = 4'b0000, // guess I could define single bits and add them up |
IPIPE_A2 = 4'b0001, // would keep from getting lint bitching -- but heck |
IPIPE_ENN = 4'b0010, // I'm married -> an expert at ignoring such stuff :-) |
350,7 → 353,7
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0 |
|
|
//wire use_sp; // old names probably from first go-around |
//wire use_sp; // old names probably from first go-around |
//wire use_pc; |
//wire use_hl; |
//wire use_de; |
370,13 → 373,13
wire [15:0] hl, de, bc; |
wire [3:0] mem_exec_dec; |
|
wire use_a ; |
wire use_b ; |
wire use_c ; |
wire use_d ; |
wire use_e ; |
wire use_h ; |
wire use_l ; |
//wire use_a ;old names for hazard dect. remove |
//wire use_b ; |
//wire use_c ; |
//wire use_d ; |
//wire use_e ; |
//wire use_h ; |
//wire use_l ; |
// don't forget that as 1r1 is executed it is transferred to ir2. Anything I need to know |
// about subsequent operations must be stored. |
// 6 5 4 15 |
406,9 → 409,9
|
reg [5:0] dec_state; // the register set each clock from next_dec_state; |
|
reg of16_reg, os16_reg, rmw8_reg, call_reg, ret_reg, ioi; |
reg push_reg; |
reg pop_reg; |
//reg of16_reg, os16_reg, rmw8_reg, call_reg, ret_reg, ioi; |
//reg push_reg; |
//reg pop_reg; |
reg inst_haz; |
reg exec_ir2; |
reg blk_rpt_flg; |
424,7 → 427,7
assign wb_dat_o = nn[15:8]; |
|
wire sf, zf, f5f, hf, f3f, pvf, nf, cf; |
assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr; |
assign { sf, zf, f5f, hf, f3f, pvf, nf, cf} = fr; // no load on f5f, f3f ok hf nf used in inst_exec.v |
|
|
assign hl = {hr, lr}; |
838,7 → 841,7
LDs6NN7_A == ir1 | // LD (NN),A ; 32 XX XX |
PUSHsAF == ir1 | |
OUTs6N7_A == ir1 | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0] && REG8_A == ir1[5:3]} ; |
(ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]}) & REG8_A == ir1[5:3] ; |
|
wire os_b = LDs6HL7_B == ir1 | // LD (HL),B ; 70 |
ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_BC == ir1[5:4] | |
866,7 → 869,7
PUSHsHL == ir1 | |
ED_OUTs6C7_REG == {ir1[9:6],ir1[2:0]} & REG8_L == ir1[5:3] ; |
|
wire os_sp = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_SP == ir1[5:4]; |
// wire os_sp = ED_LDs6NN7_REG == {ir1[9:6],ir1[3:0]} & DBL_REG_SP == ir1[5:4]; not used ? |
|
wire os_f = PUSHsAF == ir1 ; |
|
971,8 → 974,8
|
|
|
wire bc_eq0 = beq0 & ceq0; |
// ??? not used ? why defined ? |
//wire bc_eq0 = beq0 & ceq0; |
// ??? not used ? why defined ? I simply re-wrote the test re-name |
//assign rpt_blk_mv = (blk_mv_reg ) & !bc_eq0 | |
// (blk_cmp_reg) & !bc_eq0 & (nn[7:0] != 8'h0) | |
// (blk_in_reg | blk_out_reg) & !b_eq0 ; |
1058,17 → 1061,17
|
|
|
wire src_mux = {16{ src_sp }} & sp | |
{16{ src_pc }} & pc | |
{16{ src_nn }} & nn | |
{16{ src_hl }} & hl | |
{16{ src_de }} & de | |
{16{ src_bc }} & bc | |
{16{ src_ix }} & ixr | |
{16{ src_iy }} & iyr | |
{16{ src_adr }} & wb_adr | |
{16{ src_int }} & { intr, nn[15:8] } | |
{16{next_mem_state == MEM_IFRST}} & {10'h0, ir1[6:4], 3'h0} ; |
wire [15:0] src_mux = {16{ src_sp }} & sp | |
{16{ src_pc }} & pc | |
{16{ src_nn }} & nn | |
{16{ src_hl }} & hl | |
{16{ src_de }} & de | |
{16{ src_bc }} & bc | |
{16{ src_ix }} & ixr | |
{16{ src_iy }} & iyr | |
{16{ src_adr }} & wb_adr | |
{16{ src_int }} & { intr, nn[15:8] } | |
{16{next_mem_state == MEM_IFRST}} & {10'h0, ir1[6:4], 3'h0} ; |
|
wire block_mv_inc = (dec_state == DEC_ED) ? dec_blk_inc : blk_inc_flg; // flag set at DEC_ED |
|
1094,12 → 1097,14
next_mem_state == MEM_OFIXpD | |
next_mem_state == MEM_OSIXpD ; |
|
wire src2 = {16{ inc }} & 16'h0001 | |
{16{ dec }} & 16'hffff | |
{16{ reln }} & {{8{nn[15]}},nn[15:8]}| |
{16{~(reln |inc |dec )}} & 16'h0 ; |
wire [15:0] src2 = {16{ inc }} & 16'h0001 | |
{16{ dec }} & 16'hffff | |
{16{ reln }} & {{8{nn[15]}},nn[15:8]}| |
{16{~(reln | inc | dec)}} & 16'h0 ;// lint complains that this signal |
// has no load -YES it is not needed - |
// more for information -- amazing complaint though |
|
wire adr_alu = src2 + src_mux; |
wire [15:0] adr_alu = src2 + src_mux; |
|
|
wire pre_inc_dec = next_mem_state == MEM_CALL | |
1107,7 → 1112,7
next_mem_state == MEM_OSSP ; |
|
|
wire mux21 = pre_inc_dec ? adr_alu : src_mux; |
wire [15:0] mux21 = pre_inc_dec ? adr_alu : src_mux; |
|
assign wb_rdy_nhz = (!wb_cyc | wb_ack ) & ~hazard; // wishbone ready with no hazard |
wire wb_rdy = !wb_cyc | wb_ack; |
1133,7 → 1138,7
// 6 5 4 15 |
assign {next_dec_state, next_mem_state, next_pipe_state} = next_state; |
|
always @(ir1 or wb_int or inst_haz or wb_int or dec_state or mem_exec_dec or cb_mem or ed_nn or |
always @(ir1 or wb_int or inst_haz or dec_state or mem_exec_dec or cb_mem or ed_nn or |
ed_blk_cp or ed_blk_in or ed_blk_out or ed_retn or ed_blk_mv or ed_dbl_rd or blk_done or |
fr or jmpr_true or callnn_true or jmpnn_true ) |
|
1320,12 → 1325,12
// if there's anyone who knows is there anyone who cares. |
// guess I'll do it fast -- just a 16 bit subtractor. heck silicon is |
// cheap. |
DEC_INT1: next_state <= {DEC_INT2, MEM_OSSP_PCM2, IPIPE_NOP}; //must derement PC |
DEC_INT2: next_state <= {DEC_INT3, MEM_OSSP_P, IPIPE_NOP}; //must dec sp and PC 2 ops? |
DEC_INT3: next_state <= {DEC_INT4, MEM_INTA, IPIPE_NOP}; |
DEC_INT4: next_state <= {DEC_INT5, MEM_NOP, IPIPE_ENN}; |
DEC_INT5: next_state <= {DEC_IF2, MEM_IFINT, IPIPE_NOP}; |
default: next_state <= {DEC_IDLE, MEM_NOP, IPIPE_NOP}; |
DEC_INT1: next_state = {DEC_INT2, MEM_OSSP_PCM2, IPIPE_NOP}; //must derement PC |
DEC_INT2: next_state = {DEC_INT3, MEM_OSSP_P, IPIPE_NOP}; //must dec sp and PC 2 ops? |
DEC_INT3: next_state = {DEC_INT4, MEM_INTA, IPIPE_NOP}; |
DEC_INT4: next_state = {DEC_INT5, MEM_NOP, IPIPE_ENN}; |
DEC_INT5: next_state = {DEC_IF2, MEM_IFINT, IPIPE_NOP}; |
default: next_state = {DEC_IDLE, MEM_NOP, IPIPE_NOP}; |
endcase |
end |
|
1500,8 → 1505,8
if (os_l) nn <= {lr, hr }; // use for PUSHsHL |
if (os_f) nn <= {fr, ar }; // use for PUSHsAF |
end |
|
else nn <= { wb_dat_i, nn[15:8] }; |
// 4/19/2004 previously no if here - if not needed we don't need next_pipe_state[1] eithor |
else if (next_pipe_state[1]) nn <= { wb_dat_i, nn[15:8] }; |
end |
|
|