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URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

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  • This comparison shows the changes necessary to convert path
    /zap/trunk
    from Rev 37 to Rev 38
    Reverse comparison

Rev 37 → Rev 38

/src/rtl/cpu/zap_predecode_compress.v
38,6 → 38,9
input wire [31:0] i_instruction,
input wire i_instruction_valid,
 
// Offset input.
input wire [11:0] i_offset,
 
// Interrupts. Active high level sensitive signals.
input wire i_irq,
input wire i_fiq,
69,15 → 72,12
 
///////////////////////////////////////////////////////////////////////////////
 
reg [11:0] offset_ff, offset_nxt; // Remember offset.
reg [11:0] offset_w; // Previous offset.
 
///////////////////////////////////////////////////////////////////////////////
 
// Keep buferring offset since a long offset is constructed using consecutive
// valid compressed instructions.
always @ (posedge i_clk)
if ( i_instruction_valid )
offset_ff <= offset_nxt;
always @*
offset_w = i_offset;
 
///////////////////////////////////////////////////////////////////////////////
 
90,12 → 90,12
o_irq = i_irq;
o_fiq = i_fiq;
o_force32_align = 0;
offset_nxt = i_instruction[11:0];
 
 
if ( i_cpsr_ff_t && i_instruction_valid ) // compressed mode enable
begin
casez ( i_instruction[15:0] )
T_BLX1 : decode_blx1;
T_BLX2 : decode_blx2;
T_ADD_SUB_LO : decode_add_sub_lo;
T_SWI : decode_swi;
T_BRANCH_COND : decode_conditional_branch;
502,22 → 502,49
 
///////////////////////////////////////////////////////////////////////////////
 
task decode_blx1;
begin
o_instruction = 0; // Default value.
 
// Generate a BLX1.
o_instruction[31:25] = 7'b1111_101; // BLX1 identifier.
o_instruction[24] = 1'd0; // H - bit.
o_instruction[23:0] = ($signed(offset_w) << 12) | (i_instruction[10:0] << 1); // Corrected.
o_irq = 1'd0;
o_fiq = 1'd0;
end
endtask
 
////////////////////////////////////////////////////////////////////////////////
 
task decode_blx2;
begin
o_instruction = {4'b1110,4'b0001,4'b0010,4'b1111,4'b1111,4'b1111,4'b0011, i_instruction[6:3]};
o_irq = 1'd0;
o_fiq = 1'd0;
end
endtask
 
///////////////////////////////////////////////////////////////////////////////
 
task decode_bl;
begin
case ( i_instruction[11] )
1'd0:
begin
// Store the offset and send out a dummy instruction.
// offset_nxt = i_instruction[11:0];
o_instruction = 32'd0;
o_irq = 1'd0;
o_fiq = 1'd0;
// Send out a dummy instruction. Preserve lower
// 12-bits though to serve as offset. Set condition
// code to NV.
o_instruction = i_instruction[11:0];
o_instruction[31:28] = 4'b1111;
o_irq = 1'd0;
o_fiq = 1'd0;
end
1'd1:
begin
// Generate a full jump.
o_instruction = {1'd1, 2'b0, AL, 3'b101, 1'b1, 24'd0};
o_instruction[23:0] = ($signed(offset_ff) << 12) | (i_instruction[11:0]);
o_instruction[23:0] = ($signed(offset_w) << 12) | (i_instruction[10:0] << 1); // Corrected.
o_irq = 1'd0;
o_fiq = 1'd0;
end
/src/rtl/cpu/zap_predecode_coproc.v
113,6 → 113,12
wire c4 = i_instruction[34:32] == 3'd0;
wire c5 = c1 & c2 & c3 & c4;
 
`ifndef SYNTHESIS
 
reg eclass;
 
`endif
 
// Next state logic.
always @*
begin
126,38 → 132,66
o_irq = i_irq;
o_fiq = i_fiq;
 
`ifndef SYNTHESIS
eclass = 0;
`endif
 
case ( state_ff )
IDLE:
// Activate only if no thumb, not in USER mode and CP15 access is requested.
casez ( (!i_cpsr_ff_t && (i_cpsr_ff_mode != USR) & (i_instruction[11:8] == 4'b1111) & (i_instruction[34:32] == 3'd0)) ? i_instruction[31:0] : 35'd0 )
casez ( (!i_cpsr_ff_t && (i_instruction[34:32] == 3'd0) && i_valid) ? i_instruction[31:0] : 35'd0 )
MRC, MCR, LDC, STC, CDP:
begin
// Send ANDNV R0, R0, R0 instruction.
o_instruction = {4'b1111, 28'd0};
o_valid = 1'd0;
o_irq = 1'd0;
o_fiq = 1'd0;
if ( i_instruction[11:8] == 4'b1111 && i_cpsr_ff_mode != USR ) // CP15 and root access -- perfectly fine.
begin
// Send ANDNV R0, R0, R0 instruction.
o_instruction = {4'b1111, 28'd0};
o_valid = 1'd0;
o_irq = 1'd0;
o_fiq = 1'd0;
 
// As long as there is an instruction to process...
if ( i_pipeline_dav )
begin
// Do not impose any output. However, continue
// to stall all before this unit in the
// pipeline.
o_valid = 1'd0;
o_stall_from_decode = 1'd1;
cp_dav_nxt = 1'd0;
cp_word_nxt = 32'd0;
// As long as there is an instruction to process...
if ( i_pipeline_dav )
begin
// Do not impose any output. However, continue
// to stall all before this unit in the
// pipeline.
o_valid = 1'd0;
o_stall_from_decode = 1'd1;
cp_dav_nxt = 1'd0;
cp_word_nxt = 32'd0;
end
else
begin
// Prepare to move to BUSY. Continue holding
// stall. Send out 0s.
o_valid = 1'd0;
o_stall_from_decode = 1'd1;
cp_word_nxt = i_instruction;
cp_dav_nxt = 1'd1;
state_nxt = BUSY;
end
end
else
else // Warning...
begin
// Prepare to move to BUSY. Continue holding
// stall. Send out 0s.
o_valid = 1'd0;
o_stall_from_decode = 1'd1;
cp_word_nxt = i_instruction;
cp_dav_nxt = 1'd1;
state_nxt = BUSY;
`ifndef SYNTHESIS
 
if ( i_instruction[11:8] != 4'b1111 )
eclass = 1;
else
eclass = 2;
`endif
 
// Remain transparent since this is not a coprocessor
// instruction.
o_valid = i_valid;
o_instruction = i_instruction;
o_irq = i_irq;
o_fiq = i_fiq;
cp_dav_nxt = 0;
o_stall_from_decode = 0;
cp_word_nxt = {32{1'dx}}; // Don't care.
end
end
default:
/src/rtl/cpu/zap_predecode_mem_fsm.v
202,7 → 202,7
o_stall_from_decode = 1'd1;
 
// ORR DUMMY0, DUMMY0, 1 - Needed to indicate a switch
// to Thumb.
// to Thumb if needed.
o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd0, !i_cpsr_t};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
{o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
235,9 → 235,8
// Immediate Offset.
if ( i_instruction[31:25] == BLX1[31:25] && i_instruction_valid )
begin
`ifdef LDM_DEBUG
$display($time, "%m: BLX1 detected!");
`endif
 
// We must generate a SUBAL LR,PC,4 ROR 0
// This makes LR have the value
// PC+8-4=PC+4 which is the address of
255,9 → 254,8
end
else if ( i_instruction[27:4] == BLX2[27:4] && i_instruction_valid ) // BLX2 detected. Register offset. CONDITIONAL.
begin
`ifdef LDM_DEBUG
$display($time, "%m: BLX2 detected!");
`endif
 
// Write address of next instruction to LR. Now this
// depends on the mode we're in. Mode in the sense
// ARM/Thumb. We need to look at i_cpsr_t.
/src/rtl/cpu/zap_shifter_main.v
388,6 → 388,14
`ifdef SH_DEBUG
$display($time, "%m: => It is an immediate value.");
`endif
end
else if ( index_from_issue == PHY_PC )
begin
resolve_conflict = i_pc_plus_8_ff;
 
`ifdef SH_DEBUG
$display($time, "%m: => Giving PC");
`endif
end
else if ( index_from_this_stage == index_from_issue[$clog2(PHY_REGS)-1:0] && result_from_alu_valid )
begin
/src/rtl/cpu/zap_thumb_decoder.v
108,6 → 108,7
.i_instruction_valid(i_instruction_valid),
.i_irq(i_irq),
.i_fiq(i_fiq),
.i_offset(o_instruction[11:0]),
.i_cpsr_ff_t(i_cpsr_ff_t),
.o_instruction(instruction_nxt),
.o_instruction_valid(instruction_valid_nxt),
/src/scripts/makefile
20,6 → 20,7
.PHONY: dirs
.PHONY: cleanall
 
ARCH := armv4t
TC := $(shell basename `pwd`)
GCC_PATH := ../../../obj/gcc-arm-none-eabi-*/bin/
SCRIPT_PATH := ../../scripts/
30,8 → 31,8
COBJFILES := $(patsubst %.c,../../../obj/ts/$(TC)/%_c.o,$(C_FILES))
AOBJFILES := $(patsubst %.s,../../../obj/ts/$(TC)/%_s.o,$(S_FILES))
GCC_SRC := ../../../sw/gcc-arm-none-eabi-*-linux.tar.*
CFLAGS := -c -msoft-float -mfloat-abi=soft -march=armv4t -g
SFLAGS := -mcpu=arm7tdmi -g
CFLAGS := -c -msoft-float -mfloat-abi=soft -march=$(ARCH) -g
SFLAGS := -march=$(ARCH) -g
LFLAGS := -T
OFLAGS := -O binary
CC := $(GCC_PATH)/arm-none-eabi-gcc
86,7 → 87,7
rm -rfv ../../../obj/ts/$(TC)/../../gcc-arm-none-*
 
c2asm:
$(CC) -S $(CFLGAS) $(X) -o ../../../obj/ts/$(TC)/$(X).asm
$(CC) -S $(CFLAGS) $(X) -o ../../../obj/ts/$(TC)/$(X).asm
 
print-% : ; @echo $* = $($*)
 
/src/scripts/run_sim.pl
9,6 → 9,7
Usage :
perl run_sim.pl
+test+<test_case> -- Run a specific test case.
+irq_en -- Configure TB to use IRQ.
 
###############################################################################
";
30,6 → 31,7
my $TLB_DEBUG = $Config{'DEFINE_TLB_DEBUG'};
my $STALL = $Config{'ALLOW_STALLS'};
my $TX_TERM = $Config{'UART_TX_TERMINAL'};
my $IRQ_EN = $Config{'IRQ_EN'};
 
# System configuration.
my $DATA_CACHE_SIZE = $Config{'DATA_CACHE_SIZE'};
48,7 → 50,6
my $ZAP_HOME = "../../../";
my $TEST = "null";
my $SCRATCH = "/dev/null";
my $IRQ_EN = 0;
my $FIQ_EN = 0;
 
if ( $SEED == -1 ) {
108,9 → 109,9
$IVL_OPTIONS .= " -Pzap_test.CODE_CACHE_SIZE=$CODE_CACHE_SIZE ";
$IVL_OPTIONS .= "-DMAX_CLOCK_CYCLES=$MAX_CLOCK_CYCLES ";
 
if ( $IRQ_EN ) { $IVL_OPTIONS .= "-DIRQ_EN "; }
if ( $IRQ_EN ) { print "Script: IRQ defined.\n" ; $IVL_OPTIONS .= "-DIRQ_EN "; }
if ( $FIQ_EN ) { $IVL_OPTIONS .= "-DFIQ_EN "; }
if ( $STALL ) { $IVL_OPTIONS .= "-DSTALL "; }
if ( $STALL ) { print "Script: Stall defined.\n" ; $IVL_OPTIONS .= "-DSTALL "; }
if ( $SYNTHESIS ) { $IVL_OPTIONS .= "-DSYNTHESIS ";}
 
if ( $MAX_CLOCK_CYCLES == 0 ) { die "*E: MAX_CLOCK_CYCLES set to 0. Ending script..."; }
/src/testbench/cpu/zap_tb.v
103,12 → 103,15
$display("parameter START %d", START );
$display("parameter COUNT %d", COUNT );
$display("parameter FIFO_DEPTH %d", u_zap_top.FIFO_DEPTH);
 
`ifdef STALL
$display("STALL defined!");
`endif
 
`ifdef TLB_DEBUG
$display("TLB_DEBUG defined!");
`endif
 
$display("parameter DATA_SECTION_TLB_ENTRIES = %d", DATA_SECTION_TLB_ENTRIES ) ;
$display("parameter DATA_LPAGE_TLB_ENTRIES = %d", DATA_LPAGE_TLB_ENTRIES ) ;
$display("parameter DATA_SPAGE_TLB_ENTRIES = %d", DATA_SPAGE_TLB_ENTRIES ) ;
149,7 → 152,13
(
.i_clk(i_clk),
.i_reset(i_reset),
.i_irq(global_irq),
 
`ifdef IRQ_EN
.i_irq(global_irq),
`else
.i_irq(1'd0),
`endif
 
.i_fiq(1'd0),
.o_wb_cyc(data_wb_cyc),
.o_wb_stb(data_wb_stb),
/src/ts/arm_test/Config.cfg
16,6 → 16,7
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
IRQ_EN => 0,
UART_TX_TERMINAL => 0, # Disable UART TX terminal.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
/src/ts/factorial/Config.cfg
16,13 → 16,14
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
UART_TX_TERMINAL => 0,
IRQ_EN => 1, # Enable IRQs.
UART_TX_TERMINAL => 0, # No UART terminal.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
DUMP_SIZE => 200, # Length of dump in bytes.
MAX_CLOCK_CYCLES => 100000, # Clock cycles to run the simulation for.
ALLOW_STALLS => 1, # Make this 1 to allow external RAM to signal a stall.
ALLOW_STALLS => 0, # Make this 1 to allow external RAM to signal a stall.
DEFINE_TLB_DEBUG => 0, # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
REG_CHECK => {}, # Registers to examine.
FINAL_CHECK => {
/src/ts/factorial/factorial.s
190,12 → 190,12
ldr r1, =#0x0 // Prepare mask value
str r1, [r0] // Unmask all interrupt sources.
 
// Program timer peripheral to tick every 255 clock cycles.
// Program timer peripheral to tick every 32 clock cycles.
ldr r0 ,=#0xFFFFFFC0 // Timer base address.
ldr r1 ,=#1
str r1, [r0] // Enable timer
add r0, r0, #4
ldr r1, =#255
ldr r1, =#32
str r1, [r0] // Program to 255 clocks.
add r0, r0, #8
ldr r1, =#0x1
/src/ts/thumb_test/Config.cfg
16,6 → 16,7
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
IRQ_EN => 0,
UART_TX_TERMINAL => 0, # 1 will open a UART TX terminal.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
/src/ts/uart_tx/Config.cfg
16,6 → 16,7
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
IRQ_EN => 0,
UART_TX_TERMINAL => 1, # Show TX terminal.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
/src/ts/uart_tx/main.c
1,11 → 1,14
#include "uart.h"
 
char* str = "Hello World";
char* str = "Hello\n";
 
int main(void)
{
int i;
 
UARTInit();
UARTWrite(str);
UARTWrite("World");
return 0;
}
 

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