URL
https://opencores.org/ocsvn/zap/zap/trunk
Subversion Repositories zap
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- This comparison shows the changes necessary to convert path
/zap/trunk
- from Rev 8 to Rev 7
- ↔ Reverse comparison
Rev 8 → Rev 7
/ZAP/README.md
1,4 → 1,4
## *ZAP* : ARM compatible core with cache and MMU (ARMv4T ISA compatible) |
## *ZAP* : An open source ARMv4T processor with cache and MMU |
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#### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com) |
#### License : GPL v2 |
8,7 → 8,7
ZAP is a pipelined ARM processor core that can execute the ARMv4T instruction |
set. It is equipped with ARMv4 compatible split writeback caches and memory |
management capabilities. ARMv4 and Thumbv1 instruction sets are supported. |
The processor core uses a 9 stage pipeline. |
The processor core uses an 8 stage pipeline. |
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### Current Status |
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29,7 → 29,7
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### Pipeline Overview : |
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FETCH => FIFO => PRE-DECODE => DECODE => ISSUE => SHIFTER => ALU => MEMORY => WRITEBACK |
FETCH => PRE-DECODE => DECODE => ISSUE => SHIFTER => ALU => MEMORY => WRITEBACK |
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The pipeline is fully bypassed to allow most dependent instructions to execute |
without stalls. The pipeline stalls for 3 cycles if there is an attempt to |
48,7 → 48,9
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### To simulate using Icarus Verilog |
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Enter *hw/sim* and run *run_sim_gui.pl* |
Enter *hw/sim* and run *csh sample\_command.csh* from the terminal. The command |
will run the factorial test case (see sw/factorial). Ensure that you have |
GTKWave installed at your site. |
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### License |
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