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## NOTE: This project was designed by me as a part of a student design contest. It is no longer actively supported.
## This project's files are hosted on GitHub.
## The ZAP ARM Processor (ARMv5T Compatible, FPGA Synthesizable Soft Processor) @ https://github.com/krevanth/ZAP.git
## The ZAP ARMv5T Processor
 
### Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)
To install the project on your system (including HDL files, documentation, test cases etc) do:
 
### Introduction
````bash
./install.sh
````
 
The ZAP processor is a 10 stage pipelined processor for FPGA with support for cache and MMU (ARMv5T compliant).
-------------------------------------------------------------------------------
 
Please note that the processor is *not* an ARM clone but a completely different RTL design, written from scratch (in FPGA compliant Verilog-2001), that can run ARM v5T binaries (both user and kernel code), hence, no particular ARMX number is specified.
Copyright (C) Revanth Kamaraj
 
This project was originally created for the ORCONF-2016 Student Design Contest.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
ZAP is specifically designed to work with FPGAs. To keep the code generic across FPGA vendors, inference based coding style is followed.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
![Wishbone logo](https://wishbone-interconnect.readthedocs.io/en/latest/_images/wishbone_stamp.svg)
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 
#### Repos
 
This project is hosted on Github.
 
GIT: https://github.com/krevanth/ZAP
 
#### Features
 
##### ZAP Processor (zap_top.v)
 
The ZAP core is a pipelined ATMv5T processor for FPGA.
 
| Property | Description |
|-----------------------|-------------------------|
|HDL | Verilog-2001 |
|Author | Revanth Kamaraj |
|ARM v5T ISA Support | Fully compatible |
|Branch Predictor | Direct mapped bimodal |
|Write Buffer | Yes |
|Abort Model | Base Restored |
|Integrated v5T CP15 | Yes |
|External Coproc. Bus | No |
|Cache Interface | 128-Bit custom interface|
|26-Bit Support | No |
|L1 Code Cache | Direct mapped virtual |
|L1 Data Cache | Direct mapped virtual |
|Cache Write Policy | Writeback |
|L1 Code TLB | Direct mapped |
|L1 Data TLB | Direct mapped |
|Bus Interface | 32-bit Wishbone B3 Linear incrementing burst |
|Cache/TLB Lock Support | No |
|CP15 Compliance | v5T (No fine pages) |
|FCSE Support | Yes |
|Cache Read Speed (Hit) | 320MB/s @ 80MHz CLK |
|Cache Write Speed(Hit) | 160MB/s @ 80MHz CLK |
|Cache Line Size | 16B |
 
* 10-stage pipeline design. Pipeline has extensive bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
* 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
* Instructions of ALU + Shift can allow execution of subsequent commands with dependencies if the subsequent command doesn't use the shifter. This is done by having a dual feedback network.
* The core is specifically designed for use in FGPA and relies on FGPA inference to allow portability across FPGA vendors.
 
#### CPU Configuration (zap_top.v)
 
| Parameter | Default| Description |
|--------------------------|--------|-------------|
| BP_ENTRIES | 1024 | Branch Predictor Settings. Predictor RAM depth. Must be 2^n and > 2 |
| FIFO_DEPTH | 4 | Branch Predictor Settings. Command FIFO depth. Must be 2^n and > 2 |
| STORE_BUFFER_DEPTH | 16 | Branch Predictor Settings. Depth of the store buffer. Must be 2^n and > 2 |
| DATA_SECTION_TLB_ENTRIES | 4 | Data Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0) |
| DATA_LPAGE_TLB_ENTRIES | 8 | Data Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0) |
| DATA_SPAGE_TLB_ENTRIES | 16 | Data Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0) |
| DATA_CACHE_SIZE | 1024 | Data Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n |
| CODE_SECTION_TLB_ENTRIES | 4 | Instruction Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0) |
| CODE_LPAGE_TLB_ENTRIES | 8 | Instruction Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0) |
| CODE_SPAGE_TLB_ENTRIES | 16 | Instruction Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0) |
| CODE_CACHE_SIZE | 1024 | Instruction Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n |
 
#### CPU IO Interface (zap_top.v)
Wishbone B3 compatible 32-bit bus.
 
| Dir | Size | Port | Description |
|---------------|----------|--------------------|----------------------------------|
| input | | i_clk | Clock |
| input | | i_reset | Reset |
| input | | i_irq | Interrupt. Level Sensitive. |
| input | | i_fiq | Fast Interrupt. Level Sensitive.|
| output | | o_wb_cyc | Wishbone B3 Signal |
| output | | o_wb_stb | WIshbone B3 signal |
| output | [31:0] | o_wb_adr | Wishbone B3 signal. |
| output | | o_wb_we | Wishbone B3 signal. |
| output | [31:0] | o_wb_dat | Wishbone B3 signal. |
| output | [3:0] | o_wb_sel | Wishbone B3 signal. |
| output | [2:0] | o_wb_cti | Wishbone B3 signal. Cycle Type Indicator (Supported modes: Incrementing Burst, End of Burst) |
| output | [1:0] | o_wb_bte | Wishbone B3 signal. Burst Type Indicator (Supported modes: Linear) |
| input | | i_wb_ack | Wishbone B3 signal. |
| input | [31:0] | i_wb_dat | Wishbone B3 signal. |
| output | | o_wb_stb_nxt | IGNORE THIS PORT. LEAVE OPEN. |
| output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. |
| output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. |
 
### Installation and Directory Structure (GIT)
 
To get the files of the ZAP processor, please execute:
 
```bash
git pull https://github.com/krevanth/ZAP.git
```
 
This should provide the following file structure:
 
 
 
├── LICENSE
├── makefile
├── README.md
└── src
├── rtl
│   └── cpu
│   ├── zap_alu_main.v
│   ├── zap_cache_fsm.v
│   ├── zap_cache_tag_ram.v
│   ├── zap_cache.v
│   ├── zap_core.v
│   ├── zap_cp15_cb.v
│   ├── zap_decode_main.v
│   ├── zap_decode.v
│   ├── zap_decompile.v
│   ├── zap_defines.vh
│   ├── zap_fetch_main.v
│   ├── zap_fifo.v
│   ├── zap_functions.vh
│   ├── zap_issue_main.v
│   ├── zap_localparams.vh
│   ├── zap_mem_inv_block.v
│   ├── zap_memory_main.v
│   ├── zap_predecode_compress.v
│   ├── zap_predecode_coproc.v
│   ├── zap_predecode_main.v
│   ├── zap_predecode_mem_fsm.v
│   ├── zap_ram_simple.v
│   ├── zap_register_file.v
│   ├── zap_shifter_main.v
│   ├── zap_shifter_multiply.v
│   ├── zap_shift_shifter.v
│   ├── zap_sync_fifo.v
│   ├── zap_thumb_decoder.v
│   ├── zap_tlb_check.v
│   ├── zap_tlb_fsm.v
│   ├── zap_tlb.v
│   ├── zap_top.v
│   ├── zap_wb_adapter.v
│   ├── zap_wb_merger.v
│   └── zap_writeback.v
├── scripts
│   ├── bin2vlog.pl
│   ├── Config.cfg_template
│   ├── makefile
│   ├── run_sim.pl
│   └── uart_input.pl
├── testbench
│   ├── chip_top.v
│   ├── External_IP
│   │   └── uart16550
│   │   ├── doc
│   │   │   ├── CHANGES.txt
│   │   │   ├── src
│   │   │   │   └── UART_spec.doc
│   │   │   └── UART_spec.pdf
│   │   └── rtl
│   │   ├── raminfr.v
│   │   ├── uart_debug_if.v
│   │   ├── uart_defines.v
│   │   ├── uart_receiver.v
│   │   ├── uart_regs.v
│   │   ├── uart_rfifo.v
│   │   ├── uart_sync_flops.v
│   │   ├── uart_tfifo.v
│   │   ├── uart_top.v
│   │   ├── uart_transmitter.v
│   │   └── uart_wb.v
│   ├── ram.v
│   ├── timer.v
│   ├── uart_rx_logger.v
│   ├── uart_tx_dumper.v
│   ├── vic.v
│   └── zap_tb.v
└── ts
├── arm_test
│   ├── arm_test.c
│   ├── arm_test.ld
│   ├── arm_test.s
│   ├── Config.cfg
│   ├── Description.txt
│   └── makefile
├── factorial
│   ├── Config.cfg
│   ├── Description.txt
│   ├── factorial.c
│   ├── factorial.ld
│   ├── factorial.s
│   └── makefile
├── makefile
├── thumb_test
│   ├── Config.cfg
│   ├── Description.txt
│   ├── linker.ld
│   ├── main.c
│   ├── makefile
│   └── thumb.s
└── uart
├── Config.cfg
├── Description.txt
├── irq_handler.c
├── main.c
├── makefile
├── uart.c
├── uart.h
├── uart.ld
└── uart.s
 
### Run Sample Tests
 
*Tested on Ubuntu 16.04 LTS/18.04 LTS*
 
Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
 
```bash
sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd
sudo apt-get install iverilog gtkwave make perl xterm
cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
make # Runs the test using IVerilog.
cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
gvim zap.log.gz # View the log file
gtkwave zap.vcd.gz # Exists if selected by Config.cfg of that test case.
```
To use this processor in your SOC, instantiate this top level CPU module in your project: /src/rtl/cpu/zap_top.v
 
### FPGA Timing Performance (Vivado, Retime Enabled)
 
| FPGA Part | Speed | Critical Path |
|--------------------|-------|----------------|
| xc7a35tiftg256-1L | 80MHz | Cache access |
 
### License
 
 
GNU GENERAL PUBLIC LICENSE
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51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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/trunk/install.sh
0,0 → 1,2
#!/bin/bash
git pull https://github.com/krevanth/ZAP.git
trunk/install.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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