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Rev 39 → Rev 40
/zap/trunk/doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf
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/zap/trunk/src/doc/zap_ug.tex
227,6 → 227,7
# from a synthesis perspective. |
|
# Testbench configuration. |
IRQ_EN => 1, # 1 Enables VIC connection to CPU in testbench. |
UART_TX_TERMINAL => 0, # 1 Enables UART TX terminal. 0 disables it. |
EXT_RAM_SIZE => 32768, # External RAM size in bytes. |
SEED => -1, # Seed. Use -1 to use random seed. |