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URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

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  • This comparison shows the changes necessary to convert path
    /zap/trunk
    from Rev 33 to Rev 34
    Reverse comparison

Rev 33 → Rev 34

/doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/src/doc/zap_ug.tex
227,6 → 227,7
# from a synthesis perspective.
 
# Testbench configuration.
UART_TX_TERMINAL => 0, # 1 Enables UART TX terminal. 0 disables it.
EXT_RAM_SIZE => 32768, # External RAM size in bytes.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/rtl/cpu/zap_fetch_main.v
173,8 → 173,9
// PC is pumped down the pipeline.
o_pc_ff <= i_pc_ff;
 
// Instruction.
o_instruction <= i_instruction;
// Instruction. If 16-bit aligned address, move data from
// cache by 16-bit to focus on the instruction.
o_instruction <= i_pc_ff[1] ? i_instruction >> 16 : i_instruction;
end
else
begin
183,6 → 184,19
end
end
 
`ifndef SYNTHESIS
 
always @ (negedge i_clk)
begin
if ( i_pc_ff[0] != 1'd0 )
begin
$display($time, ": Error: PC LSB isn't zero. This is not legal! (Module_Src = %m)");
$finish;
end
end
 
`endif
 
// ----------------------------------------------------------------------------
 
//
/src/rtl/cpu/zap_thumb_decoder.v
172,5 → 172,16
end
end
 
`ifndef SYNTHESIS
 
// Helpful for debug.
zap_decompile u_zap_decompile (
.i_instruction(o_instruction),
.i_dav(o_instruction_valid),
.o_decompile()
);
 
`endif
 
endmodule
`default_nettype wire
/src/rtl/cpu/zap_top.v
296,8 → 296,8
u_code_cache (
.i_clk (i_clk),
.i_reset (reset),
.i_address (cpu_iaddr),
.i_address_nxt (cpu_iaddr_nxt),
.i_address (cpu_iaddr & 32'hFFFF_FFFC), // Cut off lower 2 bits.
.i_address_nxt (cpu_iaddr_nxt & 32'hFFFF_FFFC), // Cut off lower 2 bits.
 
.i_rd (cpu_instr_stb),
.i_wr (1'd0),
/src/scripts/Config.cfg_template
16,6 → 16,7
SYNTHESIS => 1, # Make this to 1 to simulate compile from a synthesis perspective.
 
# Testbench configuration.
UART_TX_TERMINAL => 1, # 1 Enables UART TX terminal. 0 disables it.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/scripts/run_sim.pl
29,6 → 29,7
my $MAX_CLOCK_CYCLES = $Config{'MAX_CLOCK_CYCLES'};
my $TLB_DEBUG = $Config{'DEFINE_TLB_DEBUG'};
my $STALL = $Config{'ALLOW_STALLS'};
my $TX_TERM = $Config{'UART_TX_TERMINAL'};
 
# System configuration.
my $DATA_CACHE_SIZE = $Config{'DATA_CACHE_SIZE'};
92,7 → 93,13
$IVL_OPTIONS .= " $ZAP_HOME/src/rtl/*/*.v $ZAP_HOME/src/testbench/cpu/*.v -o $VVP_PATH -gstrict-ca-eval -Wall -g2001 -Winfloop -DSEED=$SEED -DMEMORY_IMAGE=\\\"$PROG_PATH\\\" ";
 
$IVL_OPTIONS .= " -DVCD_FILE_PATH=\\\"$VCD_PATH\\\" ";
$IVL_OPTIONS .= " -DUART_FILE_PATH=\\\"$UART_PATH\\\" ";
 
if ( $TX_TERM) {
$IVL_OPTIONS .= " -DUART_FILE_PATH=\\\"$UART_PATH\\\" ";
} else {
$IVL_OPTIONS .= " -DUART_FILE_PATH=\\\"/dev/null\\\" ";
}
 
$IVL_OPTIONS .= " -Pzap_test.RAM_SIZE=$RAM_SIZE -Pzap_test.START=$DUMP_START -Pzap_test.COUNT=$DUMP_SIZE -DLINUX -Pzap_test.STORE_BUFFER_DEPTH=$SBUF_DEPTH ";
$IVL_OPTIONS .= " -Pzap_test.BP_ENTRIES=$BP -Pzap_test.FIFO_DEPTH=$FIFO ";
$IVL_OPTIONS .= " -Pzap_test.DATA_SECTION_TLB_ENTRIES=$DATA_SECTION_TLB_ENTRIES ";
134,15 → 141,19
print "*I: Rand is $SEED...\n";
print "iverilog $IVL_OPTIONS\n";
 
system("rm -f $UART_PATH"); # Remove UART file.
system("mknod $UART_PATH p"); # Create a UART output FIFO file.
if ( $TX_TERM ) {
system("rm -f $UART_PATH"); # Remove UART file.
system("mknod $UART_PATH p"); # Create a UART output FIFO file.
}
 
# UART output monitor.
die "Error: XTerm could not be found!" if system("which xterm");
die "Error: Icarus Verilog could not be found!" if system("which iverilog");
 
print "Setting up UART output monitor";
system("xterm -T 'TB UART Output' -hold -e 'cat $UART_PATH ; echo ; echo ------------------ ; echo UART_Output_Complete ; echo ------------------' &");
if ( $TX_TERM == 1 ) {
print "Setting up UART output monitor\n";
system("xterm -T 'TB UART Output' -hold -e 'cat $UART_PATH ; echo ; echo ------------------ ; echo UART_Output_Complete ; echo ------------------' &");
}
 
die "*E: Verilog Compilation Failed!\n" if system("iverilog $IVL_OPTIONS");
die "*E: VVP execution error!\n" if system("vvp $VVP_PATH | tee $LOG_FILE_PATH");
/src/ts/uart/uart.ld File deleted
/src/ts/uart/uart.c File deleted
/src/ts/uart/uart.s File deleted
/src/ts/uart/makefile File deleted
/src/ts/uart/uart.h File deleted
/src/ts/uart/main.c File deleted
/src/ts/arm_test/Config.cfg
16,6 → 16,7
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
UART_TX_TERMINAL => 0, # Disable UART TX terminal.
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.
/src/ts/factorial/Config.cfg
16,6 → 16,7
SYNTHESIS => 0, # 0 allows debug messages.
 
# Testbench configuration.
UART_TX_TERMINAL => 0,
EXT_RAM_SIZE => 32768, # External RAM size.
SEED => -1, # Seed. Use -1 to use random seed.
DUMP_START => 2000, # Starting memory address from which to dump.

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