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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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  • This comparison shows the changes necessary to convert path 
    /zipcpu/trunk/bench/cpp
    from Rev 39 to Rev 36
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  •

Rev 39 → Rev 36

/zippy_tb.cpp
43,7 → 43,6
 
#include "verilated.h"
#include "Vzipsystem.h"
#include "cpudefs.h"
 
#include "testb.h"
// #include "twoc.h"
185,18 → 184,18
int ln= 0;
 
mvprintw(ln,0, "Peripherals-SS"); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
printw(" %s",
// (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":" ",
(m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":" "
);
#endif
 
#ifdef OPT_EARLY_BRANCHING
printw(" %s%s",
/*
printw(" %s%s%s",
(m_core->v__DOT__thecpu__DOT__ill_err)?"IL":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ");
#endif
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ",
);
*/
/*
showval(ln, 1, "TRAP", m_core->v__DOT__trap_data);
306,9 → 305,6
attroff(A_BOLD);
ln+=1;
 
#ifdef OPT_SINGLE_FETCH
ln+=2;
#else
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x",
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr,
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv,
329,7 → 325,6
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ",
(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
(m_core->v__DOT__wb_data)); ln++;
#endif
 
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY"
341,17 → 336,7
(m_core->v__DOT__thecpu__DOT__mem_data),
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ",
(m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":" ",
(m_core->v__DOT__thecpu__DOT__mem_result));
// #define OPT_PIPELINED_BUS_ACCESS
#ifdef OPT_PIPELINED_BUS_ACCESS
printw(" %x%x%c%c",
(m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
(m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
(m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
(mem_pipe_stalled())?'S':'-'); ln++;
#else
ln++;
#endif
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++;
 
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
363,40 → 348,7
(m_core->i_wb_ack)?"ACK":" ",
(m_core->i_wb_stall)?"STL":" ",
(m_core->i_wb_data)); ln+=2;
#ifdef OPT_PIPELINED_BUS_ACCESS
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
(m_core->v__DOT__thecpu__DOT__mem_ce),
(m_core->v__DOT__thecpu__DOT__master_ce),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
(!m_core->v__DOT__thecpu__DOT__clear_pipeline),
(m_core->v__DOT__thecpu__DOT__set_cond),
(!m_core->v__DOT__thecpu__DOT__mem_stalled),
 
(m_core->v__DOT__thecpu__DOT__mem_stalled),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
(m_core->v__DOT__thecpu__DOT__master_ce),
(mem_pipe_stalled()),
(!m_core->v__DOT__thecpu__DOT__op_pipe),
(m_core->v__DOT__thecpu__DOT__mem_busy));
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
(m_core->v__DOT__thecpu__DOT__dcdvalid),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
(m_core->v__DOT__thecpu__DOT__dcdM),
(!((m_core->v__DOT__thecpu__DOT__dcdOp
^m_core->v__DOT__thecpu__DOT__opn)&1)),
(m_core->v__DOT__thecpu__DOT__dcdB
== m_core->v__DOT__thecpu__DOT__op_B),
(m_core->v__DOT__thecpu__DOT__r_dcdI
== m_core->v__DOT__thecpu__DOT__r_opI),
(m_core->v__DOT__thecpu__DOT__r_dcdI+1
== m_core->v__DOT__thecpu__DOT__r_opI));
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
(m_core->v__DOT__thecpu__DOT__r_dcdI),
(m_core->v__DOT__thecpu__DOT__r_opI));
#endif
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
 
 
showins(ln, "I ",
!m_core->v__DOT__thecpu__DOT__dcd_stalled,
m_core->v__DOT__thecpu__DOT__pf_valid,
412,13 → 364,6
m_core->v__DOT__thecpu__DOT__dcd_gie,
m_core->v__DOT__thecpu__DOT__dcd_stalled,
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
mvprintw(ln-1,10,"I");
else
#endif
if (m_core->v__DOT__thecpu__DOT__dcdM)
mvprintw(ln-1,10,"M");
 
showins(ln, "Op",
m_core->v__DOT__thecpu__DOT__op_ce,
425,16 → 370,7
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
op_pc()); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
if (m_core->v__DOT__thecpu__DOT__op_illegal)
mvprintw(ln-1,10,"I");
else
#endif
if (m_core->v__DOT__thecpu__DOT__opvalid_mem)
mvprintw(ln-1,10,"M");
else if (m_core->v__DOT__thecpu__DOT__opvalid_alu)
mvprintw(ln-1,10,"A");
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
 
showins(ln, "Al",
m_core->v__DOT__thecpu__DOT__alu_ce,
441,11 → 377,9
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
m_core->v__DOT__thecpu__DOT__alu_gie,
m_core->v__DOT__thecpu__DOT__alu_stall,
alu_pc()); ln++;
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
mvprintw(ln-1,10,"W");
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
 
mvprintw(ln-5, 65,"%s %s",
mvprintw(ln-5, 48,"%s %s",
(m_core->v__DOT__thecpu__DOT__op_break)?"OB":" ",
(m_core->v__DOT__thecpu__DOT__clear_pipeline)?"CLRP":" ");
mvprintw(ln-4, 48,
481,7 → 415,7
(m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":" ",
(m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
(m_core->v__DOT__thecpu__DOT__mem_stalled)?"PIPE":" ",
(m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
(m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV":" ",
zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
}
 
665,7 → 599,7
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
op_pc()); ln++;
m_core->v__DOT__thecpu__DOT__op_pc-1); ln++;
 
showins(ln, "Al",
m_core->v__DOT__thecpu__DOT__alu_ce,
672,7 → 606,7
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
m_core->v__DOT__thecpu__DOT__alu_gie,
m_core->v__DOT__thecpu__DOT__alu_stall,
alu_pc()); ln++;
m_core->v__DOT__thecpu__DOT__alu_pc-1); ln++;
}
void tick(void) {
int gie = m_core->v__DOT__thecpu__DOT__gie;
726,7 → 660,7
m_core->v__DOT__thecpu__DOT__dcd_ce,
m_core->v__DOT__thecpu__DOT__dcd_pc,
m_core->v__DOT__thecpu__DOT__op_ce,
op_pc(),
m_core->v__DOT__thecpu__DOT__op_pc,
m_core->v__DOT__thecpu__DOT__dcdA,
m_core->v__DOT__thecpu__DOT__opR,
m_core->v__DOT__cmd_halt,
817,13 → 751,13
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
op_pc());
m_core->v__DOT__thecpu__DOT__op_pc-1);
dbgins("Al - ",
m_core->v__DOT__thecpu__DOT__alu_ce,
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
m_core->v__DOT__thecpu__DOT__alu_gie,
m_core->v__DOT__thecpu__DOT__alu_stall,
alu_pc());
m_core->v__DOT__thecpu__DOT__alu_pc-1);
 
}
}
833,43 → 767,10
&&(m_core->v__DOT__thecpu__DOT__sleep));
}
 
unsigned op_pc(void) {
/*
unsigned r = m_core->v__DOT__thecpu__DOT__dcd_pc-1;
if (m_core->v__DOT__thecpu__DOT__dcdvalid)
r--;
return r;
*/
return m_core->v__DOT__thecpu__DOT__op_pc-1;
}
 
unsigned alu_pc(void) {
/*
unsigned r = op_pc();
if (m_core->v__DOT__thecpu__DOT__opvalid)
r--;
return r;
*/
return m_core->v__DOT__thecpu__DOT__alu_pc-1;
}
 
#ifdef OPT_PIPELINED_BUS_ACCESS
int mem_pipe_stalled(void) {
int r = 0;
r = ((m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)
||(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl));
r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
||(
((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
&&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
return r;
// return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
}
#endif
 
bool test_failure(void) {
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
&&(m_mem[alu_pc()] == 0x2f0f7fff)
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1]
== 0x2f0f7fff)
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
}
 
1216,7 → 1117,7
halted = true;
erase();
break;
case 's':
case 's': case 'S':
if (!halted)
erase();
tb->wb_write(CMD_REG, CMD_STEP);
1223,30 → 1124,10
manual = false;
halted = true;
break;
case 'S':
case 't': case 'T':
if ((!manual)||(halted))
erase();
manual = true;
halted = true;
tb->m_core->v__DOT__cmd_halt = 0;
tb->m_core->v__DOT__cmd_step = 1;
tb->eval();
tb->tick();
break;
case 'T': //
if ((!manual)||(halted))
erase();
manual = true;
halted = true;
tb->m_core->v__DOT__cmd_halt = 1;
tb->m_core->v__DOT__cmd_step = 0;
tb->eval();
tb->tick();
break;
case 't':
if ((!manual)||(halted))
erase();
manual = true;
halted = false;
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
// tb->m_core->v__DOT__cmd_halt = 0;
/Makefile
39,8 → 39,7
CXX := g++
FLAGS := -Wall -Og -g
ZASM := ../../sw/zasm
RTLD := ../../rtl
INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include -I../../sw/zasm
INCS := -I../../rtl/obj_dir/ -I/usr/share/verilator/include -I../../sw/zasm
SOURCES := zippy_tb.cpp memsim.cpp twoc.cpp $(ZASM)/zopcodes.cpp $(ZASM)/zparser.cpp
RAWLIB := /usr/share/verilator/include/verilated.cpp ../../rtl/obj_dir/Vzipsystem__ALL.a
LIBS := $(RAWLIB) -lncurses
47,7 → 46,6
TESTF := ../../sw/zasm/z.out
 
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h
zippy_tb: $(RTLD)/cpudefs.h
$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@
 
.PHONY: stest

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