OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/bench/cpp
    from Rev 76 to Rev 75
    Reverse comparison

Rev 76 → Rev 75

/zippy_tb.cpp
67,30 → 67,6
 
#define MAXERR 10000
 
 
class SPARSEMEM {
public:
bool m_valid;
unsigned int m_a, m_d;
};
 
class ZIPSTATE {
public:
bool m_valid, m_gie, m_last_pc_valid;
unsigned int m_sR[16], m_uR[16];
unsigned int m_p[20];
unsigned int m_last_pc, m_pc, m_sp;
SPARSEMEM m_smem[5];
SPARSEMEM m_imem[5];
ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
 
void step(void) {
m_last_pc_valid = true;
m_last_pc = m_pc;
}
};
 
 
// No particular "parameters" need definition or redefinition here.
class ZIPPY_TB : public TESTB<Vzipsystem> {
public:
101,10 → 77,9
bool dbg_flag, bomb, m_show_user_timers;
int m_cursor;
unsigned long m_last_instruction_tickcount;
ZIPSTATE m_state;
 
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
if (false) {
if (true) {
dbg_fp = fopen("dbg.txt", "w");
dbg_flag = true;
} else {
140,99 → 115,6
return true;
}
 
void step(void) {
wb_write(CMD_REG, CMD_STEP);
m_state.step();
}
 
void read_raw_state(void) {
m_state.m_valid = false;
for(int i=0; i<16; i++)
m_state.m_sR[i] = cmd_read(i);
for(int i=0; i<16; i++)
m_state.m_uR[i] = cmd_read(i+16);
for(int i=0; i<20; i++)
m_state.m_p[i] = cmd_read(i+32);
 
m_state.m_gie = (m_state.m_sR[14] & 0x020);
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
 
if (m_state.m_last_pc_valid)
m_state.m_imem[0].m_a = m_state.m_last_pc;
else
m_state.m_imem[0].m_a = m_state.m_pc - 1;
m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
m_state.m_imem[1].m_a = m_state.m_pc;
m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
 
for(int i=1; i<4; i++) {
if (!m_state.m_imem[i].m_valid) {
m_state.m_imem[i+1].m_valid = false;
m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
continue;
}
m_state.m_imem[i+1].m_a = zop_early_branch(
m_state.m_imem[i].m_a,
m_state.m_imem[i].m_d);
m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
}
 
m_state.m_smem[0].m_a = m_state.m_sp;
for(int i=1; i<5; i++)
m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
for(int i=0; i<5; i++) {
m_state.m_smem[i].m_valid =
(m_state.m_imem[i].m_a > 0x10000);
m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
}
m_state.m_valid = true;
}
 
void read_raw_state_cheating(void) {
m_state.m_valid = false;
for(int i=0; i<16; i++)
m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
for(int i=0; i<16; i++)
m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__upc;
 
m_state.m_gie = (m_state.m_sR[14] & 0x020);
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
 
m_state.m_p[0] = m_core->v__DOT__pic_data;
m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
if (!m_show_user_timers) {
m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
} else {
m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
}
 
m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
 
m_state.m_p[ 8] = m_core->v__DOT__utc_data;
m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
m_state.m_p[10] = m_core->v__DOT__upc_data;
m_state.m_p[11] = m_core->v__DOT__uic_data;
 
m_state.m_p[12] = m_core->v__DOT__mtc_data;
m_state.m_p[13] = m_core->v__DOT__moc_data;
m_state.m_p[14] = m_core->v__DOT__mpc_data;
m_state.m_p[15] = m_core->v__DOT__mic_data;
 
}
 
void showval(int y, int x, const char *lbl, unsigned int v, bool c) {
if (c)
mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
249,33 → 131,29
}
 
void showreg(int y, int x, const char *n, int r, bool c) {
if (r < 16)
dispreg(y, x, n, m_state.m_sR[r], c);
// 4,4,8,1 = 17 of 20, +3 = 19
if (c)
mvprintw(y, x, ">%s> 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
else
dispreg(y, x, n, m_state.m_uR[r-16], c);
move(y,x+17);
 
mvprintw(y, x, " %s: 0x%08x", n, m_core->v__DOT__thecpu__DOT__regset[r]);
#ifdef OPT_PIPELINED
addch( ((r == (int)(dcdA()&0x01f))&&(dcdvalid())
addch( ((r == (int)(dcdA()&0x01f))
&&(dcdvalid())
&&(m_core->v__DOT__thecpu__DOT__dcdA_rd))
?'a':((c)?'<':' '));
addch( ((r == (int)(dcdB()&0x01f))&&(dcdvalid())
addch( ((r == (int)(dcdB()&0x01f))
&&(dcdvalid())
&&(m_core->v__DOT__thecpu__DOT__dcdB_rd))
?'b':' ');
?'b':((c)?'<':' '));
#endif
addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
?'W':' ');
#else
addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
?'W':((c)?'<':' '));
#endif
}
 
void showins(int y, const char *lbl, const int ce, const int valid,
const int gie, const int stall, const unsigned int pc,
const bool phase) {
char la[80], lb[80];
const int gie, const int stall, const unsigned int pc) {
char line[80];
 
if (ce)
mvprintw(y, 0, "Ck ");
290,11 → 168,8
if (valid) {
if (gie) attroff(A_BOLD);
else attron(A_BOLD);
zipi_to_string(m_mem[pc], la, lb);
if ((phase)||((m_mem[pc]&0x80000000)==0))
printw(" %-24s", la);
else
printw(" %-24s", lb);
zipi_to_string(m_mem[pc], line);
printw(" %-24s", &line[1]);
} else {
attroff(A_BOLD);
printw(" (0x%08x)%28s", m_mem[pc],"");
303,9 → 178,8
}
 
void dbgins(const char *lbl, const int ce, const int valid,
const int gie, const int stall, const unsigned int pc,
const bool phase, const bool illegal) {
char la[80], lb[80];
const int gie, const int stall, const unsigned int pc) {
char line[80];
 
if (!dbg_fp)
return;
321,23 → 195,16
fprintf(dbg_fp, "0x%08x: ", pc);
 
if (valid) {
zipi_to_string(m_mem[pc], la, lb);
if ((phase)||((m_mem[pc]&0x80000000)==0))
fprintf(dbg_fp, " %-24s", la);
else
fprintf(dbg_fp, " %-24s", lb);
zipi_to_string(m_mem[pc], line);
fprintf(dbg_fp, " %-20s\n", &line[1]);
} else {
fprintf(dbg_fp, " (0x%08x)", m_mem[pc]);
} if (illegal)
fprintf(dbg_fp, " (Illegal)");
fprintf(dbg_fp, "\n");
fprintf(dbg_fp, " (0x%08x)\n", m_mem[pc]);
}
}
 
void show_state(void) {
int ln= 0;
 
read_raw_state_cheating();
 
mvprintw(ln,0, "Peripherals-SS"); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
printw(" %s",
359,8 → 226,8
&&(m_core->v__DOT__sys_addr == 0))?"W":" ",
(m_core->v__DOT__trap_int)?"I":" ");
*/
showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0));
showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1));
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
 
if (!m_show_user_timers) {
369,27 → 236,27
showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
}
 
showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
showval(ln,60, "PIC2", m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state, (m_cursor==3));
 
ln++;
showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
showval(ln, 0, "TMRA", m_core->v__DOT__timer_a__DOT__r_value, (m_cursor==4));
showval(ln,20, "TMRB", m_core->v__DOT__timer_b__DOT__r_value, (m_cursor==5));
showval(ln,40, "TMRC", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
 
if (!m_show_user_timers) {
ln++;
showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
showval(ln, 0, "MTSK", m_core->v__DOT__mtc_data, (m_cursor==8));
showval(ln,20, "MOST", m_core->v__DOT__moc_data, (m_cursor==9));
showval(ln,40, "MPST", m_core->v__DOT__mpc_data, (m_cursor==10));
showval(ln,60, "MICT", m_core->v__DOT__mic_data, (m_cursor==11));
} else {
ln++;
showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
}
 
ln++;
427,28 → 294,18
 
showreg(ln, 0, "sR12", 12, (m_cursor==24));
showreg(ln,20, "sSP ", 13, (m_cursor==25));
 
unsigned int cc = m_state.m_sR[14];
if (true) {
mvprintw(ln,40, "%ssCC : 0x%08x",
(m_cursor==26)?">":" ", cc);
} else {
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(cc&0x01000)?"FE":"",
(cc&0x00800)?"DE":"",
(cc&0x00400)?"BE":"",
(cc&0x00200)?"TP":"",
(cc&0x00100)?"IL":"",
(cc&0x00080)?"BK":"",
((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
mvprintw(ln, 54, "%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(m_core->v__DOT__thecpu__DOT__trap)?"TP":" ",
(m_core->v__DOT__thecpu__DOT__break_en)?"BK":" ",
(m_core->v__DOT__thecpu__DOT__step)?"ST":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SL":" ",
(m_core->v__DOT__thecpu__DOT__gie)?"IE":" ",
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ",
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ",
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ",
(m_core->v__DOT__thecpu__DOT__iflags&1)?"Z":" ");
showval(ln,60, "sPC ", m_core->v__DOT__thecpu__DOT__ipc, (m_cursor==27));
mvprintw(ln,60,"%s",
(m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
489,27 → 346,17
 
showreg(ln, 0, "uR12", 28, (m_cursor==40));
showreg(ln,20, "uSP ", 29, (m_cursor==41));
cc = m_state.m_uR[14];
if (false) {
mvprintw(ln,40, "%cuCC : 0x%08x",
(m_cursor == 42)?'>':' ', cc);
} else {
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(cc & 0x1000)?"FE":"",
(cc & 0x0800)?"DE":"",
(cc & 0x0400)?"BE":"",
(cc & 0x0200)?"TP":"",
(cc & 0x0100)?"IL":"",
(cc & 0x0040)?"ST":"",
((m_state.m_gie)&&(cc & 0x010))?"SL":"");
mvprintw(ln, 54, "%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
mvprintw(ln,40, "%cuCC :%s %s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(m_core->v__DOT__thecpu__DOT__trap)?"TP":" ",
(m_core->v__DOT__thecpu__DOT__step)?"ST":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SL":" ",
(m_core->v__DOT__thecpu__DOT__gie)?"IE":" ",
(m_core->v__DOT__thecpu__DOT__flags&8)?"V":" ",
(m_core->v__DOT__thecpu__DOT__flags&4)?"N":" ",
(m_core->v__DOT__thecpu__DOT__flags&2)?"C":" ",
(m_core->v__DOT__thecpu__DOT__flags&1)?"Z":" ");
showval(ln,60, "uPC ", m_core->v__DOT__thecpu__DOT__upc, (m_cursor==43));
mvprintw(ln,60,"%s",
(m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
&&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
534,10 → 381,9
(m_core->v__DOT__wb_data)); ln++;
#else
 
mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
mvprintw(ln, 0, "PFCACH: v=%08x, %s, tag=%08x, pf_pc=%08x, lastpc=%08x",
m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
(m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
(m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
m_core->v__DOT__thecpu__DOT__pf__DOT__tagval,
m_core->v__DOT__thecpu__DOT__pf_pc,
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
603,9 → 449,21
(!m_core->v__DOT__thecpu__DOT__op_pipe),
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
);
printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__dcd_pipe);
// mvprintw(4,4,"r_dcdI = 0x%06x",
// (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
printw(" op_pipe = %d%d%d%d%d(%d|%d)",
(dcdvalid()),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
(m_core->v__DOT__thecpu__DOT__dcdM),
(!((m_core->v__DOT__thecpu__DOT__dcdOp
^m_core->v__DOT__thecpu__DOT__opn)&1)),
((int)(dcdB()&0x01f)
== m_core->v__DOT__thecpu__DOT__op_B),
(m_core->v__DOT__thecpu__DOT__dcdI
== m_core->v__DOT__thecpu__DOT__r_opI),
(m_core->v__DOT__thecpu__DOT__dcdI+1
== m_core->v__DOT__thecpu__DOT__r_opI));
mvprintw(4,4,"r_dcdI = 0x%06x, r_opI = 0x%06x",
(m_core->v__DOT__thecpu__DOT__dcdI),
(m_core->v__DOT__thecpu__DOT__r_opI));
#endif
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
#ifdef OPT_SINGLE_CYCLE
630,8 → 488,7
//m_core->v__DOT__thecpu__DOT__instruction_gie,
m_core->v__DOT__thecpu__DOT__gie,
0,
m_core->v__DOT__thecpu__DOT__instruction_pc,
true); ln++;
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
showins(ln, "Dc",
642,13 → 499,7
#else
0,
#endif
m_core->v__DOT__thecpu__DOT__dcd_pc-1,
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
#else
false
#endif
); ln++;
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
mvprintw(ln-1,10,"I");
662,13 → 513,7
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
op_pc(),
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__r_op_phase
#else
false
#endif
); ln++;
op_pc()); ln++;
#ifdef OPT_ILLEGAL_INSTRUCTION
if (m_core->v__DOT__thecpu__DOT__op_illegal)
mvprintw(ln-1,10,"I");
688,13 → 533,7
#else
0,
#endif
alu_pc(),
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__r_alu_phase
#else
false
#endif
); ln++;
alu_pc()); ln++;
if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
mvprintw(ln-1,10,"W");
else if (m_core->v__DOT__thecpu__DOT__alu_valid)
739,14 → 578,7
printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
else
printw("%8s","");
mvprintw(ln-1, 48, "%s%s%s ",
(m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
:((m_core->v__DOT__thecpu__DOT__doalu__DOT__genblk3__DOT__r_busy)?"a":" "),
(m_core->v__DOT__thecpu__DOT__div_valid)?"D"
:((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
(m_core->v__DOT__thecpu__DOT__div_valid)?"F"
:((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
printw("MEM: %s%s %s%s %s %-5s",
mvprintw(ln-1, 48, "MEM: %s%s %s%s %s %-5s",
(m_core->v__DOT__thecpu__DOT__opvalid_mem)?"M":" ",
(m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":" ",
(m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
795,7 → 627,8
unsigned int v = wb_read(CMD_DATA);
 
if (dbg_flag)
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a, v);
fprintf(dbg_fp, "CMD-READ(%d) = 0x%08x\n", a,
v);
dbg_flag = false;
return v;
}
821,7 → 654,6
int ln= 0;
bool gie;
 
read_raw_state();
if (m_cursor < 0)
m_cursor = 0;
else if (m_cursor >= 44)
839,38 → 671,38
else if (v & 0x001000)
printw("Sleeping ");
else if (v & 0x002000)
printw("User Mod ");
printw("Supervisor Mod ");
if (v & 0x008000)
printw("Break-Enabled ");
if (v & 0x000080)
printw("PIC Enabled ");
} ln++;
showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
showval(ln,40, "WBUS", m_state.m_p[2], false);
showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0));
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1));
showval(ln,40, "WBUS", cmd_read(32+ 2), false);
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3));
ln++;
showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4));
showval(ln,20, "TMRB", cmd_read(32+ 5), (m_cursor==5));
showval(ln,40, "TMRC", cmd_read(32+ 6), (m_cursor==6));
showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
 
ln++;
if (!m_show_user_timers) {
showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
showval(ln, 0, "UTSK", cmd_read(32+8), (m_cursor==8));
showval(ln,20, "UMST", cmd_read(32+9), (m_cursor==9));
showval(ln,40, "UPST", cmd_read(32+10), (m_cursor==10));
showval(ln,60, "UICT", cmd_read(32+11), (m_cursor==11));
} else {
showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
}
 
ln++;
ln++;
unsigned int cc = m_state.m_sR[14];
unsigned int cc = cmd_read(14);
if (dbg_fp) fprintf(dbg_fp, "CC = %08x, gie = %d\n", cc,
m_core->v__DOT__thecpu__DOT__gie);
gie = (cc & 0x020);
881,43 → 713,35
mvprintw(ln, 0, "Supervisor Registers");
ln++;
 
dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
dispreg(ln, 0, "sR0 ", cmd_read(0), (m_cursor==12));
dispreg(ln,20, "sR1 ", cmd_read(1), (m_cursor==13));
dispreg(ln,40, "sR2 ", cmd_read(2), (m_cursor==14));
dispreg(ln,60, "sR3 ", cmd_read(3), (m_cursor==15)); ln++;
 
dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
dispreg(ln, 0, "sR4 ", cmd_read(4), (m_cursor==16));
dispreg(ln,20, "sR5 ", cmd_read(5), (m_cursor==17));
dispreg(ln,40, "sR6 ", cmd_read(6), (m_cursor==18));
dispreg(ln,60, "sR7 ", cmd_read(7), (m_cursor==19)); ln++;
 
dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
dispreg(ln, 0, "sR8 ", cmd_read( 8), (m_cursor==20));
dispreg(ln,20, "sR9 ", cmd_read( 9), (m_cursor==21));
dispreg(ln,40, "sR10", cmd_read(10), (m_cursor==22));
dispreg(ln,60, "sR11", cmd_read(11), (m_cursor==23)); ln++;
 
dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24));
dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25));
 
if (true) {
mvprintw(ln,40, "%ssCC : 0x%08x",
(m_cursor==26)?">":" ", cc);
} else {
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(cc&0x01000)?"FE":"",
(cc&0x00800)?"DE":"",
(cc&0x00400)?"BE":"",
(cc&0x00200)?"TP":"",
(cc&0x00100)?"IL":"",
(cc&0x00080)?"BK":"",
((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
mvprintw(ln, 54, "%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s",
(m_cursor==26)?">":" ",
(cc & 0x200)?"TP":" ",
(cc & 0x080)?"BK":" ",
(cc & 0x040)?"ST":" ",
(cc & 0x020)?"IE":" ",
(cc & 0x010)?"SL":" ",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
ln++;
 
933,44 → 757,35
(m_core->v__DOT__thecpu__DOT__opR_wr)?"W":" ",
(m_core->v__DOT__thecpu__DOT__opF_wr)?"F":" ");
ln++;
dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
dispreg(ln, 0, "uR0 ", cmd_read(16), (m_cursor==28));
dispreg(ln,20, "uR1 ", cmd_read(17), (m_cursor==29));
dispreg(ln,40, "uR2 ", cmd_read(18), (m_cursor==30));
dispreg(ln,60, "uR3 ", cmd_read(19), (m_cursor==31)); ln++;
 
dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
dispreg(ln, 0, "uR4 ", cmd_read(20), (m_cursor==32));
dispreg(ln,20, "uR5 ", cmd_read(21), (m_cursor==33));
dispreg(ln,40, "uR6 ", cmd_read(22), (m_cursor==34));
dispreg(ln,60, "uR7 ", cmd_read(23), (m_cursor==35)); ln++;
 
dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
dispreg(ln, 0, "uR8 ", cmd_read(24), (m_cursor==36));
dispreg(ln,20, "uR9 ", cmd_read(25), (m_cursor==37));
dispreg(ln,40, "uR10", cmd_read(26), (m_cursor==38));
dispreg(ln,60, "uR11", cmd_read(27), (m_cursor==39)); ln++;
 
dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
cc = m_state.m_uR[14];
if (false) {
mvprintw(ln,40, "%cuCC : 0x%08x",
(m_cursor == 42)?'>':' ', cc);
} else {
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(cc & 0x1000)?"FE":"",
(cc & 0x0800)?"DE":"",
(cc & 0x0400)?"BE":"",
(cc & 0x0200)?"TP":"",
(cc & 0x0100)?"IL":"",
(cc & 0x0040)?"ST":"",
((m_state.m_gie)&&(cc & 0x010))?"SL":"");
mvprintw(ln, 54, "%s%s%s%s",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
}
dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
dispreg(ln, 0, "uR12", cmd_read(28), (m_cursor==40));
dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41));
cc = cmd_read(30);
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(cc&0x100)?"TP":" ",
(cc&0x040)?"ST":" ",
(cc&0x020)?"IE":" ",
(cc&0x010)?"SL":" ",
(cc&8)?"V":" ",
(cc&4)?"N":" ",
(cc&2)?"C":" ",
(cc&1)?"Z":" ");
dispreg(ln,60, "uPC ", cmd_read(31), (m_cursor==43));
 
attroff(A_BOLD);
ln+=2;
986,8 → 801,7
m_core->v__DOT__thecpu__DOT__pf_valid,
m_core->v__DOT__thecpu__DOT__gie,
0,
m_core->v__DOT__thecpu__DOT__instruction_pc,
true); ln++;
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++;
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
 
showins(ln, "Dc",
998,13 → 812,7
#else
0,
#endif
m_core->v__DOT__thecpu__DOT__dcd_pc-1,
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
#else
false
#endif
); ln++;
m_core->v__DOT__thecpu__DOT__dcd_pc-1); ln++;
 
showins(ln, "Op",
op_ce(),
1011,13 → 819,7
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
op_pc(),
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__r_alu_phase
#else
false
#endif
); ln++;
op_pc()); ln++;
 
showins(ln, "Al",
m_core->v__DOT__thecpu__DOT__alu_ce,
1028,13 → 830,7
#else
0,
#endif
alu_pc(),
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__r_alu_phase
#else
false
#endif
); ln++;
alu_pc()); ln++;
}
 
void tick(void) {
1132,15 → 928,13
m_core->v__DOT__thecpu__DOT__op_break);
} else if ((dbg_fp)&&
((m_core->v__DOT__thecpu__DOT__op_break)
||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n",
(m_core->v__DOT__thecpu__DOT__master_ce)?"CE":" ",
m_core->v__DOT__thecpu__DOT__break_en,
m_core->v__DOT__thecpu__DOT__dcd_break,
m_core->v__DOT__thecpu__DOT__op_break,
m_core->v__DOT__thecpu__DOT__r_alu_illegal);
m_core->v__DOT__thecpu__DOT__op_break);
}
 
if (dbg_fp) {
1183,8 → 977,8
m_core->v__DOT__thecpu__DOT__upc,
m_core->v__DOT__thecpu__DOT__pf_pc);
} if (dbg_fp) {
#ifdef OPT_TRADITIONAL_PFCACHE
fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
#ifdef NEW_PREFETCH_VERSION
fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s\n",
(m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
m_core->v__DOT__thecpu__DOT__pf_pc,
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_branch_pc,
1194,8 → 988,7
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
m_core->v__DOT__thecpu__DOT__instruction_pc,
(m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
(m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
(m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
(m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ");
#endif
dbgins("Dc - ",
dcd_ce(), dcdvalid(),
1205,35 → 998,35
#else
0,
#endif
m_core->v__DOT__thecpu__DOT__dcd_pc-1,
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
#else
false,
#endif
#ifdef OPT_ILLEGAL_INSTRUCTION
m_core->v__DOT__thecpu__DOT__dcd_illegal
#else
false
#endif
);
m_core->v__DOT__thecpu__DOT__dcd_pc-1);
dbgins("Op - ",
op_ce(),
m_core->v__DOT__thecpu__DOT__opvalid,
m_core->v__DOT__thecpu__DOT__op_gie,
m_core->v__DOT__thecpu__DOT__op_stall,
op_pc(),
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__r_op_phase,
#else
false,
op_pc());
/*
#ifdef OPT_SINGLE_CYCLE
fprintf(dbg_fp, "\t\t A = %08x, B = %08x, I = %08x, B+I = %08x, %c%c %s%s%s[%2x] = %08x %s\n",
m_core->v__DOT__thecpu__DOT__r_opA,
m_core->v__DOT__thecpu__DOT__r_opB,
m_core->v__DOT__thecpu__DOT__w_opBnI,
m_core->v__DOT__thecpu__DOT__r_dcdI,
(m_core->v__DOT__thecpu__DOT__opvalid_alu)?'A':'-',
(m_core->v__DOT__thecpu__DOT__opvalid_mem)?'M':'-',
(m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"W":" ",
(m_core->v__DOT__thecpu__DOT__alu_wr)?"A":"M",
(m_core->v__DOT__thecpu__DOT__alu_ce)?"k":"-",
(m_core->v__DOT__thecpu__DOT__wr_reg_id),
(m_core->v__DOT__thecpu__DOT__wr_reg_vl),
(m_core->v__DOT__thecpu__DOT__mem_rdbusy)?"Mem-RdBusy":
((m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)?"Mem-Busy":""));
fprintf(dbg_fp, "\t\topA = %08x, opB = %08x, alu_result = %08x\n",
m_core->v__DOT__thecpu__DOT__opA,
m_core->v__DOT__thecpu__DOT__opB,
m_core->v__DOT__thecpu__DOT__alu_result);
#endif
#ifdef OPT_ILLEGAL_INSTRUCTION
m_core->v__DOT__thecpu__DOT__op_illegal
#else
false
#endif
);
*/
dbgins("Al - ",
m_core->v__DOT__thecpu__DOT__alu_ce,
m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1243,18 → 1036,7
#else
0,
#endif
alu_pc(),
#ifdef OPT_VLIW
m_core->v__DOT__thecpu__DOT__r_alu_phase,
#else
false,
#endif
#ifdef OPT_ILLEGAL_INSTRUCTION
m_core->v__DOT__thecpu__DOT__r_alu_illegal
#else
false
#endif
);
alu_pc());
 
}
 
1381,9 → 1163,9
if (m_core->v__DOT__thecpu__DOT__sleep)
return 0;
else if (m_core->v__DOT__thecpu__DOT__gie)
return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x2f0f7fff);
else
return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x2f0f7fff);
/*
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
&&(m_mem[alu_pc()] == 0x2f0f7fff)
1733,15 → 1515,6
tb->m_core->v__DOT__cmd_reset = 1;
tb->m_core->v__DOT__cmd_halt = 0;
 
/*
// For debugging purposes: do we wish to skip some number of
// instructions to fast forward to a time of interest??
for(int i=0; i<0x4d0; i++) {
tb->m_core->v__DOT__cmd_halt = 0;
tb->tick();
}
*/
 
int chv = 'q';
 
bool done = false, halted = true, manual = true,
1797,7 → 1570,7
case 's':
if (!halted)
erase();
tb->step();
tb->wb_write(CMD_REG, CMD_STEP);
manual = false;
halted = true;
high_speed = false;
1831,7 → 1604,7
halted = false;
high_speed = false;
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
tb->m_core->v__DOT__cmd_halt = 0;
// tb->m_core->v__DOT__cmd_halt = 0;
// tb->m_core->v__DOT__cmd_step = 0;
tb->tick();
break;
/Makefile
38,7 → 38,7
 
CXX := g++
FLAGS := -Wall -Og -g
ZASM := ../../sw/zasm
ZASM := ../../sw/zasm/z2
RTLD := ../../rtl
INCS := -I$(RTLD)/obj_dir/ -I$(RTLD) -I/usr/share/verilator/include -I$(ZASM)
SOURCES := zippy_tb.cpp memsim.cpp twoc.cpp $(ZASM)/zopcodes.cpp $(ZASM)/zparser.cpp
77,4 → 77,4
 
.PHONY: clean
clean:
rm ./zippy_tb pdump div_tb
rm ./zippy_tb

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