OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/bench
    from Rev 4 to Rev 8
    Reverse comparison

Rev 4 → Rev 8

/cpp/zippy_tb.cpp
834,29 → 834,29
// Overflow set from subtraction
tb->m_mem[mptr++] = zp.op_ldi(0x0400,zp.ZIP_R11); // 6: LDI $4,R11
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); // 7: LDI $1,R0
tb->m_mem[mptr++] = 0x5000001f; // 8: ROL $31,R0
tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0); // 8: ROL $31,R0
tb->m_mem[mptr++] = zp.op_sub(1,zp.ZIP_R0); // Should set ovfl
tb->m_mem[mptr++] = zp.op_bv(1); // A: BV $1+PC
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
// Overflow set from LSR
tb->m_mem[mptr++] = zp.op_ldi(0x0500,zp.ZIP_R11); // C: LDI $5,R11
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); // D: LDI $1,R0
tb->m_mem[mptr++] = 0x5000001f; // E: ROL $31,R0
tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0); // F: LSR $1,R0
tb->m_mem[mptr++] = zp.op_bv(1); // A: BV $1+PC
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_lsr(1,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_bv(1);
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
// Overflow set from LSL
tb->m_mem[mptr++] = zp.op_ldi(0x0600,zp.ZIP_R11); // C: LDI $6,R11
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); // D: LDI $1,R0
tb->m_mem[mptr++] = 0x5000001e; // E: ROL $30,R0
tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0); // F: LSR $1,R0
tb->m_mem[mptr++] = zp.op_bv(1); // A: BV $1+PC
tb->m_mem[mptr++] = zp.op_ldi(0x0600,zp.ZIP_R11);
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_rol(30,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_bv(1);
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
// Overflow set from LSL, negative to positive
tb->m_mem[mptr++] = zp.op_ldi(0x0700,zp.ZIP_R11); // C: LDI $7,R11
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0); // D: LDI $1,R0
tb->m_mem[mptr++] = 0x5000001f; // E: ROL $30,R0
tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0); // F: LSR $1,R0
tb->m_mem[mptr++] = zp.op_ldi(0x0700,zp.ZIP_R11);
tb->m_mem[mptr++] = zp.op_ldi(1,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_rol(31,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_lsl(1,zp.ZIP_R0);
tb->m_mem[mptr++] = zp.op_bv(1); // A: BV $1+PC
tb->m_mem[mptr++] = zp.op_mov(0,zp.ZIP_R11, zp.ZIP_CC); // FAIL! if here
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.