Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    from Rev 202 to Rev 209
    Reverse comparison

Rev 202 → Rev 209

3674,8 → 3674,7
instruction set has demonstrated an amazing versatility. I will contend
therefore and for anyone who will listen, that this instruction set
offers a full and complete capability for whatever a user might wish
to do with two exceptions: bytewise character access and accelerated
floating-point support.
to do with the only exception being accelerated floating-point support.
\item The burst load/store approach using the wishbone pipelining mode is
novel, and can be used to greatly increase the speed of the processor.
\item The novel approach to interrupts greatly facilitates the development of
3689,17 → 3688,6
At the same time, if most modern systems handle interrupt vectoring in
software anyway, why maintain complicated hardware support for it?
\item My goal of a high rate of instructions per clock may not be the proper
measure of this CPU. For example, if instructions are being read from a
SPI flash device, such as is common among FPGA implementations, these
same instructions may suffer stalls of between 64 and 128 cycles per
instruction just to read the instruction from the flash. Executing the
instruction in a single clock cycle is no longer the appropriate
measure. At the same time, it should be possible to use the DMA
peripheral to copy instructions from the FLASH to a temporary memory
location, after which they may be executed at a single instruction
cycle per access again.
\item Both GCC and binutils back ends exist for the ZipCPU.
\item As of this version of the CPU, a newlib veresion of the C--library
now exists.

powered by: WebSVN 2.1.0

© copyright 1999-2022, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.