URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

# Subversion Repositorieszipcpu

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• This comparison shows the changes necessary to convert path
/zipcpu/trunk/doc/src
from Rev 37 to Rev 36
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## Rev 37 → Rev 36

/spec.tex
411,6 → 411,25
 supervisor, in supervisor mode, to determine whether it got to supervisor mode from a trap or from an external interrupt or both.   These status register bits are summarized in Tbl.~\ref{tbl:ccbits}. \begin{table} \begin{center} \begin{tabular}{l|l} Bit & Meaning \\\hline 9 & Soft trap, set on a trap from user mode, cleared when returning to user mode\\\hline 8 & (Reserved for) Floating point enable \\\hline 7 & Halt on break, to support an external debugger \\\hline 6 & Step, single step the CPU in user mode\\\hline 5 & GIE, or Global Interrupt Enable \\\hline 4 & Sleep \\\hline 3 & V, or overflow bit.\\\hline 2 & N, or negative bit.\\\hline 1 & C, or carry bit.\\\hline 0 & Z, or zero bit. \\\hline \end{tabular} \caption{Condition Code / Status Register Bits}\label{tbl:ccbits} \end{center}\end{table}   \section{Conditional Instructions} Most, although not quite all, instructions may be conditionally executed. From the four condition code flags, eight conditions are defined. These are shown
813,7 → 832,7
  instruction. \\\hline NOT Rx & XOR \$-1,Rx & \\\hline POP Rx   & \parbox[t]{1.5in}{LOD \$1(SP),Rx \\ ADD \$1,SP}  & \parbox[t]{1.5in}{LOD \$-1(SP),Rx \\ ADD \\$1,SP}  & Note  that for interrupt purposes, one can never depend upon the value at  (SP). Hence you read from it, then increment it, lest having
892,7 → 911,7
  got there via a TRAP. The trap could be made conditional by making  the LDI and the AND conditional. In that case, the assembler would  quietly turn the LDI instruction into an LDILO and LDIHI pair,  but the effect would be the same. \\\hline  but the effectt would be the same. \\\hline \end{tabular} \caption{Derived Instructions, continued}\label{tbl:derived-3} \end{center}\end{table}