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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/doc/src
    from Rev 73 to Rev 92
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Rev 73 → Rev 92

/spec.tex
51,7 → 51,7
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq (at) opencores.org}
\revision{Rev.~0.7}
\revision{Rev.~0.8}
\definecolor{webred}{rgb}{0.5,0,0}
\definecolor{webgreen}{rgb}{0,0.4,0}
\usepackage[dvips,ps2pdf,colorlinks=true,
84,6 → 84,7
copy.
\end{license}
\begin{revisionhistory}
0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
973,8 → 974,8
& \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
& Add with carry \\\hline
{\tt BRA.Cond +/-\$Addr}
& \hbox{\tt MOV.cond \$Addr+PC,PC}
& Branch or jump on condition. Works for 13--bit
& \hbox{\tt ADD.cond \$Addr+PC,PC}
& Branch or jump on condition. Works for 18--bit
signed address offsets.\\\hline
{\tt BRA.Cond +/-\$Addr}
& \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
983,10 → 984,10
this can be made to work anywhere in the 32-bit address space, but yet
cost an additional instruction still. \\\hline
{\tt BNC PC+\$Addr}
& \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
& \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ ADD.Z PC+\$Addr,PC}
& Example of a branch on an unsupported
condition, in this case a branch on not carry \\\hline
{\tt BUSY } & {\tt MOV \$-1(PC),PC} & Execute an infinite loop \\\hline
{\tt BUSY } & {\tt ADD \$-1,PC} & Execute an infinite loop \\\hline
{\tt CLRF.NZ Rx }
& {\tt XOR.NZ Rx,Rx}
& Clear Rx, and flags, if the Z-bit is not set \\\hline
1005,8 → 1006,8
{\tt IRET}
& {\tt OR \$GIE,CC}
& Also known as an RTU instruction (Return to Userspace) \\\hline
{\tt JMP R6+\$Addr}
& {\tt MOV \$Addr(R6),PC}
{\tt JMP R6+\$Offset}
& {\tt MOV \$Offset(R6),PC}
& \\\hline
{\tt LJMP \$Addr}
& \parbox[t]{1.5in}{\tt LOD (PC),PC \\ {\em Address }}
1014,8 → 1015,8
works in a Von Neumann architecture, this instruction combination makes
for a nice combination that can be adjusted by a linker at a later
time.\\\hline
{\tt JSR PC+\$Addr }
& \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ MOV \$addr+PC,PC}
{\tt JSR PC+\$Offset }
& \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ ADD \$Offset,PC}
& This is similar to the jump and link instructions from other
architectures, save only that it requires a specific link
instruction, also known as the {\tt MOV} instruction on the
1297,7 → 1298,7
for the four stalls. (Were the {\tt pipefetch} cache chosen, there would
be another stall internal to the {\tt pipefetch} cache.)
 
The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and
The Zip CPU handles the {\tt ADD \$X,PC} and
{\tt LDI \$X,PC} instructions specially, however. These instructions, when
not conditioned on the flags, can execute with only a single stall cycle,
such as is shown in Fig.~\ref{fig:branch}.\footnote{Note that when using the

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