URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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/zipcpu/trunk/rtl/core
- from Rev 201 to Rev 196
- ↔ Reverse comparison
Rev 201 → Rev 196
/dcache.v
File deleted
/div.v
1,77 → 1,18
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: div.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Provide an Integer divide capability to the Zip CPU. Provides |
// for both signed and unsigned divide. |
// Purpose: Provide an Integer divide capability to the Zip CPU. |
// |
// Steps: |
// i_rst The DIVide unit starts in idle. It can also be placed into an |
// idle by asserting the reset input. |
// |
// i_wr When i_rst is asserted, a divide begins. On the next clock: |
// |
// o_busy is set high so everyone else knows we are at work and they can |
// wait for us to complete. |
// |
// pre_sign is set to true if we need to do a signed divide. In this |
// case, we take a clock cycle to turn the divide into an unsigned |
// divide. |
// |
// o_quotient, a place to store our result, is initialized to all zeros. |
// |
// r_dividend is set to the numerator |
// |
// r_divisor is set to 2^31 * the denominator (shift left by 31, or add |
// 31 zeros to the right of the number. |
// |
// pre_sign When true (clock cycle after i_wr), a clock cycle is used |
// to take the absolute value of the various arguments (r_dividend |
// and r_divisor), and to calculate what sign the output result |
// should be. |
// |
// |
// At this point, the divide is has started. The divide works by walking |
// through every shift of the |
// |
// DIVIDEND over the |
// DIVISOR |
// |
// If the DIVISOR is bigger than the dividend, the divisor is shifted |
// right, and nothing is done to the output quotient. |
// |
// DIVIDEND |
// DIVISOR |
// |
// This repeats, until DIVISOR is less than or equal to the divident, as in |
// |
// DIVIDEND |
// DIVISOR |
// |
// At this point, if the DIVISOR is less than the dividend, the |
// divisor is subtracted from the dividend, and the DIVISOR is again |
// shifted to the right. Further, a '1' bit gets set in the output |
// quotient. |
// |
// Once we've done this for 32 clocks, we've accumulated our answer into |
// the output quotient, and we can proceed to the next step. If the |
// result will be signed, the next step negates the quotient, otherwise |
// it returns the result. |
// |
// On the clock when we are done, o_busy is set to false, and o_valid set |
// to true. (It is a violation of the ZipCPU internal protocol for both |
// busy and valid to ever be true on the same clock. It is also a |
// violation for busy to be false with valid true thereafter.) |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
83,18 → 24,12
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// |
// `include "cpudefs.v" |
// |
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator, |
/pfcache.v
13,7 → 13,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
25,11 → 25,6
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
36,7 → 31,6
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache, |
// i_early_branch, i_from_addr, |
i_stall_n, i_pc, o_i, o_pc, o_v, |
/pipemem.v
1,4 → 1,4
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pipemem.v |
// |
15,9 → 15,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
29,31 → 29,24
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// |
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0; |
localparam AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_pipe_stb, i_lock; |
// CPU interface |
input [2:0] i_op; |
input i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
71,7 → 64,6
output reg o_wb_stb_lcl, o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
80,27 → 72,25
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
reg [3:0] rdaddr, wraddr; |
wire [3:0] nxt_rdaddr; |
reg [(4+5-1):0] fifo_oreg [0:15]; |
reg [(5-1):0] fifo_oreg [0:15]; |
initial rdaddr = 0; |
initial wraddr = 0; |
|
always @(posedge i_clk) |
fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] }; |
|
fifo_oreg[wraddr] <= i_oreg; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
wraddr <= 0; |
else if (i_pipe_stb) |
wraddr <= wraddr + 1'b1; |
wraddr <= wraddr + 4'h1; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
rdaddr <= 0; |
else if ((i_wb_ack)&&(cyc)) |
rdaddr <= rdaddr + 1'b1; |
assign nxt_rdaddr = rdaddr + 1'b1; |
rdaddr <= rdaddr + 4'h1; |
assign nxt_rdaddr = rdaddr + 4'h1; |
|
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_addr[31:24]==8'hff); |
assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (~lcl_stb); |
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
145,36 → 135,19
// o_wb_we <= i_op |
end |
always @(posedge i_clk) |
if ((!cyc)||(!i_wb_stall)) |
if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall)) |
begin |
o_wb_addr <= i_addr[(AW+1):2]; |
if (!i_op[0]) // Always select everything on reads |
o_wb_sel <= 4'b1111; // Op is even |
else casez({ i_op[2:1], i_addr[1:0] }) |
4'b100?: o_wb_sel <= 4'b1100; // Op = 5 |
4'b101?: o_wb_sel <= 4'b0011; // Op = 5 |
4'b1100: o_wb_sel <= 4'b1000; // Op = 5 |
4'b1101: o_wb_sel <= 4'b0100; // Op = 7 |
4'b1110: o_wb_sel <= 4'b0010; // Op = 7 |
4'b1111: o_wb_sel <= 4'b0001; // Op = 7 |
default: o_wb_sel <= 4'b1111; // Op = 7 |
endcase |
|
casez({ i_op[2:1], i_addr[1:0] }) |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
default: o_wb_data <= i_data; |
endcase |
|
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
end else if ((~cyc)&&(i_pipe_stb)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
end |
|
|
always @(posedge i_clk) |
if ((i_pipe_stb)&&(~cyc)) |
o_wb_we <= i_op[0]; |
o_wb_we <= i_op; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
184,20 → 157,12
o_err <= (cyc)&&(i_wb_err); |
assign o_busy = cyc; |
|
wire [8:0] w_wreg; |
assign w_wreg = fifo_oreg[rdaddr]; |
always @(posedge i_clk) |
o_wreg <= w_wreg[8:4]; |
o_wreg <= fifo_oreg[rdaddr]; |
always @(posedge i_clk) |
casez(w_wreg[3:0]) |
4'b1100: o_result = { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result = { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result = { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result = { 24'h00, i_wb_data[ 7: 0] }; |
4'b100?: o_result = { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result = { 16'h00, i_wb_data[15: 0] }; |
default: o_result = i_wb_data[31:0]; |
endcase |
// if (i_wb_ack) isn't necessary, since o_valid won't be true |
// then either. |
o_result <= i_wb_data; |
|
assign o_pipe_stalled = (cyc) |
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl))); |
212,7 → 177,7
always @(posedge i_clk) |
begin |
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl)); |
end |
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); |
/cpuops.v
1,4 → 1,4
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpuops.v |
// |
12,9 → 12,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
26,16 → 26,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
`include "cpudefs.v" |
// |
50,6 → 45,12
output reg o_valid; |
output wire o_busy; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result, w_lsl_result; |
wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted; |
74,20 → 75,28
assign w_brev_result[k] = i_b[31-k]; |
end endgenerate |
|
// Popcount pre-logic |
wire [31:0] w_popc_result; |
assign w_popc_result[5:0]= |
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]}) |
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]}) |
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]}) |
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]}) |
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]}) |
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]}) |
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]}) |
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]}); |
assign w_popc_result[31:6] = 26'h00; |
|
// Prelogic for our flags registers |
wire z, n, v; |
reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl; |
reg c, pre_sign, set_ovfl; |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD |
||(i_op == 4'h6) // LSL |
||(i_op == 4'h5)); // LSR |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
keep_sgn_on_ovfl<= |
(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD |
|
wire [63:0] mpy_result; // Where we dump the multiply result |
reg mpyhi; // Return the high half of the multiply |
101,7 → 110,7
// this will cost a minimum of 132 6-LUTs. |
|
wire this_is_a_multiply_op; |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc)); |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8)); |
|
generate |
if (IMPLEMENT_MPY == 0) |
324,11 → 333,13
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
4'b1000: o_c <= w_brev_result; // BREV |
4'b1000: o_c <= mpy_result[31:0]; // MPY |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= mpy_result[31:0]; // MPY |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
default: o_c <= i_b; // MOV, LDI |
endcase |
end else // if (mpydone) |
348,9 → 359,8
assign z = (o_c == 32'h0000); |
assign n = (o_c[31]); |
assign v = (set_ovfl)&&(pre_sign != o_c[31]); |
wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]); |
|
assign o_f = { v, n^vx, c, z }; |
assign o_f = { v, n, c, z }; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
/zipcpu.v
1,4 → 1,4
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcpu.v |
// |
18,7 → 18,7
// |
// The Zip CPU is fully pipelined with the following pipeline stages: |
// |
// 1. Prefetch, returns the instruction from memory. |
// 1. Prefetch, returns the instruction from memory. |
// |
// 2. Instruction Decode |
// |
72,9 → 72,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
86,23 → 86,28
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
// Slice LUTs ZipSystem ZipCPU |
// Single Fetching 2521 1734 |
// Pipelined fetching 2796 2046 |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_CLRCACHE_BIT 14 // Set to clear the I-cache, automatically clears |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a CIS |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a VLIW |
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error |
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero |
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error |
109,7 → 114,7
`define CPU_TRAP_BIT 9 // User TRAP has taken place |
`define CPU_ILL_BIT 8 // Illegal instruction |
`define CPU_BREAK_BIT 7 |
`define CPU_STEP_BIT 6 // Will step one (or two CIS) instructions |
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions |
`define CPU_GIE_BIT 5 |
`define CPU_SLEEP_BIT 4 |
// Compile time defines |
125,7 → 130,7
// CPU interface to the wishbone bus |
o_wb_gbl_cyc, o_wb_gbl_stb, |
o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_err, |
// Accounting/CPU usage interface |
134,8 → 139,7
, o_debug |
`endif |
); |
parameter [31:0] RESET_ADDRESS=32'h0100000; |
parameter ADDRESS_WIDTH=30, |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
LGICACHE=8; |
`ifdef OPT_MULTIPLY |
parameter IMPLEMENT_MPY = `OPT_MULTIPLY; |
158,9 → 162,7
`else |
parameter EARLY_BRANCHING = 0; |
`endif |
parameter WITH_LOCAL_BUS = 1; |
localparam AW=ADDRESS_WIDTH; |
localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2]; |
input i_clk, i_rst, i_interrupt; |
// Debug interface -- inputs |
input i_halt, i_clear_pf_cache; |
177,7 → 179,6
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
// Wishbone interface -- inputs |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
202,22 → 203,22
// that logic. |
// |
(* ram_style = "distributed" *) |
`ifdef OPT_NO_USERMODE |
reg [31:0] regset [0:15]; |
`else |
reg [31:0] regset [0:31]; |
`endif |
|
// Condition codes |
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
reg [3:0] flags, iflags; |
wire [14:0] w_uflags, w_iflags; |
reg break_en, step, sleep, r_halted; |
wire break_pending, trap, gie, ubreak; |
wire w_clear_icache, ill_err_u; |
reg ill_err_i; |
reg ibus_err_flag; |
wire ubus_err_flag; |
reg trap, break_en, step, gie, sleep, r_halted; |
wire break_pending; |
wire w_clear_icache; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg ill_err_u, ill_err_i; |
`else |
wire ill_err_u, ill_err_i; |
`endif |
reg ubreak; |
reg ibus_err_flag, ubus_err_flag; |
wire idiv_err_flag, udiv_err_flag; |
wire ifpu_err_flag, ufpu_err_flag; |
wire ihalt_phase, uhalt_phase; |
230,7 → 231,7
// PIPELINE STAGE #1 :: Prefetch |
// Variable declarations |
// |
reg [(AW+1):0] pf_pc; |
reg [(AW-1):0] pf_pc; |
reg new_pc; |
wire clear_pipeline; |
assign clear_pipeline = new_pc; |
239,9 → 240,9
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err; |
wire [(AW-1):0] pf_addr; |
wire [31:0] pf_data; |
wire [31:0] pf_instruction; |
wire [(AW-1):0] pf_instruction_pc; |
wire pf_valid, pf_gie, pf_illegal; |
wire [31:0] instruction; |
wire [(AW-1):0] instruction_pc; |
wire pf_valid, instruction_gie, pf_illegal; |
|
// |
// |
249,33 → 250,29
// Variable declarations |
// |
// |
reg op_valid /* verilator public_flat */, |
op_valid_mem, op_valid_alu; |
reg op_valid_div, op_valid_fpu; |
reg opvalid, opvalid_mem, opvalid_alu; |
reg opvalid_div, opvalid_fpu; |
wire op_stall, dcd_ce, dcd_phase; |
wire [3:0] dcd_opn; |
wire [4:0] dcd_A, dcd_B, dcd_R; |
wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc; |
wire [3:0] dcd_F; |
wire dcd_wR, dcd_rA, dcd_rB, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, |
dcd_wF, dcd_gie, dcd_break, dcd_lock, |
wire [3:0] dcdOp; |
wire [4:0] dcdA, dcdB, dcdR; |
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc; |
wire [3:0] dcdF; |
wire dcdR_wr, dcdA_rd, dcdB_rd, |
dcdALU, dcdM, dcdDV, dcdFP, |
dcdF_wr, dcd_gie, dcd_break, dcd_lock, |
dcd_pipe, dcd_ljmp; |
reg r_dcd_valid; |
wire dcd_valid; |
wire [AW:0] dcd_pc /* verilator public_flat */; |
wire [31:0] dcd_I; |
wire dcd_zI; // true if dcd_I == 0 |
wire dcd_A_stall, dcd_B_stall, dcd_F_stall; |
reg r_dcdvalid; |
wire dcdvalid; |
wire [(AW-1):0] dcd_pc; |
wire [31:0] dcdI; |
wire dcd_zI; // true if dcdI == 0 |
wire dcdA_stall, dcdB_stall, dcdF_stall; |
|
wire dcd_illegal; |
wire dcd_early_branch; |
wire [(AW-1):0] dcd_branch_pc; |
|
wire dcd_sim; |
wire [22:0] dcd_sim_immv; |
|
|
// |
// |
// PIPELINE STAGE #3 :: Read Operands |
285,33 → 282,33
// |
// Now, let's read our operands |
reg [4:0] alu_reg; |
wire [3:0] op_opn; |
wire [4:0] op_R; |
reg [31:0] r_op_Av, r_op_Bv; |
wire [3:0] opn; |
wire [4:0] opR; |
reg [31:0] r_opA, r_opB; |
reg [(AW-1):0] op_pc; |
wire [31:0] w_op_Av, w_op_Bv; |
wire [31:0] op_A_nowait, op_B_nowait, op_Av, op_Bv; |
reg op_wR, op_wF; |
wire op_gie, op_Rcc; |
wire [14:0] op_Fl; |
reg [6:0] r_op_F; |
wire [7:0] op_F; |
wire [31:0] w_opA, w_opB; |
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opF_wr; |
wire op_gie, opR_cc; |
wire [14:0] opFl; |
reg [5:0] r_opF; |
wire [7:0] opF; |
wire op_ce, op_phase, op_pipe, op_change_data_ce; |
// Some pipeline control wires |
`ifdef OPT_PIPELINED |
reg op_A_alu, op_A_mem; |
reg op_B_alu, op_B_mem; |
reg opA_alu, opA_mem; |
reg opB_alu, opB_mem; |
`endif |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`else |
wire op_illegal; |
assign op_illegal = 1'b0; |
`endif |
wire op_break; |
wire op_lock; |
|
`ifdef VERILATOR |
reg op_sim /* verilator public_flat */; |
reg [22:0] op_sim_immv /* verilator public_flat */; |
`endif |
|
|
// |
// |
// PIPELINE STAGE #4 :: ALU / Memory |
322,18 → 319,20
reg r_alu_pc_valid, mem_pc_valid; |
wire alu_pc_valid; |
wire alu_phase; |
wire alu_ce /* verilator public_flat */, alu_stall; |
wire alu_ce, alu_stall; |
wire [31:0] alu_result; |
wire [3:0] alu_flags; |
wire alu_valid, alu_busy; |
wire set_cond; |
reg alu_wR, alu_wF; |
reg alu_wr, alF_wr; |
wire alu_gie, alu_illegal; |
|
|
|
wire mem_ce, mem_stalled; |
`ifdef OPT_PIPELINED_BUS_ACCESS |
wire mem_pipe_stalled; |
`endif |
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err, |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we; |
wire [4:0] mem_wreg; |
341,13 → 340,12
wire mem_busy, mem_rdbusy; |
wire [(AW-1):0] mem_addr; |
wire [31:0] mem_data, mem_result; |
wire [3:0] mem_sel; |
|
wire div_ce, div_error, div_busy, div_valid; |
wire [31:0] div_result; |
wire [3:0] div_flags; |
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_div) |
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
355,7 → 353,7
wire [31:0] fpu_result; |
wire [3:0] fpu_flags; |
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_fpu) |
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
&&(set_cond); |
|
371,8 → 369,7
wire [4:0] wr_reg_id; |
wire [31:0] wr_gpreg_vl, wr_spreg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
reg [(AW+1):0] ipc; |
wire [(AW+1):0] upc; |
reg [(AW-1):0] upc, ipc; |
|
|
|
379,7 → 376,7
// |
// MASTER: clock enable. |
// |
assign master_ce = ((~i_halt)||(alu_phase))&&(~o_break)&&(~sleep); |
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep); |
|
|
// |
392,13 → 389,13
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
assign dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline); |
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline); |
|
`ifdef OPT_PIPELINED |
assign dcd_stalled = (dcd_valid)&&(op_stall); |
assign dcd_stalled = (dcdvalid)&&(op_stall); |
`else |
// If not pipelined, there will be no op_valid_ anything, and the |
// op_stall will be false, dcd_X_stall will be false, thus we can simply |
// If not pipelined, there will be no opvalid_ anything, and the |
// op_stall will be false, dcdX_stall will be false, thus we can simply |
// do a ... |
assign dcd_stalled = 1'b0; |
`endif |
405,17 → 402,17
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
wire prelock_stall; |
wire op_lock_stall; |
`ifdef OPT_PIPELINED |
reg cc_invalid_for_dcd; |
always @(posedge i_clk) |
cc_invalid_for_dcd <= (wr_flags_ce) |
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG) |
||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG))) |
||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(opvalid)&&((opF_wr)||((opR_wr)&&(opR[3:0] == `CPU_CC_REG))) |
||((alF_wr)||((alu_wr)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(mem_busy)||(div_busy)||(fpu_busy); |
|
assign op_stall = (op_valid)&&( // Only stall if we're loaded w/validins |
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins |
// Stall if we're stopped, and not allowed to execute |
// an instruction |
// (~master_ce) // Already captured in alu_stall |
428,29 → 425,27
// This also includes whether or not the divide or |
// floating point units are busy. |
(alu_stall) |
||(((op_valid_div)||(op_valid_fpu)) |
&&(!adf_ce_unconditional)) |
// |
// Stall if we are going into memory with an operation |
// that cannot be pipelined, and the memory is |
// already busy |
||(mem_stalled) // &&(op_valid_mem) part of mem_stalled |
||(op_Rcc) |
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled |
||(opR_cc) |
) |
||(dcd_valid)&&( |
||(dcdvalid)&&( |
// Stall if we need to wait for an operand A |
// to be ready to read |
(dcd_A_stall) |
(dcdA_stall) |
// Likewise for B, also includes logic |
// regarding immediate offset (register must |
// be in register file if we need to add to |
// an immediate) |
||(dcd_B_stall) |
||(dcdB_stall) |
// Or if we need to wait on flags to work on the |
// CC register |
||(dcd_F_stall) |
||(dcdF_stall) |
); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline); |
|
|
// BUT ... op_ce is too complex for many of the data operations. So |
457,11 → 452,11
// let's make their circuit enable code simpler. In particular, if |
// op_ doesn't need to be preserved, we can change it all we want |
// ... right? The clear_pipeline code, for example, really only needs |
// to determine whether op_valid is true. |
// to determine whether opvalid is true. |
assign op_change_data_ce = (~op_stall); |
`else |
assign op_stall = (op_valid)&&(~master_ce); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline); |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline); |
assign op_change_data_ce = 1'b1; |
`endif |
|
470,7 → 465,7
// Calculate stall conditions |
// |
// 1. Basic stall is if the previous stage is valid and the next is |
// busy. |
// busy. |
// 2. Also stall if the prior stage is valid and the master clock enable |
// is de-selected |
// 3. Stall if someone on the other end is writing the CC register, |
479,16 → 474,16
// through the ALU. Break instructions are not allowed through |
// the ALU. |
`ifdef OPT_PIPELINED |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2 |
||(prelock_stall) |
||((op_valid)&&(op_break)) |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2 |
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) // || op_illegal |
||(wr_reg_ce)&&(wr_write_cc) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall) |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall) |
&&(~clear_pipeline); |
`else |
assign alu_stall = (op_valid_alu)&&((~master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)&&(~clear_pipeline); |
assign alu_stall = (opvalid_alu)&&((~master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline); |
`endif |
// |
|
497,7 → 492,7
// alu_pc_valid. |
// |
`ifdef OPT_PIPELINED |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled) |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`else |
// If we aren't pipelined, then no one will be changing what's in the |
508,13 → 503,12
// something gets in the pipeline and then (due to interrupt or some |
// such) needs to be voided? Thus we avoid simplification and keep |
// what worked here. |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled) |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((op_valid_mem)&&( |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
(mem_pipe_stalled) |
||(prelock_stall) |
||((~op_pipe)&&(mem_busy)) |
||(div_busy) |
||(fpu_busy) |
526,7 → 520,7
&&((wr_write_pc)||(wr_write_cc))))); |
`else |
`ifdef OPT_PIPELINED |
assign mem_stalled = (mem_busy)||((op_valid_mem)&&( |
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
// Or waiting for a write to the PC register |
534,14 → 528,14
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc))))); |
`else |
assign mem_stalled = (op_valid_mem)&&(~master_ce); |
assign mem_stalled = (opvalid_mem)&&(~master_ce); |
`endif |
`endif |
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(op_valid) |
&&(~op_valid_mem)&&(~mem_rdbusy) |
&&((~op_valid_alu)||(~alu_stall))&&(~op_break) |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid) |
&&(~opvalid_mem)&&(~mem_rdbusy) |
&&((~opvalid_alu)||(~alu_stall))&&(~op_break) |
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline); |
|
// |
552,94 → 546,110
`ifdef OPT_SINGLE_FETCH |
wire pf_ce; |
|
assign pf_ce = (~pf_valid)&&(~dcd_valid)&&(~op_valid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
prefetch #(ADDRESS_WIDTH) |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc[(AW+1):2], gie, |
pf_instruction, pf_instruction_pc, pf_gie, |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data); |
|
initial r_dcd_valid = 1'b0; |
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_dcd_valid <= 1'b0; |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcd_valid <= (pf_valid)||(pf_illegal); |
r_dcdvalid <= (pf_valid)||(pf_illegal); |
else if (op_ce) |
r_dcd_valid <= 1'b0; |
assign dcd_valid = r_dcd_valid; |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
|
`else // Pipe fetch |
|
wire pf_stalled; |
assign pf_stalled = (dcd_stalled)||(dcd_phase); |
`ifdef OPT_TRADITIONAL_PFCACHE |
wire [(AW-1):0] pf_request_address; |
assign pf_request_address = ((dcd_early_branch)&&(!clear_pipeline)) |
? dcd_branch_pc:pf_pc[(AW+1):2]; |
pfcache #(LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
w_clear_icache, |
// dcd_pc, |
(!pf_stalled), |
pf_request_address, |
pf_instruction, pf_instruction_pc, pf_valid, |
~dcd_stalled, |
((dcd_early_branch)&&(~clear_pipeline)) |
? dcd_branch_pc:pf_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
pf_illegal); |
`else |
pipefetch #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch), |
w_clear_icache, (!pf_stalled), |
(new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc, |
pf_instruction, pf_instruction_pc, pf_valid, |
w_clear_icache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
//`ifdef OPT_PRECLEAR_BUS |
//((dcd_clear_bus)&&(dcdvalid)) |
//||((op_clear_bus)&&(opvalid)) |
//|| |
//`endif |
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
`endif |
`ifdef OPT_NO_USERMODE |
assign pf_gie = 1'b0; |
`else |
assign pf_gie = gie; |
`endif |
assign instruction_gie = gie; |
|
initial r_dcd_valid = 1'b0; |
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if ((clear_pipeline)||(w_clear_icache)) |
r_dcd_valid <= 1'b0; |
if ((i_rst)||(clear_pipeline)||(w_clear_icache)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcd_valid <= ((dcd_phase)||(pf_valid)) |
&&(~dcd_ljmp)&&(~dcd_early_branch); |
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&(~dcd_early_branch); |
else if (op_ce) |
r_dcd_valid <= 1'b0; |
assign dcd_valid = r_dcd_valid; |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
`endif |
|
// If not pipelined, there will be no op_valid_ anything, and the |
`ifdef OPT_NEW_INSTRUCTION_SET |
|
// If not pipelined, there will be no opvalid_ anything, and the |
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (clear_pipeline), |
(~dcd_valid)||(~op_stall), dcd_stalled, pf_instruction, pf_gie, |
pf_instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcd_Rcc, dcd_Rpc, dcd_R }, |
{ dcd_Acc, dcd_Apc, dcd_A }, |
{ dcd_Bcc, dcd_Bpc, dcd_B }, |
dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock, |
dcd_wR,dcd_rA, dcd_rB, |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
(~dcdvalid)||(~op_stall), dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, dcd_ljmp, |
dcd_pipe, |
dcd_sim, dcd_sim_immv); |
dcd_pipe); |
`else |
idecode_deprecated |
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
assign dcd_ljmp = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
reg r_op_pipe; |
|
initial r_op_pipe = 1'b0; |
// To be a pipeable operation, there must be |
// To be a pipeable operation, there must be |
// two valid adjacent instructions |
// Both must be memory instructions |
// Both must be writes, or both must be reads |
649,9 → 659,7
// However ... we need to know this before this clock, hence this is |
// calculated in the instruction decoder. |
always @(posedge i_clk) |
if (clear_pipeline) |
r_op_pipe <= 1'b0; |
else if (op_ce) |
if (op_ce) |
r_op_pipe <= dcd_pipe; |
else if (mem_ce) // Clear us any time an op_ is clocked in |
r_op_pipe <= 1'b0; |
665,20 → 673,31
// PIPELINE STAGE #3 :: Read Operands (Registers) |
// |
// |
`ifdef OPT_NO_USERMODE |
assign w_op_Av = regset[dcd_A[3:0]]; |
assign w_op_Bv = regset[dcd_B[3:0]]; |
`else |
assign w_op_Av = regset[dcd_A]; |
assign w_op_Bv = regset[dcd_B]; |
`endif |
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
|
wire [8:0] w_cpu_info; |
assign w_cpu_info = { |
`ifdef OPT_ILLEGAL_INSTRUCTION |
1'b1, |
(IMPLEMENT_MPY >0)? 1'b1:1'b0, |
(IMPLEMENT_DIVIDE >0)? 1'b1:1'b0, |
(IMPLEMENT_FPU >0)? 1'b1:1'b0, |
`else |
1'b0, |
`endif |
`ifdef OPT_MULTIPLY |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_DIVIDE |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_IMPLEMENT_FPU |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_PIPELINED |
1'b1, |
`else |
699,7 → 718,7
`else |
1'b0, |
`endif |
`ifdef OPT_CIS |
`ifdef OPT_VLIW |
1'b1 |
`else |
1'b0 |
707,85 → 726,79
}; |
|
wire [31:0] w_pcA_v; |
assign w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 30) |
assign w_pcA_v[31:(AW+2)] = 0; |
if (AW < 32) |
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc; |
endgenerate |
|
`ifdef OPT_PIPELINED |
reg [4:0] op_Aid, op_Bid; |
reg op_rA, op_rB; |
reg [4:0] opA_id, opB_id; |
reg opA_rd, opB_rd; |
always @(posedge i_clk) |
if (op_ce) |
begin |
op_Aid <= dcd_A; |
op_Bid <= dcd_B; |
op_rA <= dcd_rA; |
op_rB <= dcd_rB; |
opA_id <= dcdA; |
opB_id <= dcdB; |
opA_rd <= dcdA_rd; |
opB_rd <= dcdB_rd; |
end |
`endif |
|
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_ce) |
if (op_change_data_ce) |
`endif |
begin |
`ifdef OPT_PIPELINED |
if ((wr_reg_ce)&&(wr_reg_id == dcd_A)) |
r_op_Av <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == dcdA)) |
r_opA <= wr_gpreg_vl; |
else |
`endif |
if (dcd_Apc) |
r_op_Av <= w_pcA_v; |
else if (dcd_Acc) |
r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags }; |
if (dcdA_pc) |
r_opA <= w_pcA_v; |
else if (dcdA_cc) |
r_opA <= { w_cpu_info, w_opA[22:16], 1'b0, (dcdA[4])?w_uflags:w_iflags }; |
else |
r_op_Av <= w_op_Av; |
r_opA <= w_opA; |
`ifdef OPT_PIPELINED |
end else |
begin // We were going to pick these up when they became valid, |
// but for some reason we're stuck here as they became |
// valid. Pick them up now anyway |
// if (((op_A_alu)&&(alu_wR))||((op_A_mem)&&(mem_valid))) |
// r_op_Av <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA)) |
r_op_Av <= wr_gpreg_vl; |
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid))) |
// r_opA <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd)) |
r_opA <= wr_gpreg_vl; |
`endif |
end |
|
wire [31:0] w_op_BnI, w_pcB_v; |
assign w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
wire [31:0] w_opBnI, w_pcB_v; |
generate |
if (AW < 30) |
assign w_pcB_v[31:(AW+2)] = 0; |
if (AW < 32) |
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc; |
endgenerate |
|
assign w_op_BnI = (!dcd_rB) ? 32'h00 |
assign w_opBnI = (~dcdB_rd) ? 32'h00 |
`ifdef OPT_PIPELINED |
: ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl |
: ((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl |
`endif |
: ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14], |
1'b0, (dcd_B[4])?w_uflags:w_iflags} |
: w_op_Bv); |
: ((dcdB_pc) ? w_pcB_v |
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:16], // w_opB[31:14], |
1'b0, (dcdB[4])?w_uflags:w_iflags} |
: w_opB)); |
|
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if ((op_ce)&&(dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else if (op_ce) |
r_op_Bv <= w_op_BnI + dcd_I; |
else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB)) |
r_op_Bv <= wr_gpreg_vl; |
if (op_change_data_ce) |
r_opB <= w_opBnI + dcdI; |
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd)) |
r_opB <= wr_gpreg_vl; |
`else |
if ((dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else |
r_op_Bv <= w_op_BnI + dcd_I; |
r_opB <= w_opBnI + dcdI; |
`endif |
|
// The logic here has become more complex than it should be, no thanks |
796,42 → 809,54
// conditions checking those bits. Therefore, Vivado complains that |
// these two bits are redundant. Hence the convoluted expression |
// below, arriving at what we finally want in the (now wire net) |
// op_F. |
// opF. |
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_ce) // Cannot do op_change_data_ce here since op_F depends |
if (op_ce) // Cannot do op_change_data_ce here since opF depends |
// upon being either correct for a valid op, or correct |
// for the last valid op |
`endif |
begin // Set the flag condition codes, bit order is [3:0]=VNCZ |
case(dcd_F[2:0]) |
3'h0: r_op_F <= 7'h00; // Always |
3'h1: r_op_F <= 7'h11; // Z |
3'h2: r_op_F <= 7'h44; // LT |
3'h3: r_op_F <= 7'h22; // C |
3'h4: r_op_F <= 7'h08; // V |
3'h5: r_op_F <= 7'h10; // NE |
3'h6: r_op_F <= 7'h40; // GE (!N) |
3'h7: r_op_F <= 7'h20; // NC |
case(dcdF[2:0]) |
3'h0: r_opF <= 6'h00; // Always |
`ifdef OPT_NEW_INSTRUCTION_SET |
// These were remapped as part of the new instruction |
// set in order to make certain that the low order |
// two bits contained the most commonly used |
// conditions: Always, LT, Z, and NZ. |
3'h1: r_opF <= 6'h24; // LT |
3'h2: r_opF <= 6'h11; // Z |
3'h3: r_opF <= 6'h10; // NE |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h20; // GE (!N) |
`else |
3'h1: r_opF <= 6'h11; // Z |
3'h2: r_opF <= 6'h10; // NE |
3'h3: r_opF <= 6'h20; // GE (!N) |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h24; // LT |
`endif |
3'h6: r_opF <= 6'h02; // C |
3'h7: r_opF <= 6'h08; // V |
endcase |
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } |
assign op_F = { r_op_F[3], r_op_F[6:0] }; |
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
|
wire w_op_valid; |
assign w_op_valid = (~clear_pipeline)&&(dcd_valid)&&(~dcd_ljmp)&&(!dcd_early_branch); |
initial op_valid = 1'b0; |
initial op_valid_alu = 1'b0; |
initial op_valid_mem = 1'b0; |
initial op_valid_div = 1'b0; |
initial op_valid_fpu = 1'b0; |
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
initial opvalid_div = 1'b0; |
initial opvalid_fpu = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
if ((i_rst)||(clear_pipeline)) |
begin |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
end else if (op_ce) |
begin |
// Do we have a valid instruction? |
842,19 → 867,25
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch); |
op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal) |
||(dcd_early_branch)); |
op_valid_mem <= (dcd_M)&&(~dcd_illegal)&&(w_op_valid); |
op_valid_div <= (dcd_DIV)&&(~dcd_illegal)&&(w_op_valid); |
op_valid_fpu <= (dcd_FP)&&(~dcd_illegal)&&(w_op_valid); |
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid); |
`ifdef OPT_ILLEGAL_INSTRUCTION |
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal)); |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid); |
`else |
opvalid_alu <= (dcdALU)&&(w_opvalid); |
opvalid_mem <= (dcdM)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
`endif |
end else if ((adf_ce_unconditional)||(mem_ce)) |
begin |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
end |
|
// Here's part of our debug interface. When we recognize a break |
865,17 → 896,16
// condition, replace the break instruction with what it is supposed |
// to be, step through it, and then replace it back. In this fashion, |
// a debugger can step through code. |
// assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001); |
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
`ifdef OPT_PIPELINED |
reg r_op_break; |
|
initial r_op_break = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) r_op_break <= 1'b0; |
else if (op_ce) |
r_op_break <= (dcd_break); |
else if (!op_valid) |
r_op_break <= 1'b0; |
if (i_rst) r_op_break <= 1'b0; |
else if (op_ce) r_op_break <= (dcd_break); //||dcd_illegal &&(dcdvalid) |
else if ((clear_pipeline)||(~opvalid)) |
r_op_break <= 1'b0; |
assign op_break = r_op_break; |
`else |
assign op_break = dcd_break; |
885,21 → 915,33
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_op_lock; |
reg r_op_lock, r_op_lock_stall; |
|
initial r_op_lock_stall = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_op_lock_stall <= 1'b0; |
else |
r_op_lock_stall <= (~opvalid)||(~op_lock) |
||(~dcdvalid)||(~pf_valid); |
|
assign op_lock_stall = r_op_lock_stall; |
|
initial r_op_lock = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
if ((i_rst)||(clear_pipeline)) |
r_op_lock <= 1'b0; |
else if (op_ce) |
r_op_lock <= (dcd_valid)&&(dcd_lock)&&(~clear_pipeline); |
r_op_lock <= (dcd_lock)&&(~clear_pipeline); |
assign op_lock = r_op_lock; |
|
end else begin |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
end endgenerate |
|
`else |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
`endif |
|
906,13 → 948,13
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial op_illegal = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
if ((i_rst)||(clear_pipeline)) |
op_illegal <= 1'b0; |
else if(op_ce) |
`ifdef OPT_PIPELINED |
op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
op_illegal <= (dcdvalid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
`else |
op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock)); |
op_illegal <= (dcdvalid)&&((dcd_illegal)||(dcd_lock)); |
`endif |
else if(alu_ce) |
op_illegal <= 1'b0; |
925,87 → 967,61
always @(posedge i_clk) |
if (op_ce) |
begin |
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR)) |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
`else |
always @(posedge i_clk) |
begin |
op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR)) |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
end |
`endif |
|
`ifdef VERILATOR |
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
op_sim <= dcd_sim; |
op_sim_immv <= dcd_sim_immv; |
end |
`else |
always @(*) |
begin |
op_sim = dcd_sim; |
op_sim_immv = dcd_sim_immv; |
end |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [3:0] r_op_opn; |
reg [4:0] r_op_R; |
reg r_op_Rcc; |
reg [3:0] r_opn; |
reg [4:0] r_opR; |
reg r_opR_cc; |
reg r_op_gie; |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
// Which ALU operation? Early branches are |
// unimplemented moves |
r_op_opn <= (dcd_early_branch) ? 4'hf : dcd_opn; |
// opM <= dcd_M; // Is this a memory operation? |
r_opn <= dcdOp; // Which ALU operation? |
// opM <= dcdM; // Is this a memory operation? |
// What register will these results be written into? |
r_op_R <= dcd_R; |
r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie); |
r_opR <= dcdR; |
r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie); |
// User level (1), vs supervisor (0)/interrupts disabled |
r_op_gie <= dcd_gie; |
|
|
// |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
end |
assign op_opn = r_op_opn; |
assign op_R = r_op_R; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign opn = r_opn; |
assign opR = r_opR; |
assign op_gie = r_op_gie; |
`endif |
assign op_Rcc = r_op_Rcc; |
assign opR_cc = r_opR_cc; |
`else |
assign op_opn = dcd_opn; |
assign op_R = dcd_R; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign opn = dcdOp; |
assign opR = dcdR; |
assign op_gie = dcd_gie; |
`endif |
// With no pipelining, there is no early branching. We keep it |
always @(posedge i_clk) |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
`endif |
assign op_Fl = (op_gie)?(w_uflags):(w_iflags); |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
|
`ifdef OPT_CIS |
`ifdef OPT_VLIW |
reg r_op_phase; |
initial r_op_phase = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
if ((i_rst)||(clear_pipeline)) |
r_op_phase <= 1'b0; |
else if (op_change_data_ce) |
r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc)); |
r_op_phase <= dcd_phase; |
assign op_phase = r_op_phase; |
`else |
assign op_phase = 1'b0; |
1024,10 → 1040,10
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
`ifdef OPT_PIPELINED |
assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA)) |
? wr_gpreg_vl : r_op_Av; |
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd)) |
? wr_gpreg_vl : r_opA; |
`else |
assign op_Av = r_op_Av; |
assign opA = r_opA; |
`endif |
|
`ifdef OPT_PIPELINED |
1037,21 → 1053,21
// The operation might set flags, and we wish to read the |
// CC register |
// OR ... (No other conditions) |
assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere |
&&((op_valid)||(mem_rdbusy) |
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere |
&&((opvalid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)) |
&&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc)) |
||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd)); |
&&(((opF_wr)||(cc_invalid_for_dcd))&&(dcdA_cc)) |
||((dcdA_rd)&&(dcdA_cc)&&(cc_invalid_for_dcd)); |
`else |
// There are no pipeline hazards, if we aren't pipelined |
assign dcd_A_stall = 1'b0; |
assign dcdA_stall = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED |
assign op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB)) |
? wr_gpreg_vl: r_op_Bv; |
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd)) |
? wr_gpreg_vl: r_opB; |
`else |
assign op_Bv = r_op_Bv; |
assign opB = r_opB; |
`endif |
|
`ifdef OPT_PIPELINED |
1062,12 → 1078,12
// CC register |
// OR the operation might set register B, and we still need |
// a clock to add the offset to it |
assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere |
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere |
// If the op stage isn't valid, yet something |
// is running, then it must have been valid. |
// We'll use the last values from that stage |
// (op_wR, op_wF, op_R) in our logic below. |
&&((op_valid)||(mem_rdbusy) |
// (opR_wr, opF_wr, opR) in our logic below. |
&&((opvalid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)||(alu_busy)) |
&&( |
// Okay, what happens if the result register |
1074,13 → 1090,13
// from instruction 1 becomes the input for |
// instruction two, *and* there's an immediate |
// offset in instruction two? In that case, we |
// need an extra clock between the two |
// instructions to calculate the base plus |
// need an extra clock between the two |
// instructions to calculate the base plus |
// offset. |
// |
// What if instruction 1 (or before) is in a |
// memory pipeline? We may no longer know what |
// the register was! We will then need to |
// the register was! We will then need to |
// blindly wait. We'll temper this only waiting |
// if we're not piping this new instruction. |
// If we were piping, the pipe logic in the |
1088,28 → 1104,28
// is clear, so we're okay then. |
// |
((~dcd_zI)&&( |
((op_R == dcd_B)&&(op_wR)) |
((opR == dcdB)&&(opR_wr)) |
||((mem_rdbusy)&&(~dcd_pipe)) |
)) |
// Stall following any instruction that will |
// set the flags, if we're going to need the |
// flags (CC) register for op_B. |
||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc)) |
// flags (CC) register for opB. |
||(((opF_wr)||(cc_invalid_for_dcd))&&(dcdB_cc)) |
// Stall on any ongoing memory operation that |
// will write to op_B -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcd_B)&&(~dcd_zI)) |
// will write to opB -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI)) |
) |
||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd)); |
assign dcd_F_stall = ((~dcd_F[3]) |
||((dcd_rA)&&(dcd_Acc)) |
||((dcd_rB)&&(dcd_Bcc))) |
&&(op_valid)&&(op_Rcc); |
// &&(dcd_valid) is checked for elsewhere |
||((dcdB_rd)&&(dcdB_cc)&&(cc_invalid_for_dcd)); |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
`else |
// No stalls without pipelining, 'cause how can you have a pipeline |
// hazard without the pipeline? |
assign dcd_B_stall = 1'b0; |
assign dcd_F_stall = 1'b0; |
assign dcdB_stall = 1'b0; |
assign dcdF_stall = 1'b0; |
`endif |
// |
// |
1116,15 → 1132,15
// PIPELINE STAGE #4 :: Apply Instruction |
// |
// |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline), |
alu_ce, op_opn, op_Av, op_Bv, |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (i_rst)||(clear_pipeline), |
alu_ce, opn, opA, opB, |
alu_result, alu_flags, alu_valid, alu_busy); |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0], |
op_Av, op_Bv, div_busy, div_valid, div_error, div_result, |
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0], |
opA, opB, div_busy, div_valid, div_error, div_result, |
div_flags); |
end else begin |
assign div_error = 1'b0; // Can't be high unless div_valid |
1139,7 → 1155,7
begin |
// |
// sfpu thefpu(i_clk, i_rst, fpu_ce, |
// op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// fpu_flags); |
// |
assign fpu_error = 1'b0; // Must only be true if fpu_valid |
1156,27 → 1172,27
end endgenerate |
|
|
assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]); |
initial alu_wF = 1'b0; |
initial alu_wR = 1'b0; |
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]); |
initial alF_wr = 1'b0; |
initial alu_wr = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
alu_wR <= 1'b0; |
alu_wF <= 1'b0; |
alu_wr <= 1'b0; |
alF_wr <= 1'b0; |
end else if (alu_ce) |
begin |
// alu_reg <= op_R; |
alu_wR <= (op_wR)&&(set_cond); |
alu_wF <= (op_wF)&&(set_cond); |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond); |
alF_wr <= (opF_wr)&&(set_cond); |
end else if (~alu_busy) begin |
// These are strobe signals, so clear them if not |
// set for any particular clock |
alu_wR <= (i_halt)&&(i_dbg_we); |
alu_wF <= 1'b0; |
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
end |
|
`ifdef OPT_CIS |
`ifdef OPT_VLIW |
reg r_alu_phase; |
initial r_alu_phase = 1'b0; |
always @(posedge i_clk) |
1192,7 → 1208,7
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if (adf_ce_unconditional) |
alu_reg <= op_R; |
alu_reg <= opR; |
else if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
`else |
1200,7 → 1216,7
if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
else |
alu_reg <= op_R; |
alu_reg <= opR; |
`endif |
|
// |
1213,9 → 1229,6
reg [31:0] dbg_val; |
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
`ifdef OPT_NO_USERMODE |
assign alu_gie = 1'b0; |
`else |
`ifdef OPT_PIPELINED |
reg r_alu_gie; |
|
1223,27 → 1236,24
if ((adf_ce_unconditional)||(mem_ce)) |
r_alu_gie <= op_gie; |
assign alu_gie = r_alu_gie; |
`else |
assign alu_gie = op_gie; |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [(AW-1):0] r_alu_pc; |
always @(posedge i_clk) |
if ((adf_ce_unconditional) |
||((master_ce)&&(op_valid_mem)&&(~clear_pipeline) |
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline) |
&&(~mem_stalled))) |
r_alu_pc <= op_pc; |
assign alu_pc = r_alu_pc; |
`else |
assign alu_gie = op_gie; |
assign alu_pc = op_pc; |
`endif |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg r_alu_illegal; |
initial r_alu_illegal = 0; |
always @(posedge i_clk) |
if (clear_pipeline) |
if ((i_rst)||(clear_pipeline)) |
r_alu_illegal <= 1'b0; |
else if (alu_ce) |
r_alu_illegal <= op_illegal; |
1250,13 → 1260,16
else |
r_alu_illegal <= 1'b0; |
assign alu_illegal = (r_alu_illegal); |
`else |
assign alu_illegal = 1'b0; |
`endif |
|
initial r_alu_pc_valid = 1'b0; |
initial mem_pc_valid = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
if (i_rst) |
r_alu_pc_valid <= 1'b0; |
else if ((adf_ce_unconditional)&&(!op_phase)) //Includes&&(~alu_clear_pipeline) |
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline) |
r_alu_pc_valid <= 1'b1; |
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline)) |
r_alu_pc_valid <= 1'b0; |
1272,43 → 1285,17
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_prelock_stall; |
|
initial r_prelock_stall = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_stall <= 1'b0; |
else if ((op_valid)&&(op_lock)&&(op_ce)) |
r_prelock_stall <= 1'b1; |
else if ((op_valid)&&(dcd_valid)&&(pf_valid)) |
r_prelock_stall <= 1'b0; |
|
assign prelock_stall = r_prelock_stall; |
|
reg r_prelock_primed; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_primed <= 1'b0; |
else if (r_prelock_stall) |
r_prelock_primed <= 1'b1; |
else if ((adf_ce_unconditional)||(mem_ce)) |
r_prelock_primed <= 1'b0; |
|
reg [1:0] r_bus_lock; |
initial r_bus_lock = 2'b00; |
always @(posedge i_clk) |
if (clear_pipeline) |
if (i_rst) |
r_bus_lock <= 2'b00; |
else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce))) |
begin |
if (r_prelock_primed) |
r_bus_lock <= 2'b10; |
else if (r_bus_lock != 2'h0) |
r_bus_lock <= r_bus_lock + 2'b11; |
end |
else if ((op_ce)&&(op_lock)) |
r_bus_lock <= 2'b11; |
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce))) |
r_bus_lock <= r_bus_lock + 2'b11; |
assign bus_lock = |r_bus_lock; |
end else begin |
assign prelock_stall = 1'b0; |
assign bus_lock = 1'b0; |
end endgenerate |
`else |
1317,49 → 1304,38
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
(opn[0]), opB, opA, opR, |
mem_busy, mem_pipe_stalled, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, mem_err, i_wb_data); |
|
|
`else // PIPELINED_BUS_ACCESS |
memops #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
mem_busy, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, mem_err, i_wb_data); |
assign mem_pipe_stalled = 1'b0; |
`endif // PIPELINED_BUS_ACCESS |
assign mem_rdbusy = ((mem_busy)&&(~mem_we)); |
|
// Either the prefetch or the instruction gets the memory bus, but |
// Either the prefetch or the instruction gets the memory bus, but |
// never both. |
wbdblpriarb #(32,AW) pformem(i_clk, i_rst, |
// Memory access to the arbiter, priority position |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, |
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err, |
// Prefetch access to the arbiter |
// |
// At a first glance, we might want something like: |
// |
// pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf, |
// |
// However, we know that the prefetch will not generate any |
// writes. Therefore, the write specific lines (mem_data and |
// mem_sel) can be shared with the memory in order to ease |
// timing and LUT usage. |
pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel, |
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, |
// Common wires, in and out, of the arbiter |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err); |
|
|
1386,25 → 1362,25
// When shall we write back? On one of two conditions |
// Note that the flags needed to be checked before issuing the |
// bus instruction, so they don't need to be checked here. |
// Further, alu_wR includes (set_cond), so we don't need to |
// Further, alu_wr includes (set_cond), so we don't need to |
// check for that here either. |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wR)&&(alu_valid)) |
&&(((alu_wr)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
`else |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline) |
&&(((alu_wr)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
`endif |
// Which register shall be written? |
// COULD SIMPLIFY THIS: by adding three bits to these registers, |
// One or PC, one for CC, and one for GIE match |
// Note that the alu_reg is the register to write on a divide or |
// FPU operation. |
`ifdef OPT_NO_USERMODE |
assign wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid) |
? alu_reg[3:0]:mem_wreg[3:0]; |
assign wr_reg_id[4] = 1'b0; |
`else |
assign wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg; |
`endif |
|
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg; |
// Are we writing to the CC register? |
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG); |
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}); |
1421,17 → 1397,13
:((dbgv) ? dbg_val : alu_result)); |
always @(posedge i_clk) |
if (wr_reg_ce) |
`ifdef OPT_NO_USERMODE |
regset[wr_reg_id[3:0]] <= wr_gpreg_vl; |
`else |
regset[wr_reg_id] <= wr_gpreg_vl; |
`endif |
regset[wr_reg_id] <= wr_gpreg_vl; |
|
// |
// Write back to the condition codes/flags register ... |
// When shall we write to our flags register? alu_wF already |
// When shall we write to our flags register? alF_wr already |
// includes the set condition ... |
assign wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag, |
udiv_err_flag, ubus_err_flag, trap, ill_err_u, |
ubreak, step, 1'b1, sleep, |
1465,7 → 1437,7
// |
// The goal, upon encountering a break is that the CPU should stop and |
// not execute the break instruction, choosing instead to enter into |
// either interrupt mode or halt first. |
// either interrupt mode or halt first. |
// if ((break_en) AND (break_instruction)) // user mode or not |
// HALT CPU |
// else if (break_instruction) // only in user mode |
1486,7 → 1458,7
|
initial r_break_pending = 1'b0; |
always @(posedge i_clk) |
if ((clear_pipeline)||(~op_valid)) |
if ((i_rst)||(clear_pipeline)||(~opvalid)) |
r_break_pending <= 1'b0; |
else if (op_break) |
r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce); |
1509,31 → 1481,9
// sleep until the next interrupt. Setting the sleep register within |
// interrupt mode causes the processor to halt until a reset. This is |
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
initial sleep = 1'b0; |
`ifdef OPT_NO_USERMODE |
reg r_sleep_is_halt; |
initial r_sleep_is_halt = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_sleep_is_halt <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&(~wr_spreg_vl[`CPU_GIE_BIT])) |
r_sleep_is_halt <= 1'b1; |
|
// Trying to switch to user mode, either via a WAIT or an RTU |
// instruction will cause the CPU to sleep until an interrupt, in |
// the NO-USERMODE build. |
always @(posedge i_clk) |
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt))) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_GIE_BIT])) |
sleep <= 1'b1; |
`else |
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
1553,7 → 1503,6
// to sleep mode *and* supervisor mode at the same |
// time, lest you halt the CPU. |
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT]; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
1562,10 → 1511,6
step <= wr_spreg_vl[`CPU_STEP_BIT]; |
|
// The GIE register. Only interrupts can disable the interrupt register |
`ifdef OPT_NO_USERMODE |
assign w_switch_to_interrupt = 1'b0; |
assign w_release_from_interrupt = 1'b0; |
`else |
assign w_switch_to_interrupt = (gie)&&( |
// On interrupt (obviously) |
((i_interrupt)&&(~alu_phase)&&(~bus_lock)) |
1574,8 → 1519,10
// If we encounter a break instruction, if the break |
// enable isn't set. |
||((master_ce)&&(break_pending)&&(~break_en)) |
`ifdef OPT_ILLEGAL_INSTRUCTION |
// On an illegal instruction |
||((alu_illegal)&&(!clear_pipeline)) |
`endif |
// On division by zero. If the divide isn't |
// implemented, div_valid and div_error will be short |
// circuited and that logic will be bypassed |
1584,7 → 1531,7
// fpu_error must *never* be set unless fpu_valid is |
// also set as well, else this will fail. |
||(fpu_error) |
// |
// |
||(bus_err) |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
1595,56 → 1542,34
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_scc)) |
); |
`endif |
|
`ifdef OPT_NO_USERMODE |
assign gie = 1'b0; |
`else |
reg r_gie; |
|
initial r_gie = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_gie <= 1'b0; |
gie <= 1'b0; |
else if (w_switch_to_interrupt) |
r_gie <= 1'b0; |
gie <= 1'b0; |
else if (w_release_from_interrupt) |
r_gie <= 1'b1; |
assign gie = r_gie; |
`endif |
gie <= 1'b1; |
|
`ifdef OPT_NO_USERMODE |
assign trap = 1'b0; |
assign ubreak = 1'b0; |
`else |
reg r_trap; |
|
initial r_trap = 1'b0; |
initial trap = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_trap <= 1'b0; |
trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied |
r_trap <= 1'b1; |
trap <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie)) |
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
|
reg r_ubreak; |
|
initial r_ubreak = 1'b0; |
initial ubreak = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_ubreak <= 1'b0; |
ubreak <= 1'b0; |
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt)) |
r_ubreak <= 1'b1; |
ubreak <= 1'b1; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
|
assign trap = r_trap; |
assign ubreak = r_ubreak; |
`endif |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial ill_err_i = 1'b0; |
always @(posedge i_clk) |
1655,27 → 1580,18
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]); |
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline)) |
ill_err_i <= 1'b1; |
|
`ifdef OPT_NO_USERMODE |
assign ill_err_u = 1'b0; |
`else |
reg r_ill_err_u; |
|
initial r_ill_err_u = 1'b0; |
initial ill_err_u = 1'b0; |
always @(posedge i_clk) |
// The bit is automatically cleared on release from interrupt |
// or reset |
if ((i_rst)||(w_release_from_interrupt)) |
r_ill_err_u <= 1'b0; |
ill_err_u <= 1'b0; |
// If the supervisor (or debugger) writes to this register, |
// clearing the bit, then clear it |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline)) |
r_ill_err_u <= 1'b1; |
|
assign ill_err_u = r_ill_err_u; |
`endif |
ill_err_u <= 1'b1; |
`else |
assign ill_err_u = 1'b0; |
assign ill_err_i = 1'b0; |
1691,24 → 1607,16
else if ((bus_err)&&(~alu_gie)) |
ibus_err_flag <= 1'b1; |
// User bus error flag -- if ever set, it will cause an interrupt to |
// supervisor mode. |
`ifdef OPT_NO_USERMODE |
assign ubus_err_flag = 1'b0; |
`else |
reg r_ubus_err_flag; |
|
initial r_ubus_err_flag = 1'b0; |
// supervisor mode. |
initial ubus_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_ubus_err_flag <= 1'b0; |
ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(alu_gie)) |
r_ubus_err_flag <= 1'b1; |
ubus_err_flag <= 1'b1; |
|
assign ubus_err_flag = r_ubus_err_flag; |
`endif |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
1725,13 → 1633,8
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(~alu_gie)) |
r_idiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
`ifdef OPT_NO_USERMODE |
assign udiv_err_flag = 1'b0; |
`else |
// User divide (by zero) error flag -- if ever set, it will |
// cause a sudden switch interrupt to supervisor mode. |
// cause a sudden switch interrupt to supervisor mode. |
initial r_udiv_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
1742,8 → 1645,8
else if ((div_error)&&(alu_gie)) |
r_udiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
assign udiv_err_flag = r_udiv_err_flag; |
`endif |
end else begin |
assign idiv_err_flag = 1'b0; |
assign udiv_err_flag = 1'b0; |
1764,7 → 1667,7
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie)) |
r_ifpu_err_flag <= 1'b1; |
// User floating point error flag -- if ever set, it will cause |
// a sudden switch interrupt to supervisor mode. |
// a sudden switch interrupt to supervisor mode. |
initial r_ufpu_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)&&(w_release_from_interrupt)) |
1782,24 → 1685,16
assign ufpu_err_flag = 1'b0; |
end endgenerate |
|
`ifdef OPT_CIS |
reg r_ihalt_phase; |
`ifdef OPT_VLIW |
reg r_ihalt_phase, r_uhalt_phase; |
|
initial r_ihalt_phase = 0; |
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if (i_rst) |
r_ihalt_phase <= 1'b0; |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
r_ihalt_phase <= alu_phase; |
|
assign ihalt_phase = r_ihalt_phase; |
|
`ifdef OPT_NO_USERMODE |
assign uhalt_phase = 1'b0; |
`else |
reg r_uhalt_phase; |
|
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_uhalt_phase <= 1'b0; |
1808,8 → 1703,8
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc)) |
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT]; |
|
assign ihalt_phase = r_ihalt_phase; |
assign uhalt_phase = r_uhalt_phase; |
`endif |
`else |
assign ihalt_phase = 1'b0; |
assign uhalt_phase = 1'b0; |
1825,52 → 1720,58
// What happens when the pipeline has gie and ~gie instructions within |
// it? Do we clear both? What if a gie instruction tries to clear |
// a non-gie instruction? |
`ifdef OPT_NO_USERMODE |
assign upc = {(AW+2){1'b0}}; |
`else |
reg [(AW+1):0] r_upc; |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
upc <= wr_spreg_vl[(AW-1):0]; |
else if ((alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
r_upc <= { alu_pc, 2'b00 }; |
assign upc = r_upc; |
`endif |
upc <= alu_pc; |
|
always @(posedge i_clk) |
if (i_rst) |
ipc <= { RESET_BUS_ADDRESS, 2'b00 }; |
ipc <= RESET_ADDRESS; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((!alu_gie)&&(!alu_phase)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
ipc <= wr_spreg_vl[(AW-1):0]; |
else if ((~alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)) |
||(mem_pc_valid))) |
ipc <= { alu_pc, 2'b00 }; |
ipc <= alu_pc; |
|
always @(posedge i_clk) |
if (i_rst) |
pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; |
pf_pc <= RESET_ADDRESS; |
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache))) |
pf_pc <= { ipc[(AW+1):2], 2'b00 }; |
pf_pc <= ipc; |
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache))) |
pf_pc <= { upc[(AW+1):2], 2'b00 }; |
pf_pc <= upc; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
pf_pc <= wr_spreg_vl[(AW-1):0]; |
`ifdef OPT_PIPELINED |
else if ((dcd_early_branch)&&(~clear_pipeline)) |
pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 }; |
else if ((new_pc)||((!pf_stalled)&&(pf_valid))) |
pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 }; |
pf_pc <= dcd_branch_pc + 1; |
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |
`else |
else if ((alu_gie==gie)&&( |
((alu_pc_valid)&&(~clear_pipeline)) |
||(mem_pc_valid))) |
pf_pc <= { alu_pc[(AW-1):0], 2'b00 }; |
pf_pc <= alu_pc; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
`ifdef OPT_PIPELINED |
reg r_clear_icache; |
initial r_clear_icache = 1'b1; |
1883,63 → 1784,42
r_clear_icache <= 1'b0; |
assign w_clear_icache = r_clear_icache; |
`else |
assign w_clear_icache = i_clear_pf_cache; |
assign w_clear_icache = 1'b0; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(w_clear_icache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
// |
// The debug interface |
wire [31:0] w_debug_pc; |
`ifdef OPT_NO_USERMODE |
assign w_debug_pc[(AW+1):0] = { ipc, 2'b00 }; |
`else |
assign w_debug_pc[(AW+1):0] = { (i_dbg_reg[4]) |
? { upc[(AW+1):2], uhalt_phase, 1'b0 } |
: { ipc[(AW+1):2], ihalt_phase, 1'b0 } }; |
`endif |
generate |
if (AW<30) |
assign w_debug_pc[31:(AW+2)] = 0; |
endgenerate |
|
always @(posedge i_clk) |
if (AW<32) |
begin |
`ifdef OPT_NO_USERMODE |
o_dbg_reg <= regset[i_dbg_reg[3:0]]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
always @(posedge i_clk) |
begin |
o_dbg_reg[14:0] <= w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end |
`else |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
end else begin |
always @(posedge i_clk) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end |
`endif |
end |
end endgenerate |
|
always @(posedge i_clk) |
o_dbg_cc <= { o_break, bus_err, gie, sleep }; |
1952,12 → 1832,12
(~pf_cyc)&&(~mem_busy)&&(~alu_busy) |
&&(~div_busy)&&(~fpu_busy) |
// Operations must either be valid, or illegal |
&&((op_valid)||(i_rst)||(dcd_illegal)) |
&&((opvalid)||(i_rst)||(dcd_illegal)) |
// Decode stage must be either valid, in reset, or ill |
&&((dcd_valid)||(i_rst)||(pf_illegal))); |
&&((dcdvalid)||(i_rst)||(pf_illegal))); |
`else |
always @(posedge i_clk) |
r_halted <= (i_halt)&&((op_valid)||(i_rst)); |
r_halted <= (i_halt)&&((opvalid)||(i_rst)); |
`endif |
assign o_dbg_stall = ~r_halted; |
|
1977,24 → 1857,24
/* |
o_break, i_wb_err, pf_pc[1:0], |
flags, |
pf_valid, dcd_valid, op_valid, alu_valid, mem_valid, |
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid, |
op_ce, alu_ce, mem_ce, |
// |
master_ce, op_valid_alu, op_valid_mem, |
master_ce, opvalid_alu, opvalid_mem, |
// |
alu_stall, mem_busy, op_pipe, mem_pipe_stalled, |
mem_we, |
// ((op_valid_alu)&&(alu_stall)) |
// ||((op_valid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// op_Av[23:20], op_Av[3:0], |
// ((opvalid_alu)&&(alu_stall)) |
// ||((opvalid_mem)&&(~op_pipe)&&(mem_busy)) |
// ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))); |
// opA[23:20], opA[3:0], |
gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0] |
*/ |
/* |
i_rst, master_ce, (new_pc), |
((dcd_early_branch)&&(dcd_valid)), |
((dcd_early_branch)&&(dcdvalid)), |
pf_valid, pf_illegal, |
op_ce, dcd_ce, dcd_valid, dcd_stalled, |
op_ce, dcd_ce, dcdvalid, dcd_stalled, |
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err, |
pf_pc[7:0], pf_addr[7:0] |
*/ |
2004,20 → 1884,20
mem_busy, |
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we, |
o_wb_addr[8:0] } |
: { pf_instruction[31:21] }, |
: { instruction[31:21] }, |
pf_valid, (pf_valid) ? alu_pc[14:0] |
:{ pf_cyc, pf_stb, pf_pc[14:2] } |
:{ pf_cyc, pf_stb, pf_pc[12:0] } |
|
/* |
i_wb_err, gie, new_pc, dcd_early_branch, // 4 |
pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4 |
pf_instruction[30:27], // 4 |
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4 |
instruction[30:27], // 4 |
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4 |
dcd_valid, |
dcdvalid, |
((dcd_early_branch)&&(~clear_pipeline)) // 15 |
? dcd_branch_pc[14:0]:pf_pc[14:0] |
*/ |
}; |
`endif |
|
|
endmodule |
/idecode.v
1,4 → 1,4
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: idecode.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,20 → 31,14
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define CPU_SP_REG 4'hd |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
// |
62,8 → 56,7
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, o_ljmp, |
o_pipe, |
o_sim, o_sim_immv |
o_pipe |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH; |
74,7 → 67,7
input i_pf_valid, i_illegal; |
output wire o_phase; |
output reg o_illegal; |
output reg [AW:0] o_pc; |
output reg [(AW-1):0] o_pc; |
output reg o_gie; |
output reg [6:0] o_dcdR, o_dcdA, o_dcdB; |
output wire [31:0] o_I; |
89,8 → 82,6
output wire [(AW-1):0] o_branch_pc; |
output wire o_ljmp; |
output wire o_pipe; |
output reg o_sim /* verilator public_flat */; |
output reg [22:0] o_sim_immv /* verilator public_flat */; |
|
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire o_dcd_early_branch; |
111,18 → 102,18
wire w_dcdA_pc, w_dcdA_cc; |
wire w_dcdB_pc, w_dcdB_cc; |
wire [3:0] w_cond; |
wire w_wF, w_mem, w_sto, w_lod, w_div, w_fpu; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP; |
wire w_wR, w_rA, w_rB, w_wR_n; |
wire w_ljmp, w_ljmp_dly, w_cis_ljmp; |
wire w_ljmp, w_ljmp_dly; |
wire [31:0] iword; |
|
|
`ifdef OPT_CIS |
reg [15:0] r_nxt_half; |
`ifdef OPT_VLIW |
reg [16:0] r_nxt_half; |
assign iword = (o_phase) |
// set second half as a NOOP ... but really |
// set second half as a NOOP ... but really |
// shouldn't matter |
? { r_nxt_half[15:0], i_instruction[15:0] } |
? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 } |
: i_instruction; |
`else |
assign iword = { 1'b0, i_instruction[30:0] }; |
130,87 → 121,27
|
generate |
if (EARLY_BRANCHING != 0) |
begin |
`ifdef OPT_CIS |
reg r_pre_ljmp; |
always @(posedge i_clk) |
if ((i_rst)||(o_early_branch)) |
r_pre_ljmp <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_pre_ljmp <= (!o_phase)&&(i_instruction[31]) |
&&(i_instruction[14:0] == 15'h7cf8); |
else if (i_ce) |
r_pre_ljmp <= 1'b0; |
|
assign w_cis_ljmp = r_pre_ljmp; |
`else |
assign w_cis_ljmp = 1'b0; |
`endif |
// 0.1111.10010.000.1.1111.000000000... |
// 0111.1100.1000.0111.11000.... |
assign w_ljmp = (iword == 32'h7c87c000); |
end else begin |
assign w_cis_ljmp = 1'b0; |
else |
assign w_ljmp = 1'b0; |
end |
endgenerate |
|
`ifdef OPT_CIS |
`ifdef VERILATOR |
wire [4:0] w_cis_op; |
always @(iword) |
if (!iword[31]) |
w_cis_op = w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op = 5'h00; |
3'h1: w_cis_op = 5'h01; |
3'h2: w_cis_op = 5'h02; |
3'h3: w_cis_op = 5'h10; |
3'h4: w_cis_op = 5'h12; |
3'h5: w_cis_op = 5'h13; |
3'h6: w_cis_op = 5'h18; |
3'h7: w_cis_op = 5'h0d; |
endcase |
`else |
reg [4:0] w_cis_op; |
always @(iword,w_op) |
if (!iword[31]) |
w_cis_op <= w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op <= 5'h00; |
3'h1: w_cis_op <= 5'h01; |
3'h2: w_cis_op <= 5'h02; |
3'h3: w_cis_op <= 5'h10; |
3'h4: w_cis_op <= 5'h12; |
3'h5: w_cis_op <= 5'h13; |
3'h6: w_cis_op <= 5'h18; |
3'h7: w_cis_op <= 5'h0d; |
endcase |
`endif |
`else |
wire [4:0] w_cis_op; |
assign w_cis_op = w_op; |
`endif |
|
assign w_op= iword[26:22]; |
assign w_mov = (w_cis_op == 5'h0d); |
assign w_ldi = (w_cis_op[4:1] == 4'hc); |
assign w_brev = (w_cis_op == 5'h8); |
assign w_cmptst = (w_cis_op[4:1] == 4'h8); |
assign w_ldilo = (w_cis_op[4:0] == 5'h9); |
assign w_ALU = (!w_cis_op[4]) // anything with [4]==0, but ... |
&&(w_cis_op[3:1] != 3'h7); // not the divide |
assign w_mov = (w_op == 5'h0f); |
assign w_ldi = (w_op[4:1] == 4'hb); |
assign w_brev = (w_op == 5'hc); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldilo = (w_op[4:0] == 5'h9); |
assign w_ALU = (~w_op[4]); |
|
|
// w_dcdR (4 LUTs) |
// 4 LUTs |
// |
// What register will we be placing results into (if at all)? |
// |
// Two parts to the result register: the register set, given for |
// moves in iword[18] but only for the supervisor, and the other |
// moves in i_word[18] but only for the supervisor, and the other |
// four bits encoded in the instruction. |
// |
assign w_dcdR = { ((!iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
iword[30:27] }; |
// 2 LUTs |
// |
217,20 → 148,16
// If the result register is either CC or PC, and this would otherwise |
// be a floating point instruction with floating point opcode of 0, |
// then this is a NOOP. |
assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&( |
assign w_noop = (w_op[4:0] == 5'h18)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7)) |
||(IMPLEMENT_FPU==0)); |
|
// dcdB - What register is used in the opB? |
// |
assign w_dcdB[4] = ((!iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie; |
assign w_dcdB[3:0]= (iword[31]) |
? (((!iword[23])&&(iword[26:25]==2'b10)) |
? `CPU_SP_REG : iword[22:19]) |
: iword[17:14]; |
// 4 LUTs |
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie, |
iword[17:14] }; |
|
// 0 LUTs |
assign w_dcdA = w_dcdR; // on ZipCPU, A is always result reg |
assign w_dcdA = w_dcdR; |
// 2 LUTs, 1 delay each |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
238,8 → 165,8
assign w_dcdA_pc = w_dcdR_pc; |
assign w_dcdA_cc = w_dcdR_cc; |
// 2 LUTs, 1 delays each |
assign w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == `CPU_CC_REG); |
assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG); |
|
// Under what condition will we execute this |
// instruction? Only the load immediate instruction |
246,55 → 173,46
// is completely unconditional. |
// |
// 3+4 LUTs |
assign w_cond = ((w_ldi)||(iword[31])) ? 4'h8 : |
{ (iword[21:19]==3'h0), iword[21:19] }; |
assign w_cond = (w_ldi) ? 4'h8 : |
(iword[31])?{(iword[20:19]==2'b00), |
1'b0,iword[20:19]} |
: { (iword[21:19]==3'h0), iword[21:19] }; |
|
// 1 LUT |
assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00); |
assign w_sto = (w_mem)&&( w_cis_op[0]); |
assign w_lod = (w_mem)&&(!w_cis_op[0]); |
assign w_dcdM = (w_op[4:1] == 4'h9); |
// 1 LUT |
assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7); |
// 2 LUTs |
assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11) |
&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00); |
// |
// rA - do we need to read register A? |
assign w_rA = // Floating point reads reg A |
((w_fpu)&&(w_cis_op[4:1] != 4'hf)) |
// Divide's read A |
||(w_div) |
// ALU ops read A, |
// except for MOV's and BREV's which don't |
||((w_ALU)&&(!w_brev)&&(!w_mov)) |
// STO's read A |
||(w_sto) |
// Test/compares |
||(w_cmptst); |
// rB -- do we read a register for operand B? Specifically, do we |
// add the registers value to the immediate to create opB? |
assign w_rB = (w_mov) |
||((!iword[31])&&(iword[18])&&(!w_ldi)) |
||(( iword[31])&&(iword[23])&&(!w_ldi)) |
// If using compressed instruction sets, |
// we *always* read on memory operands. |
||(( iword[31])&&(w_mem)); |
// wR -- will we be writing our result back? |
// wR_n = !wR |
assign w_dcdDV = (w_op[4:1] == 4'ha); |
// 1 LUT |
assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7); |
// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before) |
// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV |
assign w_rA = (w_dcdFP) |
// Divide's read A |
||(w_dcdDV) |
// ALU read's A, unless it's a MOV to A |
// This includes LDIHI/LDILO |
||((~w_op[4])&&(w_op[3:0]!=4'hf)) |
// STO's read A |
||((w_dcdM)&&(w_op[0])) |
// Test/compares |
||(w_op[4:1]== 4'h8); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi)); |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = (w_sto) |
||((!iword[31])&&(w_cis_op[4:3]==2'b11) |
&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7)) |
assign w_wR_n = ((w_dcdM)&&(w_op[0])) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
assign w_wR = ~w_wR_n; |
// |
// wF -- do we write flags when we are done? |
// |
// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits) |
// |
// This'd be 4 LUTs, save that we have the carve out for NOOPs |
// and writes to the PC/CC register(s). |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_fpu)||(w_div) |
||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev) |
&&(w_dcdR[3:1] != 3'h7)))); |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev) |
&&(iword[30:28] != 3'h7)))); |
|
// Bottom 13 bits: no LUT's |
// w_dcd[12: 0] -- no LUTs |
306,23 → 224,16
wire w_Iz; |
|
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI |
// MOVE immediates have one less bit |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } |
// Normal Op-B immediate ... 18 or 14 bits |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move |
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] } |
: { {(23-14){iword[13]}}, iword[13:0] } |
)); |
|
`ifdef OPT_CIS |
wire [7:0] w_halfbits; |
assign w_halfbits = iword[23:16]; |
|
wire [7:0] w_halfI; |
assign w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0] |
:(w_halfbits[7])? |
{ {(6){w_halfbits[2]}}, w_halfbits[1:0]} |
:{ w_halfbits[6], w_halfbits[6:0] }; |
assign w_I = (iword[31])?{{(23-8){w_halfI[7]}}, w_halfI }:w_fullI; |
`ifdef OPT_VLIW |
wire [5:0] w_halfI; |
assign w_halfI = (w_ldi) ? iword[5:0] |
:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]}); |
assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI; |
`else |
assign w_I = w_fullI; |
`endif |
329,12 → 240,12
assign w_Iz = (w_I == 0); |
|
|
`ifdef OPT_CIS |
`ifdef OPT_VLIW |
// |
// The o_phase parameter is special. It needs to let the software |
// following know that it cannot break/interrupt on an o_phase asserted |
// instruction, lest the break take place between the first and second |
// half of a CIS instruction. To do this, o_phase must be asserted |
// half of a VLIW instruction. To do this, o_phase must be asserted |
// when the first instruction half is valid, but not asserted on either |
// a 32-bit instruction or the second half of a 2x16-bit instruction. |
reg r_phase; |
344,10 → 255,7
||(o_early_branch)||(w_ljmp_dly)) |
r_phase <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_phase <= (o_phase)? 1'b0 |
: ((i_instruction[31])&&(i_pf_valid)); |
else if (i_ce) |
r_phase <= 1'b0; |
r_phase <= (o_phase)? 1'b0:(i_instruction[31]); |
// Phase is '1' on the first instruction of a two-part set |
// But, due to the delay in processing, it's '1' when our output is |
// valid for that first part, but that'll be the same time we |
366,32 → 274,32
o_illegal <= 1'b0; |
else if (i_ce) |
begin |
`ifdef OPT_CIS |
`ifdef OPT_VLIW |
o_illegal <= (i_illegal); |
`else |
o_illegal <= ((i_illegal) || (i_instruction[31])); |
`endif |
if ((IMPLEMENT_MPY==0)&&((w_cis_op[4:1]==4'h5)||(w_cis_op[4:0]==5'h0c))) |
if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08))) |
o_illegal <= 1'b1; |
|
if ((IMPLEMENT_DIVIDE==0)&&(w_div)) |
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_div)&&(w_dcdR[3:1]==3'h7)) |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
|
|
if ((IMPLEMENT_FPU==0)&&(w_fpu)) |
if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP)) |
o_illegal <= 1'b1; |
|
if ((w_cis_op[4:3]==2'b11)&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7) |
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7) |
&&( |
(w_cis_op[2:0] != 3'h4) // BREAK |
(w_op[2:0] != 3'h1) // BREAK |
`ifdef OPT_PIPELINED |
&&(w_cis_op[2:0] != 3'h5) // LOCK |
&&(w_op[2:0] != 3'h2) // LOCK |
`endif |
// SIM instructions are always illegal |
&&(w_cis_op[2:0] != 3'h7))) // NOOP |
&&(w_op[2:0] != 3'h0))) // NOOP |
o_illegal <= 1'b1; |
end |
|
399,19 → 307,16
always @(posedge i_clk) |
if (i_ce) |
begin |
`ifdef OPT_CIS |
if (!o_phase) |
`ifdef OPT_VLIW |
if (~o_phase) |
begin |
o_gie<= i_gie; |
|
if ((iword[31])&&(!o_phase)) |
o_pc <= { i_pc, 1'b1 }; |
else if ((iword[31])&&(i_pf_valid)) |
o_pc <= { i_pc, 1'b0 }; |
else |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
// i.e. dcd_pc+1 |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
end |
`else |
o_gie<= i_gie; |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
`endif |
|
// Under what condition will we execute this |
429,12 → 334,12
// the ALU. Likewise, the two compare instructions |
// CMP and TST becomes SUB and AND here as well. |
// We keep only the bottom four bits, since we've |
// already done the rest of the decode necessary to |
// already done the rest of the decode necessary to |
// settle between the other instructions. For example, |
// o_FP plus these four bits uniquely defines the FP |
// instruction, o_DV plus the bottom of these defines |
// the divide, etc. |
o_op <= ((w_ldi)||(w_noop))? 4'hd : w_cis_op[3:0]; |
o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0]; |
|
// Default values |
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR}; |
446,36 → 351,29
r_I <= w_I; |
o_zI <= w_Iz; |
|
// Turn a NOOP into an ALU operation--subtract in |
// Turn a NOOP into an ALU operation--subtract in |
// particular, although it doesn't really matter as long |
// as it doesn't take longer than one clock. Note |
// also that this depends upon not setting any registers |
// or flags, which should already be true. |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); |
o_M <= w_mem; |
o_DV <= w_div; |
o_FP <= w_fpu; |
|
o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&( |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT |
o_M <= w_dcdM; |
o_DV <= w_dcdDV; |
o_FP <= w_dcdFP; |
|
o_break <= (w_op[4:0]==5'b11001)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`ifdef OPT_PIPELINED |
r_lock <= (!iword[31])&&(w_op[4:0]==5'h1d)&&( |
r_lock <= (w_op[4:0]==5'b11010)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`endif |
`ifdef OPT_CIS |
r_nxt_half <= { iword[31], iword[14:0] }; |
`ifdef OPT_VLIW |
r_nxt_half <= { iword[31], iword[13:5], |
((iword[21])? iword[20:19] : 2'h0), |
iword[4:0] }; |
`endif |
|
`ifdef VERILATOR |
// Support the SIM instruction(s) |
o_sim <= (!iword[31])&&(w_op[4:1] == 4'hf) |
&&(w_dcdR[3:1] == 3'h7); |
`else |
o_sim <= 1'b0; |
`endif |
o_sim_immv <= iword[22:0]; |
end |
|
`ifdef OPT_PIPELINED |
494,10 → 392,6
always @(posedge i_clk) |
if (i_rst) |
r_ljmp <= 1'b0; |
`ifdef OPT_CIS |
else if ((i_ce)&&(o_phase)) |
r_ljmp <= w_cis_ljmp; |
`endif |
else if ((i_ce)&&(i_pf_valid)) |
r_ljmp <= (w_ljmp); |
assign o_ljmp = r_ljmp; |
510,14 → 404,17
if (r_ljmp) |
// LOD (PC),PC |
r_early_branch <= 1'b1; |
else if ((!iword[31])&&(iword[30:27]==`CPU_PC_REG) |
&&(w_cond[3])) |
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
begin |
if ((w_op[4:0]==5'h02)&&(!iword[18])) |
if (w_op[4:1] == 4'hb) // LDI to PC |
// LDI x,PC |
r_early_branch <= 1'b1; |
else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
// Add x,PC |
r_early_branch <= 1'b1; |
else |
else begin |
r_early_branch <= 1'b0; |
end |
end else |
r_early_branch <= 1'b0; |
end else if (i_ce) |
527,10 → 424,12
if (i_ce) |
begin |
if (r_ljmp) |
r_branch_pc <= iword[(AW+1):2]; |
r_branch_pc <= iword[(AW-1):0]; |
else if (w_op[4:1] == 4'hb) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
else // Add x,PC |
r_branch_pc <= i_pc |
+ {{(AW-15){iword[17]}},iword[16:2]} |
+ {{(AW-17){iword[17]}},iword[16:0]} |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
560,26 → 459,15
initial r_pipe = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
r_pipe <= (r_valid)&&((i_pf_valid)||(o_phase)) |
// Both must be memory operations |
&&(w_mem)&&(o_M) |
// Both must be writes, or both stores |
&&(o_op[0] == w_cis_op[0]) |
// Both must be register ops |
&&(w_rB) |
// Both must use the same register for B |
&&(w_dcdB[3:0] == o_dcdB[3:0]) |
// But ... the result can never be B |
&&((o_op[0]) |
||(w_dcdB[3:0] != o_dcdA[3:0])) |
// Needs to be to the mode, supervisor or user |
r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31]) |
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22]) |
&&(i_instruction[17:14] == o_dcdB[3:0]) |
&&(i_instruction[17:14] != o_dcdA[3:0]) |
&&(i_gie == o_gie) |
// Same condition, or no condition before |
&&((i_instruction[21:19]==o_cond[2:0]) |
||(o_cond[2:0] == 3'h0)) |
// Same immediate |
&&((w_I[13:2]==r_I[13:2]) |
||({1'b0, w_I[13:2]}==(r_I[13:2]+12'h1))); |
&&((i_instruction[13:0]==r_I[13:0]) |
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1))); |
assign o_pipe = r_pipe; |
`else |
assign o_pipe = 1'b0; |
594,8 → 482,8
r_valid <= 1'b1; |
else if (~i_stalled) |
r_valid <= 1'b0; |
|
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; |
|
endmodule |
/pipefetch.v
30,7 → 30,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
42,11 → 42,6
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
53,7 → 48,6
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc, |
o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
/idecode_deprecated.v
0,0 → 1,320
/////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: idecode_deprecated.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This RTL file specifies how the original instruction set was |
// to be decoded into a machine understandable microcode. It has |
// been drawn out of zipcpu.v in an effort to provide some encapsulation, |
// some of measuring its performance independently, and some means of |
// updating it without impacting everything else (much). |
// |
// It has since been deprecated by a newer version of the instruction |
// set architecture. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
// |
// |
// |
module idecode_deprecated(i_clk, i_rst, i_ce, i_stalled, |
i_instruction, i_gie, i_pc, i_pf_valid, i_illegal, |
o_phase, o_illegal, |
o_pc, o_gie, o_R, o_A, o_B, |
o_I, o_zI, o_cond, o_wF, o_op, |
o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, o_pipe |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
IMPLEMENT_DIVIDE=0, IMPLEMENT_FPU=0, AW=ADDRESS_WIDTH; |
input i_clk, i_rst, i_ce, i_stalled; |
input [31:0] i_instruction; |
input i_gie; |
input [(AW-1):0] i_pc; |
input i_pf_valid, i_illegal; |
output wire o_phase; |
output reg o_illegal; |
output reg [(AW-1):0] o_pc; |
output reg o_gie; |
output wire [6:0] o_R; |
output reg [6:0] o_A, o_B; |
output wire [31:0] o_I; |
output reg o_zI; |
output reg [3:0] o_cond; |
output reg o_wF; |
output reg [3:0] o_op; |
output wire o_ALU, o_DV, o_FP; |
output reg o_M, o_break, o_lock; |
output reg o_wR, o_rA, o_rB; |
output wire o_early_branch; |
output wire [(AW-1):0] o_branch_pc; |
output wire o_pipe; |
|
|
assign o_phase = 1'b0; |
assign o_R = { (o_A[6]), (o_A[5]), o_A[4:0] }; |
|
// |
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Variable declarations |
// |
// |
reg [23:0] r_I; |
reg r_zI; // true if dcdI == 0 |
|
generate |
if (EARLY_BRANCHING != 0) |
begin |
reg r_early_branch; |
reg [(AW-1):0] r_branch_pc; |
assign o_early_branch = r_early_branch; |
assign o_branch_pc = r_branch_pc; |
|
always @(posedge i_clk) |
if ((i_ce)&&(i_pf_valid)&&(i_instruction[27:24]==`CPU_PC_REG)) |
begin |
r_early_branch <= 1'b0; |
// First case, a move to PC instruction |
if ((i_instruction[31:28] == 4'h2) |
// Offsets of the PC register *only* |
&&(i_instruction[19:16] == `CPU_PC_REG) |
&&((i_gie) |
||((~i_instruction[20])&&(~i_instruction[15]))) |
&&(i_instruction[23:21]==3'h0)) // Unconditional |
begin |
r_early_branch <= 1'b1; |
|
end else // Next case, an Add Imm -> PC instruction |
if ((i_instruction[31:28] == 4'ha) // Add |
&&(~i_instruction[20]) // Immediate |
&&(i_instruction[23:21]==3'h0)) // Always |
begin |
r_early_branch <= 1'b1; |
end else // Next case: load Immediate to PC |
if (i_instruction[31:28] == 4'h3) |
begin |
r_early_branch <= 1'b1; |
end |
end else |
begin |
if (i_ce) r_early_branch <= 1'b0; |
end |
|
if (AW == 24) |
begin |
always @(posedge i_clk) |
if (i_ce) |
begin |
if (i_instruction[31]) // Add |
begin |
r_branch_pc <= i_pc |
+ { {(AW-20){i_instruction[19]}}, i_instruction[19:0] } |
+ {{(AW-1){1'b0}},1'b1}; |
end else if (~i_instruction[28]) // 4'h2 = MOV |
r_branch_pc <= i_pc+{ {(AW-15){i_instruction[14]}}, i_instruction[14:0] } + {{(AW-1){1'b0}},1'b1}; |
else // if (i_instruction[28]) // 4'h3 = LDI |
r_branch_pc <= i_pc+{ i_instruction[23:0] } + {{(AW-1){1'b0}},1'b1}; |
end |
end else begin |
always @(posedge i_clk) |
if (i_ce) |
begin |
if (i_instruction[31]) // Add |
begin |
r_branch_pc <= i_pc |
+ { {(AW-20){i_instruction[19]}}, i_instruction[19:0] } |
+ {{(AW-1){1'b0}},1'b1}; |
end else if (~i_instruction[28]) // 4'h2 = MOV |
begin |
r_branch_pc <= i_pc+{ {(AW-15){i_instruction[14]}}, i_instruction[14:0] } + {{(AW-1){1'b0}},1'b1}; |
end else // if (i_instruction[28]) // 4'h3 = LDI |
begin |
r_branch_pc <= i_pc+{ {(AW-24){i_instruction[23]}}, i_instruction[23:0] } + {{(AW-1){1'b0}},1'b1}; |
end |
end |
end end else begin // No early branching |
// wire o_early_branch; |
// wire [(AW-1):0] o_branch_pc; |
assign o_early_branch = 1'b0; |
assign o_branch_pc = {(AW){1'b0}}; |
end endgenerate |
|
wire [4:0] w_A, w_B; |
wire w_mpy, w_wF, w_ldixx, w_zI; |
wire [3:0] w_op; |
wire [23:0] w_I; |
|
assign w_op= i_instruction[31:28]; |
assign w_I = (w_op == 4'h2) ? |
{ {(9){i_instruction[14]}},i_instruction[14:0] } |
: ((w_op == 4'h3) ? { i_instruction[23:0] } |
: ((w_op == 4'h4) ? { 8'h00, i_instruction[15:0] } |
: (((w_op[3:1]==3'h3)&&(i_instruction[20])) ? |
{ {(8){i_instruction[15]}},i_instruction[15:0] } |
: (((w_op[3:1]==3'h3)&&(~i_instruction[20])) ? |
{ {(4){i_instruction[19]}},i_instruction[19:0] } |
: (i_instruction[20]) ? |
{ {(8){i_instruction[15]}},i_instruction[15:0] } |
: { {(4){i_instruction[19]}},i_instruction[19:0] } |
)))); |
assign w_zI = (w_I == 0); |
|
assign w_mpy = ((w_op == 4'h4)&&(i_instruction[27:25]!=3'h7)); |
assign w_ldixx = ((w_op == 4'h4)&&(i_instruction[27:24]==4'hf)); |
|
// 4 LUTs |
assign w_A = { (((w_op==4'h2)&&(~i_gie))?i_instruction[20]:i_gie), |
(w_ldixx)?(i_instruction[19:16]):(i_instruction[27:24])}; |
|
// 1 LUT |
assign w_B = { (((w_op==4'h2)&&(~i_gie))?i_instruction[15]:i_gie), |
(i_instruction[19:16]) }; |
|
// Don't change the flags on conditional instructions, |
// UNLESS: the conditional instruction was a CMP or TST instruction. |
// 8 LUTs |
assign w_wF= (w_op[3:1]==3'h0) |
||((i_instruction[23:21]==3'h0)&&((w_op[3])||(w_mpy))); |
|
|
always @(posedge i_clk) |
if (i_ce) |
begin |
o_pc <= i_pc +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1 |
|
// Record what operation we are doing |
o_op <= (w_op == 4'h3) ? 4'h2 |
: ((w_op == 4'h4) ? |
((i_instruction[27:24]==4'he) ? 4'h2 |
:((i_instruction[27:24]==4'hf) ? |
(i_instruction[20]? 4'h7:4'h6) |
:(i_instruction[20]? 4'h4:4'h3))) |
: w_op); |
|
// Default values |
o_A <= {(w_A[3:0]==`CPU_CC_REG),(w_A[3:0]==`CPU_PC_REG),w_A}; |
o_B <= {(w_B[3:0]==`CPU_CC_REG),(w_B[3:0]==`CPU_PC_REG),w_B}; |
o_M <= (w_op[3:1] == 3'h3); |
r_I <= w_I; |
o_zI<= w_zI; |
|
o_wF <= w_wF; |
|
// 4 LUTs |
o_rA <= (w_op[3:0] != 4'h2) |
&&(w_op[3:0] != 4'h3) |
&&((w_op[3:0] != 4'h4)||(i_instruction[27:24]!=4'he)) |
&&(w_op[3:0] != 4'h6); |
|
// function of 11 bits, -- ugly |
o_rB <= (w_op[3:0] != 4'h3) // Don't read for LDI |
// Don't read for LODxx, NOOP, or MPYxI |
&&((w_op[3:0] != 4'h4) |
||(i_instruction[27:25]!=3'h7) |
&&(i_instruction[19:16]!=4'hf)) |
// Always read on MOVE, or when OpB requests it |
&&((w_op[3:0]==4'h2)||(i_instruction[20]) |
||(w_op[3:0]==4'h4)); |
|
// Always write back ... unless we are doing a store, |
// CMP/TST, or a NOOP/BREAK |
// 4 LUTs |
o_wR <= (w_op[3:1] != 3'h0) |
&&(w_op[3:0] != 4'h7) |
&&((w_op[3:0] != 4'h4) |
||(i_instruction[27:24] != 4'he)); |
|
o_illegal <= i_illegal; |
|
// Set the condition under which we do this operation |
// The top four bits are a mask, the bottom four the |
// value the flags must equal once anded with the mask |
o_cond <= (i_instruction[31:28]==4'h3)? 4'h8 |
: { (i_instruction[23:21]==3'h0), |
i_instruction[23:21]}; |
casez(i_instruction[31:28]) |
4'h2: begin // Move instruction |
end |
4'h3: begin // Load immediate |
o_op <= 4'h2; |
end |
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK |
if (i_instruction[27:24] == 4'he) |
begin |
// NOOP instruction |
// Might also be a break. Big |
// instruction set hole here. |
o_illegal <= (i_illegal)||(i_instruction[23:3] != 0); |
end else if (i_instruction[27:24] == 4'hf) |
begin // Load partial immediate(s) |
// o_op <= { 3'h3, instruction[20] }; |
end else begin |
// Actual multiply instruction |
// dcdA_rd <= 1'b1; |
// dcdB_rd <= (i_instruction[19:16] != 4'hf); |
// o_op[3:0] <= (i_instruction[20])? 4'h4:4'h3; |
end end |
default: begin |
end |
endcase |
o_gie <= i_gie; |
end |
|
initial o_break = 1'b0; |
initial o_lock = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
begin // 6 LUTs |
o_break <= (i_instruction[31:0] == 32'h4e000001); |
o_lock <= (i_instruction[31:0] == 32'h4e000002); |
end |
|
assign o_I = { {(32-24){r_I[23]}}, r_I}; |
assign o_ALU = (~o_M); |
assign o_DV = 1'b0; |
assign o_FP = 1'b0; |
|
always @(posedge i_clk) |
if (i_ce) |
begin |
o_pipe <= (o_valid)&&(i_valid) |
&&(o_M)&&(w_op[3:1] == 3'h3)&&(w_op[0]==o_op[0]) |
&&(i_instruction[19:16] == o_B[3:0]) |
&&(i_gie == o_gie) |
&&((i_instruction[23:21]==o_cond) |
||(o_cond == 3'h0)) |
&&((i_instruction[15:0] == r_I[15:0]) |
||(i_instruction[15:0] == (r_I[15:0]+16'h1))); |
end |
|
endmodule |
/memops.v
1,4 → 1,4
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memops.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,31 → 31,24
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
/////////////////////////////////////////////////////////////////////////// |
// |
// |
module memops(i_clk, i_rst, i_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0, WITH_LOCAL_BUS=0; |
localparam AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_stb, i_lock; |
// CPU interface |
input [2:0] i_op; |
input i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
73,7 → 66,6
output reg o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
80,8 → 72,8
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff); |
assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff)); |
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
initial r_wb_cyc_gbl = 1'b0; |
initial r_wb_cyc_lcl = 1'b0; |
112,54 → 104,13
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); |
else |
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation |
|
reg [3:0] r_op; |
always @(posedge i_clk) |
if (i_stb) |
begin |
o_wb_we <= i_op[0]; |
casez({ i_op[2:1], i_addr[1:0] }) |
`ifdef ZERO_ON_IDLE |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
`else |
4'b10??: o_wb_data <= { (2){ i_data[15:0] } }; |
4'b11??: o_wb_data <= { (4){ i_data[7:0] } }; |
`endif |
default: o_wb_data <= i_data; |
endcase |
|
o_wb_addr <= i_addr[(AW+1):2]; |
`ifdef SET_SEL_ON_READ |
if (i_op[0] == 1'b0) |
o_wb_sel <= 4'hf; |
else |
`endif |
casez({ i_op[2:1], i_addr[1:0] }) |
4'b01??: o_wb_sel <= 4'b1111; |
4'b100?: o_wb_sel <= 4'b1100; |
4'b101?: o_wb_sel <= 4'b0011; |
4'b1100: o_wb_sel <= 4'b1000; |
4'b1101: o_wb_sel <= 4'b0100; |
4'b1110: o_wb_sel <= 4'b0010; |
4'b1111: o_wb_sel <= 4'b0001; |
default: o_wb_sel <= 4'b1111; |
endcase |
r_op <= { i_op[2:1] , i_addr[1:0] }; |
o_wb_we <= i_op; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW-1):0]; |
end |
`ifdef ZERO_ON_IDLE |
else if ((!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl)) |
begin |
o_wb_we <= 1'b0; |
o_wb_addr <= 0; |
o_wb_data <= 32'h0; |
o_wb_sel <= 4'h0; |
end |
`endif |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
173,21 → 124,8
if (i_stb) |
o_wreg <= i_oreg; |
always @(posedge i_clk) |
`ifdef ZERO_ON_IDLE |
if (!i_wb_ack) |
o_result <= 32'h0; |
else |
`endif |
casez(r_op) |
4'b01??: o_result <= i_wb_data; |
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] }; |
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] }; |
default: o_result <= i_wb_data; |
endcase |
if (i_wb_ack) |
o_result <= i_wb_data; |
|
generate |
if (IMPLEMENT_LOCK != 0) |
/prefetch.v
24,7 → 24,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
36,11 → 36,6
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
47,7 → 42,6
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Flash requires a minimum of 4 clocks per byte to read, so that would be |
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline |
// mode which this prefetch does not support. In non--pipelined mode, the |
120,7 → 114,7
if ((o_wb_cyc)&&(i_wb_ack)) |
begin |
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err); |
o_illegal <= (i_wb_err)&&(i_pc == o_wb_addr); |
o_illegal <= i_wb_err; |
end else if (i_stalled_n) |
begin |
o_valid <= 1'b0; |
/cpuops_deprecated.v
0,0 → 1,164
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpuops_deprecated.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This is the ALU within the Zip CPU. This particular version, |
// however, has been deprecated in favor of the newer instruction |
// set. The primary difference is that this instruction set doesn't |
// offer the bit reversal or population count instructions, and the |
// newer ALU reorders the opcodes. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module cpuops_deprecated(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, |
o_c, o_f, o_valid, o_illegal); |
parameter IMPLEMENT_MPY = 1; |
input i_clk, i_rst, i_ce; |
input [3:0] i_op; |
input [31:0] i_a, i_b; |
input i_valid; |
output reg [31:0] o_c; |
output wire [3:0] o_f; |
output reg o_valid; |
output wire o_illegal; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result; |
assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}} |
: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR |
assign w_lsr_result = (|i_b[31:5])? 33'h00 |
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR |
|
|
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
always @(posedge i_clk) |
if (i_ce) |
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP |
&&(i_a[31] != i_b[31])) |
||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD |
||(i_op == 4'hd) // LSL |
||(i_op == 4'hf)); // LSR |
|
|
// A 4-way multiplexer can be done in one 6-LUT. |
// A 16-way multiplexer can therefore be done in 4x 6-LUT's with |
// the Xilinx multiplexer fabric that follows. |
// Given that we wish to apply this multiplexer approach to 33-bits, |
// this will cost a minimum of 132 6-LUTs. |
generate |
if (IMPLEMENT_MPY == 0) |
begin |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB |
4'b?001: o_c <= i_a & i_b; // BTST/And |
// 4'h3: There's a hole here for the unimplemented MPYU, |
// 4'h4: and here for the unimplemented MPYS |
4'h5: o_c <= w_rol_result; // ROL |
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
4'ha: { c, o_c } <= i_a + i_b; // Add |
4'hb: o_c <= i_a | i_b; // Or |
4'hc: o_c <= i_a ^ i_b; // Xor |
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR |
default: o_c <= i_b; // MOV, LDI |
endcase |
end |
end else begin |
// |
// Multiply pre-logic |
// |
wire signed [16:0] w_mpy_a_input, w_mpy_b_input; |
wire signed [33:0] w_mpy_result; |
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] }; |
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] }; |
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input; |
|
|
// |
// The master ALU case statement |
// |
always @(posedge i_clk) |
if (i_ce) |
begin |
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB |
4'b?001: o_c <= i_a & i_b; // BTST/And |
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU |
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS |
4'h5: o_c <= w_rol_result; // ROL |
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
4'ha: { c, o_c } <= i_a + i_b; // Add |
4'hb: o_c <= i_a | i_b; // Or |
4'hc: o_c <= i_a ^ i_b; // Xor |
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR |
default: o_c <= i_b; // MOV, LDI |
endcase |
end |
end endgenerate |
|
generate |
if (IMPLEMENT_MPY == 0) |
begin |
reg r_illegal; |
always @(posedge i_clk) |
r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4)); |
assign o_illegal = r_illegal; |
end else |
assign o_illegal = 1'b0; |
endgenerate |
|
assign z = (o_c == 32'h0000); |
assign n = (o_c[31]); |
assign v = (set_ovfl)&&(pre_sign != o_c[31]); |
|
assign o_f = { v, n, c, z }; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
o_valid <= 1'b0; |
else |
o_valid <= (i_ce)&&(i_valid); |
endmodule |