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Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/rtl/core
    from Rev 9 to Rev 3
    Reverse comparison

Rev 9 → Rev 3

/zipcpu.v
121,7 → 121,7
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_data,
// Accounting/CPU usage interface
o_op_stall, o_pf_stall, o_i_count);
o_mem_stall, o_pf_stall, o_alu_stall);
parameter RESET_ADDRESS=32'h0100000;
input i_clk, i_rst, i_interrupt;
// Debug interface -- inputs
140,31 → 140,30
input i_wb_ack, i_wb_stall;
input [31:0] i_wb_data;
// Accounting outputs ... to help us count stalls and usage
output wire o_op_stall;
output wire o_mem_stall;
output wire o_pf_stall;
output wire o_i_count;
output wire o_alu_stall;
 
// Registers
reg [31:0] regset [0:31];
 
// Condition codes
reg [3:0] flags, iflags; // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
wire master_ce;
wire [7:0] w_uflags, w_iflags;
reg break_en, step, gie, sleep;
reg step, gie, sleep, break_en;
 
// The master chip enable
wire master_ce;
wire [4:0] mem_wreg;
wire mem_busy, mem_rdbusy;
 
reg [31:0] pf_pc;
reg new_pc;
 
//
//
// PIPELINE STAGE #1 :: Prefetch
// Variable declarations
//
reg [31:0] pf_pc;
reg new_pc;
 
wire dcd_stalled;
wire pf_ce, dcd_stalled;
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
wire [31:0] pf_addr, pf_data;
wire [31:0] instruction, instruction_pc;
232,9 → 231,6
wire mem_ce, mem_stalled;
wire mem_valid, mem_ack, mem_stall,
mem_cyc, mem_stb, mem_we;
wire [4:0] mem_wreg;
 
wire mem_busy, mem_rdbusy;
wire [31:0] mem_addr, mem_data, mem_result;
 
 
261,6 → 257,7
//
// PIPELINE STAGE #1 :: Prefetch
// Calculate stall conditions
assign pf_ce = (~dcd_stalled);
 
//
// PIPELINE STAGE #2 :: Instruction Decode
303,9 → 300,6
//
//
`ifdef SINGLE_FETCH
wire pf_ce;
 
assign pf_ce = (~dcd_stalled);
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
instruction, instruction_pc, instruction_gie,
pf_valid,
796,7 → 790,9
// it? Do we clear both? What if a gie instruction tries to clear
// a non-gie instruction?
always @(posedge i_clk)
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
if (i_rst)
upc <= RESET_ADDRESS;
else if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
upc <= wr_reg_vl;
else if ((alu_gie)&&(alu_pc_valid))
upc <= alu_pc;
827,6 → 823,7
else if ((i_halt)&&(i_dbg_we)
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
pf_pc <= i_dbg_data;
// else if (pf_ce)
else if (dcd_ce)
pf_pc <= pf_pc + 1;
 
868,7 → 865,11
// later evaluate how well we are doing.
//
//
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
assign o_pf_stall = (master_ce)&&(~pf_valid);
assign o_i_count = alu_pc_valid;
assign o_mem_stall = (~i_halt)&&(~sleep)&&(opvalid)&&(mem_busy)
&&(~pf_cyc);
assign o_pf_stall = (~i_halt)&&(~sleep)&&(((pf_ce)&&(~pf_valid))
||((opvalid)&&(mem_busy)&&(pf_cyc)));
// assign o_alu_stall = (~i_halt)&&(~sleep)&&(~mem_busy)&&
// ((alu_stall)||(~alu_valid));
assign o_alu_stall = alu_pc_valid;
endmodule

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