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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/rtl
    from Rev 115 to Rev 118
    Reverse comparison

Rev 115 → Rev 118

/core/idecode.v
98,16 → 98,9
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
wire w_wR, w_rA, w_rB, w_wR_n;
wire w_ljmp;
wire [31:0] iword;
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
wire [31:0] iword;
`ifdef OPT_VLIW
reg [16:0] r_nxt_half;
assign iword = (o_phase)
119,6 → 112,14
assign iword = { 1'b0, i_instruction[30:0] };
`endif
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
assign w_op= iword[26:22];
assign w_mov = (w_op == 5'h0f);
assign w_ldi = (w_op[4:1] == 4'hb);
/core/pfcache.v
91,18 → 91,13
 
initial tagval = 0;
always @(posedge i_clk)
if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}})
&&(i_wb_ack)&&(~i_wb_err))
// Our tag value changes any time we finish reading a
// new cache line
tagval <= o_wb_addr[(AW-1):CW];
else if ((i_stall_n)&&(~o_wb_cyc))
// Otherwise, as long as we're not reading new stuff,
// the tag line changes any time the pipeline steps
// forwards. Our purpose here is primarily just to
// catch sudden changes. The result is that walking
// from one cache line to the next will cost a clock.
tagval <= tags[i_pc[(CW-1):PW]];
// It may be possible to recover a clock once the cache line
// has been filled, but our prior attempt to do so has lead
// to a race condition, so we keep this logic simple.
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc))
lastpc <= tags[i_pc[(CW-1):PW]];
else
tagval <= tags[lastpc[(CW-1):PW]];
 
// i_pc will only increment when everything else isn't stalled, thus
// we can set it without worrying about that. Doing this enables
202,10 → 197,12
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
vmask <= 0;
else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
vmask[lastpc[(CW-1):PW]] <= 1'b0;
else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
else begin
if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
vmask[lastpc[(CW-1):PW]] <= 1'b0;
end
 
reg illegal_valid;
initial illegal_cache = 0;
/core/zipcpu.v
1279,7 → 1279,9
assign o_break = (((break_en)||(~op_gie))&&(op_break)
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
&&(~clear_pipeline))
||((~alu_gie)&&(bus_err));
||((~alu_gie)&&(bus_err))
||((~alu_gie)&&(div_valid)&&(div_error))
||((~alu_gie)&&(fpu_valid)&&(fpu_error));
`endif
 
 
1632,7 → 1634,7
`ifdef DEBUG_SCOPE
always @(posedge i_clk)
o_debug <= {
pf_pc[3:0], flags,
i_wb_err, pf_pc[2:0], flags,
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
op_ce, alu_ce, mem_ce,
//

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