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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/rtl
    from Rev 140 to Rev 144
    Reverse comparison

Rev 140 → Rev 144

/peripherals/ziptimer.v
67,7 → 67,7
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_int);
parameter BW = 32, VW = (BW-1);
parameter BW = 32, VW = (BW-1), RELOADABLE=1;
input i_clk, i_rst, i_ce;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
79,34 → 79,49
// Interrupt line
output reg o_int;
 
reg r_auto_reload, r_running;
reg [(VW-1):0] r_reload_value;
reg r_running;
 
wire wb_write;
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
 
wire auto_reload;
wire [(VW-1):0] reload_value;
 
initial r_running = 1'b0;
initial r_auto_reload = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_running <= 1'b0;
else if (wb_write)
r_running <= (|i_wb_data[(VW-1):0]);
else if ((o_int)&&(~r_auto_reload))
else if ((o_int)&&(~auto_reload))
r_running <= 1'b0;
 
generate
if (RELOADABLE != 0)
begin
reg r_auto_reload;
reg [(VW-1):0] r_reload_value;
 
always @(posedge i_clk)
if (wb_write)
r_auto_reload <= (i_wb_data[(BW-1)]);
initial r_auto_reload = 1'b0;
 
// If setting auto-reload mode, and the value to other
// than zero, set the auto-reload value
always @(posedge i_clk)
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
r_reload_value <= i_wb_data[(VW-1):0];
always @(posedge i_clk)
if (wb_write)
r_auto_reload <= (i_wb_data[(BW-1)]);
 
assign auto_reload = r_auto_reload;
 
// If setting auto-reload mode, and the value to other
// than zero, set the auto-reload value
always @(posedge i_clk)
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
r_reload_value <= i_wb_data[(VW-1):0];
assign reload_value = r_reload_value;
end else begin
assign auto_reload = 1'b0;
assign reload_value = 0;
end endgenerate
 
 
reg [(VW-1):0] r_value;
initial r_value = 0;
always @(posedge i_clk)
114,13 → 129,16
r_value <= i_wb_data[(VW-1):0];
else if ((r_running)&&(i_ce)&&(~o_int))
r_value <= r_value + {(VW){1'b1}}; // r_value - 1;
else if ((r_running)&&(r_auto_reload)&&(o_int))
r_value <= r_reload_value;
else if ((r_running)&&(auto_reload)&&(o_int))
r_value <= reload_value;
 
// Set the interrupt on our last tick.
// Set the interrupt on our last tick, as we transition from one to
// zero.
initial o_int = 1'b0;
always @(posedge i_clk)
if (i_ce)
if (i_rst)
o_int <= 1'b0;
else if (i_ce)
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
else
o_int <= 1'b0;
130,6 → 148,11
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
assign o_wb_stall = 1'b0;
 
assign o_wb_data = { r_auto_reload, r_value };
generate
if (VW < BW-1)
assign o_wb_data = { auto_reload, {(BW-1-VW){1'b0}}, r_value };
else
assign o_wb_data = { auto_reload, r_value };
endgenerate
 
endmodule

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