URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl
- from Rev 30 to Rev 34
- ↔ Reverse comparison
Rev 30 → Rev 34
/core/zipcpu.v
270,7 → 270,7
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
assign dcd_ce = (pf_valid)&&(~dcd_stalled); |
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline); |
assign dcd_stalled = (dcdvalid)&&( |
(op_stall) |
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall)) |
764,6 → 764,9
break_en <= 1'b0; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
break_en <= wr_reg_vl[`CPU_BREAK_BIT]; |
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG })) |
break_en <= i_dbg_data[`CPU_BREAK_BIT]; |
assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy); |
|
|
886,7 → 889,7
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_reg_vl; |
else if ((i_halt)&&(i_dbg_we) |
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG})) |
&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG})) |
pf_pc <= i_dbg_data; |
else if (dcd_ce) |
pf_pc <= pf_pc + 1; |
902,7 → 905,7
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else if ((i_halt)&&(i_dbg_we) |
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG})) |
&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG})) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
/zipsystem.v
134,7 → 134,8
// Wishbone slave interface for debugging purposes |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data); |
parameter RESET_ADDRESS=32'h0100000; |
parameter RESET_ADDRESS=32'h0100000, START_HALTED=1, |
EXTERNAL_INTERRUPTS=1; |
input i_clk, i_rst; |
// Wishbone master |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
143,7 → 144,7
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
// Incoming interrupts |
input i_ext_int; |
input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int; |
// Outgoing interrupt |
output wire o_ext_int; |
// Wishbone slave |
211,7 → 212,7
initial cmd_halt = 1'b1; |
always @(posedge i_clk) |
if (i_rst) |
cmd_halt <= 1'b1; |
cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0; |
else if (dbg_cmd_write) |
cmd_halt <= dbg_idata[10]; |
else if ((cmd_step)||(cpu_break)) |
234,16 → 235,16
cmd_addr <= dbg_idata[5:0]; |
|
wire cpu_reset; |
assign cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset); |
assign cpu_reset = (cmd_reset)||(wdt_reset); |
|
wire cpu_halt, cpu_dbg_stall; |
assign cpu_halt = (cmd_halt)&&(~cmd_step); |
assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step)); |
wire [31:0] pic_data; |
wire [31:0] cmd_data; |
// Values: |
// 0x0003f -> cmd_addr mask |
// 0x00040 -> reset |
// 0x00080 -> interrrupts enabled |
// 0x00080 -> PIC interrrupts enabled |
// 0x00100 -> cmd_step |
// 0x00200 -> cmd_stall |
// 0x00400 -> cmd_halt |
251,7 → 252,8
// 0x01000 -> cc.sleep |
// 0x02000 -> cc.gie |
// 0x10000 -> External interrupt line is high |
assign cmd_data = { 15'h00, i_ext_int, 2'b00, cpu_dbg_cc, |
assign cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int, |
2'b00, cpu_dbg_cc, |
1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0, |
pic_data[15], cpu_reset, cmd_addr }; |
|
454,10 → 456,10
// The programmable interrupt controller peripheral |
// |
wire pic_interrupt; |
wire [6:0] int_vector; |
wire [(5+EXTERNAL_INTERRUPTS):0] int_vector; |
assign int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int, |
jif_int, cache_int }; |
icontrol #(7) pic(i_clk, cpu_reset, |
icontrol #(6+EXTERNAL_INTERRUPTS) pic(i_clk, cpu_reset, |
(sys_cyc)&&(sys_stb)&&(sys_we) |
&&(sys_addr==`INTCTRL), |
sys_data, pic_data, |
/aux/busdelay.v
90,6 → 90,6
// Our only non-delayed line, yet still really delayed. Perhaps |
// there's a way to register this? |
// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such? |
assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(~o_dly_stb)); |
assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb)); |
|
endmodule |