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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/rtl
    from Rev 84 to Rev 88
    Reverse comparison

Rev 84 → Rev 88

/core/div.v
57,28 → 57,27
if (i_rst)
begin
o_busy <= 1'b0;
o_valid <= 1'b0;
end else if (i_wr)
begin
o_busy <= 1'b1;
end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
o_busy <= 1'b0;
// else busy is zero and stays at zero
 
always @(posedge i_clk)
if ((i_rst)||(i_wr))
o_valid <= 1'b0;
end else if (o_busy)
else if (o_busy)
begin
if ((r_bit == 6'h0)||(o_err))
begin
o_busy <= 1'b0;
o_valid <= (o_err)||(~r_sign);
end
end else if (r_sign)
begin
// if (o_err), o_valid is already one.
// if not, o_valid has not yet become one.
o_valid <= (~o_err); // 1'b1;
// r_sign <= 1'b0;
end else begin
o_busy <= 1'b0;
end else
o_valid <= 1'b0;
end
 
always @(posedge i_clk)
if((i_rst)||(o_valid))
/core/pfcache.v
143,7 → 143,7
if (o_wb_cyc)
delay <= 2'h2;
else if (delay != 0)
delay <= delay - 1;
delay <= delay + 2'b11; // i.e. delay -= 1;
end
 
assign o_v = (r_v)&&(~i_new_pc);
/peripherals/wbdmac.v
269,7 → 269,9
2'b00: begin
cfg_wp <= (i_swb_data[27:16]!=12'hfed);
cfg_blocklen_sub_one
<= i_swb_data[(LGMEMLEN-1):0]-1;
<= i_swb_data[(LGMEMLEN-1):0]
+ {(LGMEMLEN){1'b1}};
// i.e. -1;
cfg_dev_trigger <= i_swb_data[14:10];
cfg_on_dev_trigger <= i_swb_data[15];
cfg_incs <= ~i_swb_data[29];

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