OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/sw
    from Rev 60 to Rev 69
    Reverse comparison

Rev 60 → Rev 69

/zipdbg/zipdbg.cpp
19,7 → 19,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Tecnhology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
/zipdbg/regdefs.h
14,7 → 14,7
//
//
// Creator: Dan Gisselquist
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
/zipdbg/devbus.h
11,7 → 11,7
// to be accomplished.
//
// Creator: Dan Gisselquist
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
/lib/mpy32u.S
8,7 → 8,7
; multiply..
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
; Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
33,19 → 33,21
;
;
mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1, R2 = rtn addr (on stack)
SUB 2,SP
SUB 3,SP
STO R2,(SP)
STO R3,1(SP)
STO R4,2(SP)
;
MOV R0,R2
MULU R1,R2 ; R2 = Low order bits, low(R0) * low(R1)
MPYU R1,R2 ; R2 = Low order bits, low(R0) * low(R1)
MOV R0,R3
LSR 16,R3 ; Put high order bits in lower half of R3
MULU R1,R3 ; R3 = Mid order bits, high(R0) * low(R1)
MPYU R1,R3 ; R3 = Mid order bits, high(R0) * low(R1)
LSR 16,R1 ; R1 = High order bits of R1, being done w/ low order
MOV R1,R4 ;
MUL R0,R4 ; R4 = Mid order bits, low(R0) * high(R1)
MPYU R0,R4 ; R4 = Mid order bits, low(R0) * high(R1)
LSR 16,R0
MULU R1,R0 ; R0 = High order bits, high(R0) * high(R1)
MPYU R1,R0 ; R0 = High order bits, high(R0) * high(R1)
ADD R3,R4 ; R4 = sum of mid order bits
ADD.C 0x010000,R0 ; Add in the carry (if it happened)
MOV R4,R3
55,9 → 57,10
ADD R4,R2 ; R2 = low order bits plus low order mid-bits
ADD.C 1,R0 ; Add in the carry to R0 (if it happened)
MOV R2,R1 ; Place low order bits into R1
;
;
LOD (SP),R2
LOD 1(SP),R3
LOD 2(SP),R4
LOD 3(SP),R2
ADD 2,SP
ADD 3,SP
JMP R2
 
/lib/divs.S
14,9 → 14,9
;
;
;
divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1
lib_divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1
SUB 2,SP
; (stall)
STO R2,(SP)
STO R3,2(SP)
;
CLR R3 ; Keep track of resulting sign in R2
29,8 → 29,7
XOR.LT 1,R3 ; If so, result will be opposite sign of before
NEG.LT R1 ; Now we get R1=ABS(R1)
MOV.LT divu_divs_return(PC),R2
STO R2,1(SP)
BRA divu ; Do our unsigned multiply
BRA lib_divu ; Do our unsigned multiply
; JSR divu ; Do our unsigned multiply
divu_divs_return:
TST 1,R3 ; Check resulting sign
38,8 → 37,8
TST 2,R3 ; Now, if R1 was originally negative
NEG.NE R1 ; Then negate R1
ret_div32s:
LOD (SP),R2
LOD 2(SP),R3
LOD 3(SP),R2
ADD 2,SP
JMP R2
 
/lib/divu.S
8,7 → 8,7
; This routine is also called by the signed divide.
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
; Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
32,13 → 32,14
;
;
;
divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
lib_divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
TST -1,R1
; BNZ divu_valid_divide
CLR.Z R0 ; Should be a divide by zero error / trap
RETN.Z
JMP.Z R2
divu_valid_divide:
SUB 1,SP
SUB 2,SP
STO R2,(SP)
STO R3,1(SP)
;
LDI 1,R2 ; Here's where we record the bit we are working on
122,8 → 123,8
divu_record_result:
MOV R0,R1
MOV R3,R0
LOD (SP),R2
LOD 1(SP),R3
LOD 2(SP),R2
ADD 1,SP
ADD 2,SP
JMP R2
 
/lib/mpy32s.S
9,7 → 9,7
; unsigned multiply.
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
; Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
41,22 → 41,22
; R3 - used as scratch internally
mpy32s:
ADD 2,SP
STO R2,(SP)
STO R3,2(SP)
;
CLR R3 ; Keep track of resulting sign in R2
TST R0 ; Is R0 negative?
XOR.LT #1,R3 ; If so, resulting sign will be negative, and
TST -1,R0 ; Is R0 negative?
XOR.LT 1,R3 ; If so, resulting sign will be negative, and
NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0))
TST R1 ; Is R1 negative?
XOR.LT #1,R3 ; If so, result will be opposite sign of before
TST -1,R1 ; Is R1 negative?
XOR.LT 1,R3 ; If so, result will be opposite sign of before
NEG.LT R1 ; Now we get R1=ABS(R1)
 
; JSR mpy32u
MOV __HERE__+2,R2 ; Do our unsigned multiply
STO R2,1(SP)
MOV __HERE__+2(PC),R2 ; Do our unsigned multiply
BRA mpy32u
;
TST 0,R3 ; Check resulting sign
TST -1,R3 ; Check resulting sign
BZ ret_mul32s ; If positive, do nothing more
NOT R0 ; If negative, negate the result
NOT R1
63,8 → 63,8
ADD $1,R1
ADD.C $1,R0
ret_mul32s:
LOD (SP),R2
LOD 2(SP),R3
LOD 3(SP),R2
ADD 2,SP
JMP R2
 
/zasm/test.S
26,7 → 26,7
;
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
; Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
88,6 → 88,7
#define MEM_PIPELINE_TEST
#define CONDITIONAL_EXECUTION_TEST
#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
#define BCMEM_TEST // Do memory and conditions work well together?
test:
#ifdef DO_TEST_ASSEMBLER
; We start out by testing our assembler. We give it some instructions, which
273,8 → 274,9
traptest_supervisor:
mov traptest_user(pc),upc
rtu
mov cc,r0
mov ucc,r0
tst sys.cctrap,r0
tst.nz sys.gie,r0
bz test_failure
#endif
 
288,7 → 290,7
sto r0,(r12)
rtu
mov ucc,r0
cmp sys.cctrap,r0
CMP sys.cctrap+sys.gie,r0
bnz test_failure
halt
// Go into an infinite loop if the trap fails
529,6 → 531,19
ldi 0x40000000,r1
cmp r0,r1
trap.ne r11
//
// And from our eyeball test ...
LDI 0x01ff01ff,R0
MOV R0,R7
MOV 8(SP),R6
LSR 7,R0
AND 7,R0
LDI 7,R1
SUB R0,R1
MOV R1,R0
MPYU 5,R0
CMP 20,R0
TRAP.NE R11
#endif
 
#ifdef PUSH_TEST
536,7 → 551,7
ldi 0x01248cab,r0
ldi 0xd5312480,r1 // Let's see if we can preserve this as well
mov r1,r7
JSR(reverse_bit_order,R4); // *SP = 0x010013d
FJSR(reverse_bit_order,R4); // *SP = 0x010013d
cmp r0,r1
trap.ne r11
cmp r0,r7
552,7 → 567,7
MOV 1(R3),R4
MOV 1(R4),R5
MOV 1(R5),R6
JSR(pipeline_stack_test,R7)
FJSR(pipeline_stack_test,R7)
CMP 1,R0
trap.ne R11
CMP 2,R1
570,17 → 585,49
#endif
 
#ifdef MEM_PIPELINE_TEST
JSR(mem_pipeline_test,R0)
LDI 0x10000,R11
FJSR(mem_pipeline_test,R0)
#endif // MEM_PIPELINE_TEST
 
#ifdef CONDITIONAL_EXECUTION_TEST
JSR(conditional_execution_test,R0)
LDI 0x11000,R11
FJSR(conditional_execution_test,R0)
#endif // CONDITIONAL_EXECUTION_TEST
 
#ifdef NOWAIT_PIPELINE_TEST
JSR(nowait_pipeline_test,R0)
LDI 0x12000,R11
FJSR(nowait_pipeline_test,R0)
#endif // NOWAIT_PIPELINE_TEST
 
#ifdef BCMEM_TEST
LDI 0x13000,R11
CLR R0
LDI -1,R1
STO R0,bcmemtestloc(PC)
LOD bcmemtestloc(PC),R1
CMP R0,R1
TRAP.NZ R11
CMP 0x13000,R11
BZ bcmemtest_cmploc_1
STO R11,bcmemtestloc(PC)
bcmemtest_cmploc_1:
LOD bcmemtestloc(PC),R0
CMP R0,R11
TRAP.Z R11
CLR R0
CMP R0,R11
BZ bcmemtest_cmploc_2
STO.NZ R11,bcmemtestloc(PC)
bcmemtest_cmploc_2:
NOOP
LOD bcmemtestloc(PC),R0
CMP R0,R11
TRAP.NZ R11
BRA end_bcmemtest
bcmemtestloc:
WORD 0
end_bcmemtest:
#endif
// Return success / Test the trap interrupt
clr r11
trap r11
595,8 → 642,10
// Now, let's test whether or not we can handle a subroutine
#ifdef PUSH_TEST
reverse_bit_order:
PUSH(R1,SP) ; R1 will be our loop counter
PUSH(R2,SP) ; R2 will be our accumulator and eventual result
SUB 3,SP
STO R1,(SP) ; R1 will be our loop counter
STO R2,1(SP) ; R2 will be our accumulator and eventual result
STO R4,2(SP)
LDI 32,R1
CLR R2
reverse_bit_order_loop:
606,9 → 655,11
SUB 1,R1
BNZ reverse_bit_order_loop
MOV R2,R0
POP(R2,SP)
POP(R1,SP)
RET
LOD (SP),R1
LOD 1(SP),R2
LOD 2(SP),R4
ADD 3,SP
JMP R4
#endif
 
; The pipeline stack test examines whether or not a series of memory commands
621,19 → 672,19
#ifdef PIPELINE_STACK_TEST
pipeline_stack_test:
SUB 13,SP
STO R0,1(SP)
STO R1,2(SP)
STO R2,3(SP)
STO R3,4(SP)
STO R4,5(SP)
STO R5,6(SP)
STO R6,7(SP)
STO R7,8(SP)
STO R8,9(SP)
STO R9,10(SP)
STO R10,11(SP)
STO R11,12(SP)
STO R12,13(SP)
STO R0,(SP)
STO R1,1(SP)
STO R2,2(SP)
STO R3,3(SP)
STO R4,4(SP)
STO R5,5(SP)
STO R6,6(SP)
STO R7,7(SP)
STO R8,8(SP)
STO R9,9(SP)
STO R10,10(SP)
STO R11,11(SP)
STO R12,12(SP)
XOR -1,R0
XOR -1,R1
XOR -1,R2
647,35 → 698,35
XOR -1,R10
XOR -1,R11
XOR -1,R12
LOD 1(SP),R0
LOD 2(SP),R1
LOD 3(SP),R2
LOD 4(SP),R3
LOD 5(SP),R4
LOD 6(SP),R5
LOD 7(SP),R6
LOD 8(SP),R7
LOD 9(SP),R8
LOD 10(SP),R9
LOD 11(SP),R10
LOD 12(SP),R11
LOD 13(SP),R12
LOD (SP),R0
LOD 1(SP),R1
LOD 2(SP),R2
LOD 3(SP),R3
LOD 4(SP),R4
LOD 5(SP),R5
LOD 6(SP),R6
LOD 7(SP),R7
LOD 8(SP),R8
LOD 9(SP),R9
LOD 10(SP),R10
LOD 11(SP),R11
LOD 12(SP),R12
ADD 13,SP
LOD 1(SP),PC
JMP R7
#endif // PIPELINE_STACK_TEST
 
#ifdef MEM_PIPELINE_TEST
mem_pipeline_test:
SUB 4,SP
STO R0,1(SP)
STO R1,2(SP)
STO R0,(SP)
STO R1,1(SP)
LDI 0x10000,R11
;
; Test #1 ... Let's start by writing a value to memory
LDI -1,R0
CLR R1
STO R0,3(SP)
LOD 3(SP),R1
STO R0,2(SP)
LOD 2(SP),R1
CMP R1,R0
MOV.NZ R11,CC
 
684,31 → 735,30
NOP
CLR R0
CLR R1
LOD 3(SP),R0 ; This should load back up our -1 value
STO R0,4(SP)
LOD 2(SP),R0 ; This should load back up our -1 value
STO R0,3(SP)
; Insist that the pipeline clear
LOD 3(SP),R0
LOD 2(SP),R0
; Now let's try loading into R1
NOP
NOP
NOP
NOP
LOD 4(SP),R1
LOD 3(SP),R1
CMP R1,R0
MOV.NZ R11,CC
LOD 1(SP),R0
LOD 2(SP),R1
LOD (SP),R0
LOD 1(SP),R1
ADD 4,SP
RETN
JMP R0
#endif
 
#ifdef CONDITIONAL_EXECUTION_TEST
conditional_execution_test:
; R0 is corrupt on entry, no need to save it
; SUB 1,SP
; STO R0,1(SP)
 
SUB 1,SP
STO R0,(SP)
;
CLRF R0
ADD.Z 1,R0
TRAP.NZ R11
715,10 → 765,9
CMP.Z 0,R0
TRAP.Z R11
 
; LOD 1(SP),R0
; ADD 1,SP
; ; Stall
RETN
LOD (SP),R0
ADD 1,SP
JMP R0
#endif
 
;
734,11 → 783,11
SUB 6,SP
; Leave a spot open on the stack for a local variable,
; kept in memory.
STO R0,2(SP)
STO R1,3(SP)
STO R2,4(SP)
STO R3,5(SP)
STO R4,6(SP)
STO R0,(SP)
STO R1,1(SP)
STO R2,2(SP)
STO R3,3(SP)
STO R4,4(SP)
;
; Let's start with ALU-ALU testing
; AA: result->input A
785,16 → 834,16
; Then we need to do ALU-Mem input testing
;
CLR R0
STO R0,1(SP)
STO R0,5(SP)
LDI 8352,R0
LOD 1(SP),R0
LOD 5(SP),R0
TST -1,R0
TRAP.NZ R11
 
LDI 937,R0 ; Let's try again, this time something that's
STO R0,1(SP) ; not zero
STO R0,5(SP) ; not zero
NOOP
LOD 1(SP),R0
LOD 5(SP),R0
CMP 938,R0 ; Let's not compare with self, let's that
TRAP.GE R11 ; masks a problem--compare with a different
CMP 936,R0 ; number instead.
805,21 → 854,22
; Mem output->MEM input testing
;
LDI 5328,R2
LOD 1(SP),R2
STO R2,1(SP)
LOD 1(SP),R1
LOD 5(SP),R2
STO R2,5(SP)
LOD 5(SP),R1
CMP 937,R1
TRAP.NZ R11
;
LOD 2(SP),R0
LOD 3(SP),R1
LOD 4(SP),R2
LOD 5(SP),R3
LOD 6(SP),R4
LOD (SP),R0
LOD 1(SP),R1
LOD 2(SP),R2
LOD 3(SP),R3
LOD 4(SP),R4
ADD 6,SP
RETN
JMP R0
#endif // NOWAIT_PIPELINE_TEST
 
 
fill 512,0
stack: // Must point to a valid word initially
word 0
/zasm/zdump.cpp
7,7 → 7,7
// Purpose: Disassemble machine code files onto the stdout file.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/zasm/zasm.y
8,7 → 8,7
** the parser, but the main program as well.
**
** Creator: Dan Gisselquist, Ph.D.
** Gisselquist Tecnology, LLC
** Gisselquist Technology, LLC
**
********************************************************************************
**
/zasm/asmdata.cpp
9,7 → 9,7
// of the code for actually building such structures.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
224,19 → 224,19
if (m_opa == zp.ZIP_Rnone) \
yyerror("Err: Dual Ops need a result register"); \
if (m_opb != zp.ZIP_Rnone) { \
if(!fitsin(imm, 16)) \
yyerror("16-bit: Immediate out of range"); \
if(!fitsin(imm, 14)) \
yyerror("14-bit: Immediate out of range"); \
in = zp.OP(m_cond,imm,m_opb,m_opa); \
} else { \
if(!fitsin(imm, 20)) \
yyerror("20-bit: Immediate out of range"); \
if(!fitsin(imm, 18)) \
yyerror("18-bit: Immediate out of range"); \
in = zp.OP(m_cond,imm,m_opa); \
}
 
#define BLD_BRANCH(OP,CND) \
if (fitsin(offset, 16)) \
if (fitsin(offset, 13)) \
in = zp.OP(offset); \
else if (fitsin(offset, 20)) \
else if (fitsin(offset, 18)) \
in = zp.op_add(zp.CND, offset, zp.ZIP_PC); \
else { in = zp.OP(offset); yyerror("LONG JUMP NOT SUPPORTED"); }
 
272,7 → 272,7
yyerror("Moves can only occurr between registers");
fprintf(stderr, "m_opa = %d, m_opb = %d\n", m_opa, m_opb);
fprintf(stderr, "m_imm = %d\n", imm);
} else if (!fitsin(imm, 16))
} else if (!fitsin(imm, 13))
yyerror("Immediate overflow on move");
in = zp.op_mov(m_cond, imm, m_opb, m_opa);
break;
358,8 → 358,14
else
in = zp.op_sto(m_cond, m_opa, imm);
break;
case OP_BREV:
BLD_DUALOP(op_brev);
break;
case OP_POPC:
BLD_DUALOP(op_popc);
break;
case OP_LDI:
if ((!fitsin(imm, 24))||(m_cond != zp.ZIPC_ALWAYS)) {
if ((!fitsin(imm, 23))||(m_cond != zp.ZIPC_ALWAYS)) {
if (m_opa == zp.ZIP_PC)
yyerror("Cannot LDI 32-bit addresses into PC register!");
LLINE *lln = new LLINE;
370,6 → 376,12
} else
in = zp.op_ldi(imm, m_opa);
break;
case OP_DIVU:
BLD_DUALOP(op_divu);
break;
case OP_DIVS:
BLD_DUALOP(op_divs);
break;
case OP_CLRF:
in = zp.op_clrf(m_cond, m_opb);
break;
392,13 → 404,13
if (m_opb == zp.ZIP_Rnone) {
if (m_cond != zp.ZIPC_ALWAYS)
yyerror("JMP: Conditions are not allowed for absolute jumps.");
imm &= (1<<24)-1;
if (!fitsin(imm, 24))
imm &= (1<<23)-1;
if (!fitsin(imm, 23))
yyerror("JMP: Absolute jump address out of range");
in = zp.op_ldi(imm, zp.ZIP_PC);
} else if (fitsin(imm,16)) {
} else if (fitsin(imm,13)) {
in = zp.op_mov(m_cond, imm, m_opb, zp.ZIP_PC);
} else if (fitsin(imm,20))
} else if (fitsin(imm,18))
in = zp.op_add(m_cond, imm, m_opb, zp.ZIP_PC);
else
yyerror("JMP: Immediate out of range");
438,7 → 450,7
in = zp.op_ldi(imm, zp.ZIP_CC);
else if((m_opb == zp.ZIP_Rnone)&&((imm&0x0ffdf)==imm))
in = zp.op_ldilo(m_cond, imm & 0x0ffdf, zp.ZIP_CC);
else if((m_opb != zp.ZIP_Rnone)&&(fitsin(imm, 16)))
else if((m_opb != zp.ZIP_Rnone)&&(fitsin(imm, 13)))
in = zp.op_mov(m_cond, imm, m_opb, zp.ZIP_CC);
else {
yyerror("Illegal trap!");
445,12 → 457,16
in = zp.op_trap(m_cond, 0);
}
break;
case OP_RETN: in = zp.op_retn(m_cond); break;
case OP_RETN: // yywarn("RETN opcode is deprecated");
in = zp.op_lod(m_cond, imm, m_opb, m_opa);
in = zp.op_lod(m_cond, -1, zp.ZIP_SP, zp.ZIP_PC);
break;
case OP_HALT: in = zp.op_halt(m_cond); break;
case OP_RTU: in = zp.op_rtu(m_cond); break;
case OP_BUSY: in = zp.op_busy(m_cond); break;
case OP_NOOP: in = zp.op_noop(); break;
case OP_BREAK: in = zp.op_break(); break;
case OP_NOOP: in = zp.op_noop(); break;
case OP_LOCK: in = zp.op_lock(); break;
// OP_LJMP:
case OP_NONE:
default: { char ebuf[256]; sprintf(ebuf, "Unrecognized OP-Code, %d, NONE = %d, CLR=%d", m_opcode, OP_NONE, OP_CLR);
465,7 → 481,7
int TLINE::nlines(void) {
if ((m_opcode == OP_LDI)&&( (!(m_imm->isdefined()))
|| (m_cond != ZPARSER::ZIPC_ALWAYS)
|| (!fitsin(m_imm->eval(), 24)) )) {
|| (!fitsin(m_imm->eval(), 23)) )) {
return 2;
}
return 1;
560,6 → 576,7
case OP_BREAK: fprintf(fp, "\tTLINE OP = BREAK\n");
break;
case OP_NOOP: fprintf(fp, "\tTLINE OP = NOOP\n");
case OP_LOCK: fprintf(fp, "\tTLINE OP = LOCK\n");
break;
// OP_LJMP:
case OP_NONE:
/zasm/twoc.cpp
10,7 → 10,7
// are properly sign extended (or not) as desired.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/zasm/optest.cpp
10,7 → 10,7
// code isn't nearly as useful anymore.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/zasm/asmdata.h
13,7 → 13,7
// part of the assembler and not part of a separate linker.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
57,6 → 57,12
OP_CMP, OP_TST, OP_MOV, OP_LDIHI, OP_LDILO, OP_MPYU, OP_MPYS, OP_ROL,
OP_SUB, OP_AND, OP_ADD, OP_OR, OP_XOR,
OP_LSL, OP_ASR, OP_LSR,
// New bit-wise operations
OP_BREV, OP_POPC,
// New divide instruction
OP_DIVU, OP_DIVS,
// New floating point instructions
OP_FPADD, OP_FPSUB, OP_FPMUL, OP_FPDIV, OP_FPCVT, OP_FPINT,
// Memory operands/operators
OP_LOD, OP_STO,
// Dual operand instructions that do not take conditions
64,18 → 70,18
// Single operand instructions that can take conditions
OP_CLRF, OP_JMP, OP_LJMP, OP_NOT,
// Branch operands
OP_BRA, OP_BZ, OP_BNZ, OP_BGE, OP_BGT, OP_BLT, OP_BRC, OP_BRV,
OP_BRA, OP_BLT, OP_BZ, OP_BNZ, OP_BGT, OP_BGE, OP_BRC, OP_BRV,
// Single operand instructions that have no explicit conditions
OP_CLR, OP_TRAP, OP_NEG,
// BAREOPs that can have conditions
OP_HALT, OP_RTU, OP_BUSY, OP_RETN,
// BAREOPs without conditions
OP_BREAK, OP_NOOP,
OP_BREAK, OP_NOOP, OP_LOCK,
// Error condition--undefined operand
OP_NONE
} LEXOPCODE;
 
#define DEFAULT_LINE 0x4e000000
#define DEFAULT_LINE 0x76000000
 
class ASMLINE {
public:
/zasm/twoc.h
10,7 → 10,7
// are properly sign extended (or not) as desired.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
/zasm/zpp.l
13,7 → 13,7
** supposed to be supported, but the support isn't there yet.
**
** Creator: Dan Gisselquist, Ph.D.
** Gisselquist Tecnology, LLC
** Gisselquist Technology, LLC
**
********************************************************************************
**
133,6 → 133,8
free(dup);
yyless(strchr(yytext,'(')-yytext);
}
} else if (!stb_current(yytext)) {
stb_macro(yytext);
} else {
char *dup = strdup(yytext), *ptr;
ptr = strchr(dup, '(');
261,6 → 263,7
fprintf(yyout, "%s", yytext);
}
}
<INITIAL,INDEF>"\'"(("\\\'")|([^'\\])|("\\"[0abfnrtv])|("\\\\")|("\\\"")){1,4}"\'" { ECHO; }
<*>[ \t]*"//".*$ { /* Ignore (trailing) comment only lines */ }
<*>[ \t]*";".*$ { /* Ignore (trailing) comment only lines */ }
<*>"#warning".*$ { fprintf(stderr, "WARNING: %s\n", &yytext[8]); }
/zasm/zasm.l
9,7 → 9,7
**
**
** Creator: Dan Gisselquist, Ph.D.
** Gisselquist Tecnology, LLC
** Gisselquist Technology, LLC
**
********************************************************************************
**
141,21 → 141,31
(?i:break) { yylval.u_op = OP_BREAK; return BAREOP; }
(?i:brk) { yylval.u_op = OP_BREAK; return BAREOP; }
(?i:busy) { yylval.u_op = OP_BUSY; return BAREOP; }
(?i:brev) { yylval.u_op = OP_BREV; return DUALOP; }
(?i:popc) { yylval.u_op = OP_POPC; return DUALOP; }
(?i:divu) { yylval.u_op = OP_DIVU; return DUALOP; }
(?i:divs) { yylval.u_op = OP_DIVS; return DUALOP; }
(?i:fpadd) { yylval.u_op = OP_FPADD; return DUALOP; }
(?i:fpsub) { yylval.u_op = OP_FPSUB; return DUALOP; }
(?i:fpmul) { yylval.u_op = OP_FPMUL; return DUALOP; }
(?i:fpdiv) { yylval.u_op = OP_FPDIV; return DUALOP; }
(?i:fpcvt) { yylval.u_op = OP_FPCVT; return DUALOP; }
(?i:fpint) { yylval.u_op = OP_FPINT; return DUALOP; }
(?i:equ) { return EQU; }
(?i:fill) { return FILL; }
(?i:word) { return WORD; }
"__"[hH][eE][rR][eE]"__" { return HERE; }
[\.][dD][aA][tT] { return WORD; }
[\.][zZ]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_Z; return COND; }
[\.][nN][eE]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_NZ; return COND; }
[\.][nN][zZ]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_NZ; return COND; }
[\.][gG][eE]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_GE; return COND; }
[\.][gG][tT]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_GT; return COND; }
[\.][lL][tT]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_LT; return COND; }
[\.][nN]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_LT; return COND; }
[\.][cC]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_C; return COND; }
[\.][vV]/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_V; return COND; }
[_A-Za-z][_a-zA-Z0-9]* { yylval.u_id = strdup(yytext); return IDENTIFIER; }
[\.](?i:z)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_Z; return COND; }
[\.](?i:ne)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_NZ; return COND; }
[\.](?i:nz)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_NZ; return COND; }
[\.](?i:ge)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_GE; return COND; }
[\.](?i:gt)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_GT; return COND; }
[\.](?i:lt)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_LT; return COND; }
[\.](?i:n)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_LT; return COND; }
[\.](?i:c)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_C; return COND; }
[\.](?i:v)/[ \t\n] { yylval.u_cond = ZPARSER::ZIPC_V; return COND; }
[_A-Za-z][_a-zA-Z0-9]* { yylval.u_id = strdup(yytext); return IDENTIFIER; }
"$"?[-]?0[xX][0-9A-Fa-f]+ { yylval.u_ival = strtoul(yytext+(((*yytext)=='$')?1:0),NULL,16);return INT;}
"$"?[-]?0[0-7]+ { yylval.u_ival = strtoul(yytext+(((*yytext)=='$')?1:0),NULL, 8);return INT;}
"$"?[-]?[1-9][0-9]* { yylval.u_ival = strtoul(yytext+(((*yytext)=='$')?1:0),NULL,10);return INT;}
/zasm/sys.i
13,7 → 13,7
; macros (yet).
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
; Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
120,71 → 120,72
STO RG,1(SP) \
BRA LBL \
ADD 1,SP
 
#define RET LOD 1(SP),PC
#define SAVE_USER_CONTEXT(DR,AR) \
#define SAVE_USER_CONTEXT(DA,DB,DC,DD,AR) \
MOV -15(uSP),AR \
MOV uPC,DR \
STO DR,15(AR) \
MOV uCC,DR \
STO DR,14(AR) \
MOV uR12,DR \
STO DR,13(AR) \
MOV uR11,DR \
STO DR,12(AR) \
MOV uR10,DR \
STO DR,11(AR) \
MOV uR9,DR \
STO DR,10(AR) \
MOV uR8,DR \
STO DR,9(AR) \
MOV uR7,DR \
STO DR,8(AR) \
MOV uR6,DR \
STO DR,7(AR) \
MOV uR5,DR \
STO DR,6(AR) \
MOV uR4,DR \
STO DR,5(AR) \
MOV uR3,DR \
STO DR,4(AR) \
MOV uR2,DR \
STO DR,3(AR) \
MOV uR1,DR \
STO DR,2(AR) \
MOV uR0,DR \
STO DR,1(AR)
#define RESTORE_USER_CONTEXT(DR,AR) \
LOD 1(AR),DR \
MOV DR,uR0 \
LOD 2(AR),DR \
MOV DR,uR1 \
LOD 3(AR),DR \
MOV DR,uR2 \
LOD 4(AR),DR \
MOV DR,uR3 \
LOD 5(AR),DR \
MOV DR,uR4 \
LOD 6(AR),DR \
MOV DR,uR5 \
LOD 7(AR),DR \
MOV DR,uR6 \
LOD 8(AR),DR \
MOV DR,uR7 \
LOD 9(AR),DR \
MOV DR,uR8 \
LOD 10(AR),DR \
MOV DR,uR9 \
LOD 11(AR),DR \
MOV DR,uR10 \
LOD 12(AR),DR \
MOV DR,uR11 \
LOD 13(AR),DR \
MOV DR,uR12 \
LOD 14(AR),DR \
MOV DR,uCC \
LOD 15(AR),DR \
MOV DR,uPC
MOV uR0,DA \
MOV uR1,DB \
MOV uR2,DC \
MOV uR3,DD \
STO DA,(AR) \
STO DB,1(AR) \
STO DC,2(AR) \
STO DD,3(AR) \
MOV uR4,DA \
MOV uR5,DB \
MOV uR6,DC \
MOV uR7,DD \
STO DA,4(AR) \
STO DB,5(AR) \
STO DC,6(AR) \
STO DD,7(AR) \
MOV uR8,DA \
MOV uR9,DB \
MOV uR10,DC \
MOV uR11,DD \
STO DA,8(AR) \
STO DB,9(AR) \
STO DC,10(AR) \
STO DD,11(AR) \
MOV uR12,DA \
MOV uCC,DC \
MOV uPC,DD \
STO DA,12(AR) \
STO DC,13(AR) \
STO DD,14(AR)
#define RESTORE_USER_CONTEXT(DA,DB,DC,DD,AR) \
LOD (AR),DA \
LOD 1(AR),DB \
LOD 2(AR),DC \
LOD 3(AR),DD \
MOV DA,uR0 \
MOV DB,uR1 \
MOV DC,uR2 \
MOV DD,uR3 \
LOD 4(AR),DA \
LOD 5(AR),DB \
LOD 6(AR),DC \
LOD 7(AR),DD \
MOV DA,uR4 \
MOV DB,uR5 \
MOV DC,uR6 \
MOV DD,uR7 \
LOD 8(AR),DA \
LOD 9(AR),DB \
LOD 10(AR),DC \
LOD 11(AR),DD \
MOV DA,uR8 \
MOV DB,uR9 \
MOV DC,uR10 \
MOV DD,uR11 \
LOD 12(AR),DA \
LOD 13(AR),DB \
LOD 14(AR),DC \
MOV DA,uR12 \
MOV DB,uCC \
MOV DC,uPC \
MOV 15(AR),uSP
#define READ_USER_TRAP(RG) \
MOV uCC,RG \
AND -256,RG
 
/zasm/zopcodes.cpp
10,7 → 10,7
// string (disassemble) conversion.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
61,7 → 61,7
};
 
const char *zop_ccstr[] = {
"", ".Z", ".NE", ".GE", ".GT", ".LT", ".C", ".V"
"", ".LT", ".Z", ".NZ", ".GT", ".GE", ".C", ".V"
};
 
const ZOPCODE zoplist[] = {
68,112 → 68,437
// Special case instructions. These are general instructions, but with
// special opcodes
// Conditional branches
"BUSY", 0xff1fffff, 0x2f0f7fff, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"BRA", 0xffff8000, 0x2f0f0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BRZ", 0xffff8000, 0x2f2f0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BNZ", 0xffff8000, 0x2f4f0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BGE", 0xffff8000, 0x2f6f0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BGT", 0xffff8000, 0x2f8f0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BLT", 0xffff8000, 0x2faf0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BRC", 0xffff8000, 0x2fcf0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
"BRV", 0xffff8000, 0x2fef0000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(15,0), OPUNUSED,
// CLR
"CLRF", 0xff1f0000, 0xc0100000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc1110000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc2120000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc3130000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc4140000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc5150000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc6160000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc7170000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc8180000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xc9190000, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xca1a0000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xcb1b0000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xcc1c0000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xcd1d0000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xce1e0000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"CLRF", 0xff1f0000, 0xcf1f0000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
//
"CLR", 0xf0ffffff, 0x30000000, REGFIELD(24),OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
//
"HALT", 0xff10007f, 0xbe000010, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
// 0.1111.0111.ccc.0.111.10iiiii--
// 0111 1011 11cc c011 110i iiii iiii iiii
"BUSY", 0xffc7ffff, 0x7bc3dfff, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"BRA", 0xffffe000, 0x7bc3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BLT", 0xffffe000, 0x7bcbc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BRZ", 0xffffe000, 0x7bd3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BNZ", 0xffffe000, 0x7bdbc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BGE", 0xffffe000, 0x7be3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BGT", 0xffffe000, 0x7bebc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BRC", 0xffffe000, 0x7bf3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
"BRV", 0xffffe000, 0x7bfbc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// CLRF ... an XOR w/ self instruction
// 0.rrrr.00100.ccc.1.rrrr.iiiii---
// 0rrr r001 00cc c1rr rr00 0000 0000 0000
"CLRF", 0xffc7cfff, 0x01040000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x09044000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x11048000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x1904c000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x21050000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x29054000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x31058000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x3905c000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x41060000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x49064000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x51068000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x5906c000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x61070000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x69074000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x71078000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
"CLRF", 0xffc7cfff, 0x7907c000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// CLR -- a LDI of zero
// 0.rrrr.1011.iiiiiii--
// 0rrr r101 1...
"CLR", 0x878fffff, 0x05800000, REGFIELD(27),OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
// HALT
// 0.1110.00011.ccc.0.0000000000010
// 0111.0000.11cc.c000.0000.0000.0000.0010
"HALT", 0xffc7ffff, 0x70c00010, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// The "wait" instruction is identical, with the only difference being
// the interrrupt context of the processor. Hence we allow both
// instructions here.
"WAIT", 0xff10007f, 0xbe000010, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
// the interrrupt context of the processor. Well, almost. To
// facilitate waits from supervisor mode, the wait instruction
// explicitly forces the CPU into user mode.
"WAIT", 0xffc7ffff, 0x70c00030, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
//
"INT", 0xff10007f, 0x9e00005f, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
// "INT", 0xff10007f, 0x9e00005f, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// Return to user space
"RTU", 0xff10007f, 0xbe000020, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"RTU", 0xffc7ffff, 0x70c00020, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// JMP (possibly a conditional jump, if not covered by branches above)
"JMP", 0xff108000, 0x2f000000, OPUNUSED,OPUNUSED, REGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
"JMP", 0xff108000, 0x2f008000, OPUNUSED,OPUNUSED, URGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
"LJMP", 0xff100000, 0xaf000000, OPUNUSED,OPUNUSED, OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
// NOT
"NOT", 0xf01fffff, 0xc00fffff, REGFIELD(24), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
// 0.1111.01111.ccc.a.rrrr.biiiiiiiiiiiiiiii
// 0111.1011.11cc.c0rr.rrbi.iiii.iiii.iiii
"JMP", 0xffc42000, 0x7bc00000, OPUNUSED,OPUNUSED, REGFIELD(14), IMMFIELD(13,0), BITFIELD(3,19),
"JMP", 0xffc42000, 0x7bc02000, OPUNUSED,OPUNUSED, URGFIELD(14), IMMFIELD(13,0), BITFIELD(3,19),
// 0.1111.1001.ii.iiii.iiii.iiii.iiii.iiii.iiii
// 0111.1100.1iii.iiii.iiii.iiii.iiii.iiii
"JMP", 0xff800000, 0x7c800000, REGFIELD(27),OPUNUSED, OPUNUSED, IMMFIELD(23,0), OPUNUSED,
// 0.1111.00010.ccc0.iiiii.iiii.iiii.iiii.iiii
// 0111.1000.10cc.c0ii.iiii.iiii.iiii.iiii
"LJMP", 0xffc40000, 0x78800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
// 0.1111.10010.000.1.1111.000000000000000
// 0111.1100.10cc.c111.11ii.iiii.iiii.iiii
"FJMP", 0xffc7ffff, 0x7c87c000, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// NOT : XOR w/ -1
// 0.rrrr.00100.ccc.0111.11111111111
// 0rrr.r001.00cc.c011.f.f.f.f
"NOT", 0x87c7ffff, 0x0103ffff, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// General instructions
"CMP", 0xf0100000, 0x00000000, OPUNUSED, REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"CMP", 0xf0100000, 0x00100000, OPUNUSED, REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
"TST", 0xf0100000, 0x10000000, OPUNUSED, REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"TST", 0xf0100000, 0x10100000, OPUNUSED, REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
// 0rrr.rooo.oocc.cxrr.rrii.iiii.iiii.iiii
"SUB", 0x87c40000, 0x00000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"SUB", 0x87c40000, 0x00040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"AND", 0x87c40000, 0x00400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"AND", 0x87c40000, 0x00440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"ADD", 0x87c40000, 0x00800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"ADD", 0x87c40000, 0x00840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"OR", 0x87c40000, 0x00c00000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"OR", 0x87c40000, 0x00c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"XOR", 0x87c40000, 0x01000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"XOR", 0x87c40000, 0x01040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"LSR", 0x87c40000, 0x01400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"LSR", 0x87c40000, 0x01440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"LSL", 0x87c40000, 0x01800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"LSL", 0x87c40000, 0x01840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"ASR", 0x87c40000, 0x01c00000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"ASR", 0x87c40000, 0x01c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"LDIHI",0x87c40000, 0x02000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"LDIHI",0x87c40000, 0x02040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"LDILO",0x87c40000, 0x02400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"LDILO",0x87c40000, 0x02440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"MPYU", 0x87c40000, 0x02800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"MPYU", 0x87c40000, 0x02840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"MPYS", 0x87c40000, 0x02c00000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"MPYS", 0x87c40000, 0x02c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"BREV", 0x87c40000, 0x03000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"BREV", 0x87c40000, 0x03040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"POPC", 0x87c40000, 0x03400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"POPC", 0x87c40000, 0x03440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"ROL", 0x87c40000, 0x03800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"ROL", 0x87c40000, 0x03840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
// map bit = 1 (interrupts enabled) specifies user reg
"MOV", 0xf0108000, 0x20000000, REGFIELD(24),OPUNUSED, REGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
"MOV", 0xf0108000, 0x20100000, URGFIELD(24),OPUNUSED, REGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
"MOV", 0xf0108000, 0x20008000, REGFIELD(24),OPUNUSED, URGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
"MOV", 0xf0108000, 0x20108000, URGFIELD(24),OPUNUSED, URGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
// 0rrr.rooo.oocc.cxrr.rrxi.iiii.iiii.iiii
"MOV", 0x87c42000, 0x03c00000, REGFIELD(27),OPUNUSED, REGFIELD(14), IMMFIELD(13,0), BITFIELD(3,19),
"MOV", 0x87c42000, 0x03c40000, URGFIELD(27),OPUNUSED, REGFIELD(14), IMMFIELD(13,0), BITFIELD(3,19),
"MOV", 0x87c42000, 0x03c02000, REGFIELD(27),OPUNUSED, URGFIELD(14), IMMFIELD(13,0), BITFIELD(3,19),
"MOV", 0x87c42000, 0x03c42000, URGFIELD(27),OPUNUSED, URGFIELD(14), IMMFIELD(13,0), BITFIELD(3,19),
//
"LDI", 0xf0000000, 0x30000000, REGFIELD(24),OPUNUSED, OPUNUSED, IMMFIELD(24,0), OPUNUSED,
"CMP", 0x87c40000, 0x04000000, OPUNUSED, REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"CMP", 0x87c40000, 0x04040000, OPUNUSED, REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
"TST", 0x87c40000, 0x04400000, OPUNUSED, REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"TST", 0x87c40000, 0x04440000, OPUNUSED, REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
// 0rrr.r101.1
"LDI", 0x87800000, 0x05800000, REGFIELD(27),OPUNUSED, OPUNUSED, IMMFIELD(23,0), OPUNUSED,
//
"NOOP", 0xffffffff, 0x4e000000, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
"BRK", 0xffffffff, 0x4e000001, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
"NOOP", 0xffffffff, 0x76000000, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
"BRK", 0xffffffff, 0x76400000, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
"LOCK", 0xffffffff, 0x76800000, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
//
"LDILO",0xff100000, 0x4f000000, REGFIELD(16),OPUNUSED, OPUNUSED, IMMFIELD(16,0), BITFIELD(3,21),
"LDIHI",0xff100000, 0x4f100000, REGFIELD(16),OPUNUSED, OPUNUSED, IMMFIELD(16,0), BITFIELD(3,21),
//
"MPYU", 0xf01f0000, 0x400f0000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(15,0), BITFIELD(3,21),
"MPYU", 0xf0100000, 0x40000000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
"MPYS", 0xf01f0000, 0x401f0000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(15,0), BITFIELD(3,21),
"MPYS", 0xf0100000, 0x40100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(15,0), BITFIELD(3,21),
// LOD: 0rrr.r100.10cc.cxrr.rrii.iiii.iiii.iiii
"LOD", 0x87c40000, 0x04800000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"LOD", 0x87c40000, 0x04840000, REGFIELD(27), OPUNUSED, REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"ROL", 0xf0100000, 0x50000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(5,0), BITFIELD(3,21),
"ROL", 0xf0100000, 0x50100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(5,0), BITFIELD(3,21),
"STO", 0x87c40000, 0x04c00000, OPUNUSED, REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"STO", 0x87c40000, 0x04c40000, OPUNUSED, REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"RETN", 0xff1fffff, 0x6f1d0001, OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,21),
"LOD", 0xf0100000, 0x60000000, REGFIELD(24), OPUNUSED, OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"LOD", 0xf0100000, 0x60100000, REGFIELD(24), OPUNUSED, REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
// 0rrr.r101.1dcc.cxrr.rrii.iiii.iiii.iiii
"DIVU", 0x87c40000, 0x05000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"DIVU", 0x87c40000, 0x05040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
"DIVS", 0x87c40000, 0x05400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"DIVS", 0x87c40000, 0x05440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"STO", 0xf0100000, 0x70000000, OPUNUSED, REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"STO", 0xf0100000, 0x70100000, OPUNUSED, REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
// 0rrr.r11f.ffcc.cxrr.rrii.iiii.iiii.iiii
"FPADD",0x87c43fff, 0x06040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(3,19),
"FPSUB",0x87c43fff, 0x06440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(3,19),
"FPMPY",0x87c43fff, 0x06840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(3,19),
"FPDIV",0x87c43fff, 0x06c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(3,19),
"FPCVT",0x87c40000, 0x07000000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(18,0), BITFIELD(3,19),
"FPCVT",0x87c40000, 0x07040000, REGFIELD(27), OPUNUSED, REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
"FPINT",0x87c40000, 0x07440000, REGFIELD(27), OPUNUSED, REGFIELD(14), IMMFIELD(14,0), BITFIELD(3,19),
//
"SUB", 0xf0100000, 0x80000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"SUB", 0xf0100000, 0x80100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
//
"AND", 0xf0100000, 0x90000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"AND", 0xf0100000, 0x90100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
//
"ADD", 0xf0100000, 0xa0000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"ADD", 0xf0100000, 0xa0100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
//
"OR", 0xf0100000, 0xb0000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"OR", 0xf0100000, 0xb0100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
//
"XOR", 0xf0100000, 0xc0000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"XOR", 0xf0100000, 0xc0100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
// 16-bit instructions, high side
//
"LSL", 0xf0100000, 0xd0000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"LSL", 0xf0100000, 0xd0100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
// LDI 1.rrrr.1001x.ccc.iiiii -> 1rrr r100 1xcc ciii ii
"CLR", 0x87c7c000, 0x84800000, REGFIELD(27),OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
// JMP 1.1111.01111.ccc.1rrrr -> 1111 1011 11cc c1rr rr
"JMP", 0xffc40000, 0xfbc40000, REGFIELD(27),OPUNUSED, REGFIELD(14), OPUNUSED, BITFIELD(2,19),
// XOR 1.rrrr.00100.ccc.01111 -> 1rrr r001 00cc c011 11
"NOT", 0x87c7c000, 0x8103c000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(2,19),
// General instructions, top half
// 1rrr.rooo.oocc.cxrr.rr
"SUB", 0x87c40000, 0x80000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"SUB", 0x87c40000, 0x80040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"ASR", 0xf0100000, 0xe0000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"ASR", 0xf0100000, 0xe0100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
"AND", 0x87c40000, 0x80400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"AND", 0x87c40000, 0x80440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"LSR", 0xf0100000, 0xf0000000, REGFIELD(24), REGFIELD(24), OPUNUSED, IMMFIELD(19,0), BITFIELD(3,21),
"LSR", 0xf0100000, 0xf0100000, REGFIELD(24), REGFIELD(24), REGFIELD(16), IMMFIELD(16,0), BITFIELD(3,21),
"ADD", 0x87c40000, 0x80800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"ADD", 0x87c40000, 0x80840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"OR", 0x87c40000, 0x80c00000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"OR", 0x87c40000, 0x80c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"XOR", 0x87c40000, 0x81000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"XOR", 0x87c40000, 0x81040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"LSR", 0x87c40000, 0x81400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"LSR", 0x87c40000, 0x81440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"LSL", 0x87c40000, 0x81800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"LSL", 0x87c40000, 0x81840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"ASR", 0x87c40000, 0x81c00000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"ASR", 0x87c40000, 0x81c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"LDIHI",0x87c40000, 0x82000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(5,14), BITFIELD(2,19),
"LDILO",0x87c40000, 0x82400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(5,14), BITFIELD(2,19),
//
"MPYU", 0x87c40000, 0x82800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"MPYU", 0x87c40000, 0x82840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"MPYS", 0x87c40000, 0x82c00000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"MPYS", 0x87c40000, 0x82c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"BREV", 0x87c40000, 0x83000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"BREV", 0x87c40000, 0x83040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"POPC", 0x87c40000, 0x83400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"POPC", 0x87c40000, 0x83440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"ROL", 0x87c40000, 0x83800000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"ROL", 0x87c40000, 0x83840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"MOV", 0x87c40000, 0x83c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"CMP", 0x87c40000, 0x84000000, OPUNUSED, REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"CMP", 0x87c40000, 0x84040000, OPUNUSED, REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"TST", 0x87c40000, 0x84400000, OPUNUSED, REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"TST", 0x87c40000, 0x84440000, OPUNUSED, REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"LOD", 0x87c40000, 0x84840000, REGFIELD(27), OPUNUSED, REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"STO", 0x87c40000, 0x84c40000, REGFIELD(27), OPUNUSED, REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"DIVU", 0x87c40000, 0x85000000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"DIVU", 0x87c40000, 0x85040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"DIVS", 0x87c40000, 0x85400000, REGFIELD(27), REGFIELD(27), OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"DIVS", 0x87c40000, 0x85440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"LDI", 0x87c40000, 0x85800000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(5,14), BITFIELD(2,19),
//
"NOOP", 0xf7c00000, 0xf6000000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
//
"BRK", 0xf7c00000, 0xf6400000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
//
"LOCK", 0xf7c00000, 0xf6800000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
//
//
"FPADD",0x87c40000, 0x86040000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"FPSUB",0x87c40000, 0x86440000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"FPMUL",0x87c40000, 0x86840000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"FPDIV",0x87c40000, 0x86c40000, REGFIELD(27), REGFIELD(27), REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"FPCVT",0x87c40000, 0x87000000, REGFIELD(27), OPUNUSED, OPUNUSED, IMMFIELD(4,14), BITFIELD(2,19),
"FPCVT",0x87c40000, 0x87040000, REGFIELD(27), OPUNUSED, REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
"FPINT",0x87c40000, 0x87440000, REGFIELD(27), OPUNUSED, REGFIELD(14), OPUNUSED, BITFIELD(2,19),
//
//
// Illegal instruction !!
"ILL", 0x00000000, 0x00000000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(32,0), OPUNUSED
};
 
const ZOPCODE zbottomlist[] = {
//
//
//
// 16-bit instructions, low side ... treat these as special
//
//
// Special case instructions. These are general instructions, but with
// special opcodes
// Conditional branches
// 0.1111.0111.ccc.0.111.10iiiii--
// 0111 1011 11cc c011 110i iiii iiii iiii
// "BRA", 0xffffe000, 0x7bc3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BLT", 0xffffe000, 0x7bcbc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BRZ", 0xffffe000, 0x7bd3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BNZ", 0xffffe000, 0x7bdbc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BGE", 0xffffe000, 0x7be3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BGT", 0xffffe000, 0x7bebc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BRC", 0xffffe000, 0x7bf3c000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
// "BRV", 0xffffe000, 0x7bfbc000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(13,0), OPUNUSED,
//
//
// CLRF ... an XOR w/ self instruction
// 0.rrrr.00100.ccc.1.rrrr.iiiii---
// 0rrr r001 00cc c1rr rr00 0000 0000 0000
// "CLRF", 0xffc7cfff, 0x7907c000, REGFIELD(27), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(3,19),
// CLR -- a LDI of zero
// LDI 1xxx.xxxx.xxxx.xxxx.xxrr.rroo.ooo.iiiii -> 1rrr r100 1xcc ciii ii
"CLR", 0x800003ff, 0x80000000, REGFIELD(12),OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
// JMP 1xxx -- xx11.1101.1111.rrrr
"JMP", 0x80203ff0, 0x80003df0, REGFIELD(12),OPUNUSED, REGFIELD(0), OPUNUSED, OPUNUSED,
"JMP", 0x80203ff0, 0x80203df0, REGFIELD(12),OPUNUSED, REGFIELD(0), OPUNUSED, BITFIELD(2,19),
//
// XOR 1xxx -- xx00.1000.1111 -> 1rrr r001 00cc c011 11
"NOT", 0x802003ff, 0x80000080, REGFIELD(12), OPUNUSED, OPUNUSED, OPUNUSED, OPUNUSED,
"NOT", 0x802003ff, 0x80200080, REGFIELD(12), OPUNUSED, OPUNUSED, OPUNUSED, BITFIELD(2,19),
// General instructions, bottom half
// 1xxx -- xxrr.rroo.ooox.rrrr
"SUB", 0x800003f0, 0x80000000, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"SUB", 0x802003f0, 0x80200000, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"SUB", 0x800003f0, 0x80000010, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"SUB", 0x802003f0, 0x80200010, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"AND", 0x800003f0, 0x80000020, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"AND", 0x802003f0, 0x80200020, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"AND", 0x800003f0, 0x80000030, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"AND", 0x802003f0, 0x80200030, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"ADD", 0x800003f0, 0x80000040, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"ADD", 0x802003f0, 0x80200040, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"ADD", 0x800003f0, 0x80000050, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"ADD", 0x802003f0, 0x80200050, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"OR", 0x800003f0, 0x80000060, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"OR", 0x802003f0, 0x80200060, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"OR", 0x800003f0, 0x80000070, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"OR", 0x802003f0, 0x80200070, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"XOR", 0x800003f0, 0x80000080, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"XOR", 0x802003f0, 0x80200080, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"XOR", 0x800003f0, 0x80000090, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"XOR", 0x802003f0, 0x80200090, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"LSR", 0x800003f0, 0x800000a0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"LSR", 0x802003f0, 0x802000a0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"LSR", 0x800003f0, 0x800000b0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"LSR", 0x802003f0, 0x802000b0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"LSL", 0x800003f0, 0x800000c0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"LSL", 0x802003f0, 0x802000c0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"LSL", 0x800003f0, 0x800000d0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"LSL", 0x802003f0, 0x802000d0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"ASR", 0x800003f0, 0x800000e0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"ASR", 0x802003f0, 0x802000e0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"ASR", 0x800003f0, 0x800000f0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"ASR", 0x802003f0, 0x802000f0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"LDIHI",0x800003e0, 0x80000100, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(5,0), BITFIELD(2,19),
"LDIHI",0x802003e0, 0x80200100, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(5,0), OPUNUSED,
//
"LDILO",0x800003e0, 0x80000120, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(5,0), BITFIELD(2,19),
"LDILO",0x802003e0, 0x80200120, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(5,0), OPUNUSED,
//
//
"MPYU", 0x800003f0, 0x80000140, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"MPYU", 0x802003f0, 0x80200140, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"MPYU", 0x800003f0, 0x80000150, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"MPYU", 0x802003f0, 0x80200150, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"MPYS", 0x800003f0, 0x80000160, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"MPYS", 0x802003f0, 0x80200160, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"MPYS", 0x800003f0, 0x80000170, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"MPYS", 0x802003f0, 0x80200170, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"BREV", 0x800003f0, 0x80000180, REGFIELD(12), OPUNUSED, OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"BREV", 0x802003f0, 0x80200180, REGFIELD(12), OPUNUSED, OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"BREV", 0x800003f0, 0x80000190, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"BREV", 0x802003f0, 0x80200190, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, OPUNUSED,
//
"POPC", 0x800003f0, 0x800001a0, REGFIELD(12), OPUNUSED, OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"POPC", 0x802003f0, 0x802001a0, REGFIELD(12), OPUNUSED, OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"POPC", 0x800003f0, 0x800001b0, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"POPC", 0x802003f0, 0x802001b0, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, OPUNUSED,
//
"ROL", 0x800003f0, 0x800001c0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"ROL", 0x802003f0, 0x802001c0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"ROL", 0x800003f0, 0x800001d0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"ROL", 0x802003f0, 0x802001d0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"MOV", 0x800003f0, 0x800001f0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"MOV", 0x802003f0, 0x802001f0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"CMP", 0x800003f0, 0x80000200, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"CMP", 0x802003f0, 0x80200200, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"CMP", 0x800003f0, 0x80000210, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"CMP", 0x802003f0, 0x80200210, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"TST", 0x800003f0, 0x80000220, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"TST", 0x802003f0, 0x80200220, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"TST", 0x800003f0, 0x80000230, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"TST", 0x802003f0, 0x80200230, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"LOD", 0x800003f0, 0x80000250, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"LOD", 0x802003f0, 0x80200250, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, OPUNUSED,
//
"STO", 0x800003f0, 0x80000270, OPUNUSED, REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"STO", 0x802003f0, 0x80200270, OPUNUSED, REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"DIVU", 0x800003f0, 0x80000280, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"DIVU", 0x802003f0, 0x80200280, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"DIVU", 0x800003f0, 0x80000290, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"DIVU", 0x802003f0, 0x80200290, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"DIVS", 0x800003f0, 0x800002a0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"DIVS", 0x802003f0, 0x802002a0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"DIVS", 0x800003f0, 0x800002b0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
"DIVS", 0x802003f0, 0x802002b0, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
//
"LDI", 0x802003d0, 0x800002c0, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
//
"NOOP", 0x80003bf0, 0x80003b00, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
//
"BRK", 0x80003bf0, 0x80003b20, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
//
"LOCK", 0x80003bf0, 0x80003b40, REGFIELD(12), REGFIELD(12), OPUNUSED, IMMFIELD(4,0), OPUNUSED,
//
// FPU instructions
//
"FPADD",0x802003f0, 0x80000310, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
"FPADD",0x802003f0, 0x80200310, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
//
"FPSUB",0x802003f0, 0x80000330, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
"FPSUB",0x802003f0, 0x80200330, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
//
"FPMUL",0x802003f0, 0x80000350, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
"FPMUL",0x802003f0, 0x80200350, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
//
"FPDIV",0x802003f0, 0x80000370, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, OPUNUSED,
"FPDIV",0x802003f0, 0x80200370, REGFIELD(12), REGFIELD(12), REGFIELD(0), OPUNUSED, BITFIELD(2,19),
// Convert to floating point
"FPCVT",0x802003f0, 0x80000380, REGFIELD(12), OPUNUSED, OPUNUSED, IMMFIELD(4,0), OPUNUSED,
"FPCVT",0x802003f0, 0x80200380, REGFIELD(12), OPUNUSED, OPUNUSED, IMMFIELD(4,0), BITFIELD(2,19),
"FPCVT",0x802003f0, 0x80000390, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, OPUNUSED,
"FPCVT",0x802003f0, 0x80200390, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, BITFIELD(2,19),
// Convert to integer
"FPINT",0x802003f0, 0x800003b0, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, OPUNUSED,
"FPINT",0x802003f0, 0x802003b0, REGFIELD(12), OPUNUSED, REGFIELD(0), OPUNUSED, BITFIELD(2,19),
//
//
// Illegal instruction !!
"ILL", 0x00000000, 0x00000000, OPUNUSED, OPUNUSED, OPUNUSED, IMMFIELD(32,0), OPUNUSED
};
 
 
const int nzoplist = (sizeof(zoplist)/sizeof(ZOPCODE));
const int nzopbottom = (sizeof(zbottomlist)/sizeof(ZOPCODE));
 
static int getbits(const ZIPI ins, const int which) {
if (which & 0x40000000) {
188,9 → 513,14
}
 
void zipi_to_string(const ZIPI ins, char *line) {
for(int i=0; i<nzoplist; i++)
assert(((~zoplist[i].s_mask)&zoplist[i].s_val)==0);
for(int i=0; i<nzoplist; i++) {
if (((~zoplist[i].s_mask)&zoplist[i].s_val)!=0) {
printf("Instruction %d, %s, fails consistency check\n",
i, zoplist[i].s_opstr);
assert(((~zoplist[i].s_mask)&zoplist[i].s_val)==0);
}
}
for(int i=0; i<nzoplist; i++) {
// printf("%2d: %6s %08x & %08x == %08x\n",
// i, zoplist[i].s_opstr, ins,
// zoplist[i].s_mask, zoplist[i].s_val);
/zasm/zparser.cpp
14,7 → 14,7
// op_noop() returns the instruction code for a NOOP instruction.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
46,6 → 46,7
#include <string.h>
#include <ctype.h>
#include <strings.h>
#include <assert.h>
 
#include "zparser.h"
#include "zopcodes.h"
52,35 → 53,42
 
typedef ZPARSER::ZIPI ZIPI; // A Zip Instruction (i.e. uint32)
 
#define IMMOP(OP,CND,IMM,A) (((OP&0x0f)<<28)|((A&0x0f)<<24)|((CND&0x07)<<21) \
| (IMM & 0x0fffff))
#define IMMOP(OP,CND,IMM,A) (((OP&0x01f)<<22)|((A&0x0f)<<27)|((CND&0x07)<<19) \
| (IMM & 0x03ffff))
 
#define DBLREGOP(OP,CND,IMM,B,A) (((OP&0x0f)<<28)|((A&0x0f)<<24) \
|((CND&0x07)<<21)|(1<<20)|((B&0x0f)<<16) \
| (IMM & 0x0ffff))
#define DBLREGOP(OP,CND,IMM,B,A) (((OP&0x01f)<<22)|((A&0x0f)<<27) \
|((CND&0x07)<<19)|(1<<18)|((B&0x0f)<<14) \
| (IMM & 0x03fff))
 
ZIPI ZPARSER::op_cmp(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0x0, cnd, imm, b, a);
return DBLREGOP(ZIPO_CMP, cnd, imm, b, a);
}
 
ZIPI ZPARSER::op_cmp(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0x0, cnd, imm, a);
return IMMOP(ZIPO_CMP, cnd, imm, a);
}
 
 
ZIPI ZPARSER::op_tst(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0x1, cnd, imm, b, a);
return DBLREGOP(ZIPO_TST, cnd, imm, b, a);
} ZIPI ZPARSER::op_tst(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0x1, cnd, imm, a);
return IMMOP(ZIPO_TST, cnd, imm, a);
}
 
ZIPI ZPARSER::op_mov(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
ZIPI in;
in = (0x02 << 28)|((a&0x0f)<<24)|((cnd&0x07)<<21);
in |= (a&0x10)<<16;
in |= (b&0x0f)<<16;
in |= (b&0x10)<<11;
in |= imm & 0x07fff;
 
in = (ZIPO_MOV)<<22;
in |= ((a &0x0f)<<27);
in |= ((cnd&0x07)<<19);
in |= ((b &0x0f)<<14);
in |= ( imm&0x01fff);
 
 
if (b & 0x10)
in |= (1<<13);
if (a & 0x10)
in |= (1<<18);
return in;
}
 
87,7 → 95,7
 
ZIPI ZPARSER::op_ldi(ZIPIMM imm, ZIPREG a) const {
ZIPI in;
in = ((0x03)<<28) | ((a&0x0f)<<24) | (imm & ((1<<24)-1));
in = ((a&0x0f)<<27) | (ZIPO_LDI << 22) | (imm & ((1<<23)-1));
return in;
}
 
103,109 → 111,299
}
 
ZIPI ZPARSER::op_noop(void) const {
return 0x4e000000;
return 0x76000000;
} ZIPI ZPARSER::op_break(void) const {
return 0x76400000;
} ZIPI ZPARSER::op_lock(void) const {
return 0x76800000;
}
ZIPI ZPARSER::op_break(void) const {
return 0x4e000001;
}
 
ZIPI ZPARSER::op_ldihi(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
ZIPI in;
in = ((0x4f)<<24)|((cnd&0x07)<<21)|(1<<20)|((a&0x0f)<<16);
in |= (imm & 0x0ffff);
ZIPI in = IMMOP(ZIPO_LDIHI, cnd, (imm & 0x0ffff), a);
return in;
}
ZIPI ZPARSER::op_ldilo(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
ZIPI in;
in = ((0x4f)<<24)|((cnd&0x07)<<21)|(0<<20)|((a&0x0f)<<16);
in |= (imm & 0x0ffff);
} ZIPI ZPARSER::op_ldilo(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
ZIPI in = IMMOP(ZIPO_LDILO, cnd, (imm & 0x0ffff), a);
return in;
}
 
ZIPI ZPARSER::op_mpyu(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return (0x04<<28)|((a&0x0f)<<24)|((cnd&0x7)<<21)|(0<<20)|((b&0x0f)<<16)|(imm & 0x0ffff);
return DBLREGOP(ZIPO_MPYU, cnd, imm, b, a);
} ZIPI ZPARSER::op_mpyu(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return (0x04<<28)|((a&0x0f)<<24)|((cnd&0x7)<<21)|(0<<20)|((0x0f)<<16)|(imm & 0x0ffff);
return IMMOP(ZIPO_MPYU, cnd, imm & 0x0ffff, a);
}
 
ZIPI ZPARSER::op_mpys(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return (0x04<<28)|((a&0x0f)<<24)|((cnd&0x7)<<21)|(1<<20)|((b&0x0f)<<16)|(imm & 0x0ffff);
return DBLREGOP(ZIPO_MPYS, cnd, imm, b, a);
} ZIPI ZPARSER::op_mpys(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return (0x04<<28)|((a&0x0f)<<24)|((cnd&0x7)<<21)|(1<<20)|((0x0f)<<16)|(imm & 0x0ffff);
return IMMOP(ZIPO_MPYS, cnd, imm & 0x0ffff, a);
}
 
ZIPI ZPARSER::op_rol(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0x5, cnd, imm, b, a);
return DBLREGOP(ZIPO_ROL, cnd, imm, b, a);
} ZIPI ZPARSER::op_rol(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0x5, cnd, imm, a);
return IMMOP(ZIPO_ROL, cnd, imm, a);
}
 
ZIPI ZPARSER::op_popc(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(ZIPO_POPC, cnd, imm, b, a);
} ZIPI ZPARSER::op_popc(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(ZIPO_POPC, cnd, imm, a);
}
 
ZIPI ZPARSER::op_brev(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(ZIPO_BREV, cnd, imm, b, a);
} ZIPI ZPARSER::op_brev(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(ZIPO_BREV, cnd, imm, a);
}
 
ZIPI ZPARSER::op_lod(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0x6, cnd, imm, b, a);
return DBLREGOP(ZIPO_LOD, cnd, imm, b, a);
} ZIPI ZPARSER::op_lod(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0x6, cnd, imm, a);
return IMMOP(ZIPO_LOD, cnd, imm, a);
}
 
 
ZIPI ZPARSER::op_sto(ZIPCOND cnd, ZIPREG v, ZIPIMM imm, ZIPREG b) const {
return DBLREGOP(0x7, cnd, imm, b, v);
return DBLREGOP(ZIPO_STO, cnd, imm, b, v);
} ZIPI ZPARSER::op_sto(ZIPCOND cnd, ZIPREG v, ZIPIMM imm) const {
return IMMOP(0x7, cnd, imm, v);
return IMMOP(ZIPO_STO, cnd, imm, v);
}
 
 
ZIPI ZPARSER::op_sub(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0x8, cnd, imm, b, a);
return DBLREGOP(ZIPO_SUB, cnd, imm, b, a);
} ZIPI ZPARSER::op_sub(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
// While it seems like we might do well replacing a subtract immediate
// with an add of the negative same, the conditions aren't the same
// when doing so. Hence this is an invalid substitution.
// return IMMOP(0xa, cnd, -imm, a); // Do an add of the negative of imm
return IMMOP(0x8, cnd, imm, a);
return IMMOP(ZIPO_SUB, cnd, imm, a);
}
 
 
ZIPI ZPARSER::op_and(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0x9, cnd, imm, b, a);
return DBLREGOP(ZIPO_AND, cnd, imm, b, a);
} ZIPI ZPARSER::op_and(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0x9, cnd, imm, a);
return IMMOP(ZIPO_AND, cnd, imm, a);
}
 
 
ZIPI ZPARSER::op_add(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0xa, cnd, imm, b, a);
return DBLREGOP(ZIPO_ADD, cnd, imm, b, a);
} ZIPI ZPARSER::op_add(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0xa, cnd, imm, a);
return IMMOP(ZIPO_ADD, cnd, imm, a);
}
 
 
ZIPI ZPARSER::op_or(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0xb, cnd, imm, b, a);
return DBLREGOP(ZIPO_OR, cnd, imm, b, a);
} ZIPI ZPARSER::op_or(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0xb, cnd, imm, a);
return IMMOP(ZIPO_OR, cnd, imm, a);
}
 
ZIPI ZPARSER::op_xor(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0xc, cnd, imm, b, a);
return DBLREGOP(ZIPO_XOR, cnd, imm, b, a);
} ZIPI ZPARSER::op_xor(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0xc, cnd, imm, a);
return IMMOP(ZIPO_XOR, cnd, imm, a);
}
 
ZIPI ZPARSER::op_lsl(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0xd, cnd, imm, b, a);
return DBLREGOP(ZIPO_LSL, cnd, imm, b, a);
} ZIPI ZPARSER::op_lsl(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0xd, cnd, imm, a);
return IMMOP(ZIPO_LSL, cnd, imm, a);
}
 
ZIPI ZPARSER::op_asr(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0xe, cnd, imm, b, a);
return DBLREGOP(ZIPO_ASR, cnd, imm, b, a);
} ZIPI ZPARSER::op_asr(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0xe, cnd, imm, a);
return IMMOP(ZIPO_ASR, cnd, imm, a);
}
 
ZIPI ZPARSER::op_lsr(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(0xf, cnd, imm, b, a);
return DBLREGOP(ZIPO_LSR, cnd, imm, b, a);
} ZIPI ZPARSER::op_lsr(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(0xf, cnd, imm, a);
return IMMOP(ZIPO_LSR, cnd, imm, a);
}
 
ZIPI ZPARSER::op_divu(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(ZIPO_DIVU, cnd, imm, b, a);
} ZIPI ZPARSER::op_divu(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(ZIPO_DIVU, cnd, imm, a);
}
 
ZIPI ZPARSER::op_divs(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const {
return DBLREGOP(ZIPO_DIVS, cnd, imm, b, a);
} ZIPI ZPARSER::op_divs(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const {
return IMMOP(ZIPO_DIVS, cnd, imm, a);
}
 
ZPARSER::ZIPIMM ZPARSER::immediate(const ZIPI a) {
ZIPOP op((ZIPOP)((a>>25)&0x012));
ZIPIMM imm;
switch(op) {
case ZIPO_MOV:
imm = (a & 0x0fff); if (a&0x1fff) imm |= -0x1000; break;
case ZIPO_LDI:
imm = (a & 0x03fffff); break;
case ZIPO_LDIn:
imm = (a & 0x03fffff); imm |= -0x200000; break;
case ZIPO_LDILO: case ZIPO_LDIHI:
imm = (a & 0x0ffff); break;
default:
if (a & 0x040000) {
imm = (a&0x3fff);
if (a&0x2000) imm |= -0x02000;
if (imm != 0)
return false;
} else {
imm = (a&0x3ffff);
if (a&0x20000)
imm |= -0x20000;
}
}
 
return imm;
}
 
bool ZPARSER::can_merge(const ZIPI a, const ZIPI b) {
// 1. Can't merge anything that's already merged
if ((a|b) & 0x80000000)
return false;
 
ZIPOP opa((ZIPOP)((a>>25)&0x012)), opb((ZIPOP)((b>>22)&0x01f));
// 2. Conditions
{
ZIPCOND ca((ZIPCOND)((a>>19)&0x07)),cb((ZIPCOND)((b>>19)&0x07));
 
if ((opa == ZIPO_LDI)||(opa == ZIPO_LDIn))
ca = ZIPC_ALWAYS;
if ((opb == ZIPO_LDI)||(opb == ZIPO_LDIn))
cb = ZIPC_ALWAYS;
 
if ((ca == ZIPC_ALWAYS)&&(cb != ZIPC_ALWAYS))
return false;
if ((ca|cb) &0x04)
return false;
if ((ca != ZIPC_ALWAYS)&&((cb != ca)&&(cb != ZIPC_ALWAYS)))
return false;
// if ((ca != ZIPC_ALWAYS)||(cb != ZIPC_ALWAYS))
// return false;
}
 
// 3. Moves ... only move if the move doesn't address user registers
 
if ((opa == ZIPO_MOV)&&(a & ((1<<18)|(1<<13))))
return false;
if ((opb == ZIPO_MOV)&&(b & ((1<<18)|(1<<13))))
return false;
 
// 4. Immediates. If Register + Immediate, the answer is No.
ZIPIMM imma, immb;
switch(opa) {
case ZIPO_MOV:
imma = (a & 0x0fff); if (a) return false; break;
case ZIPO_LDI: case ZIPO_LDIn:
case ZIPO_LDILO: case ZIPO_LDIHI:
imma = immediate(a); break;
default:
if (a & 0x040000) {
imma = (a&0x3ffff);
// if (a&0x20000) a |= -0x20000;
if (imma != 0)
return false;
} else {
imma = (a&0x3fff);
if (a&0x2000) // Sign extension?
imma |= -0x02000;
}
} switch(opb) {
case ZIPO_MOV:
immb = (b & 0x0fff); if (b) return false; break;
case ZIPO_LDI: case ZIPO_LDIn:
case ZIPO_LDILO: case ZIPO_LDIHI:
immb = immediate(b); break;
default:
if (b & 0x040000) {
immb = (b&0x3fff);
// if (b&0x2000) b |= -0x02000;
if (immb != 0)
return false;
} else {
immb = (b&0x3ffff);
if (b&0x20000)
immb |= -0x20000;
}
}
 
if ((opa == ZIPO_LDI)||(opa == ZIPO_LDIn)||(opa == ZIPO_LDILO)||(opa == ZIPO_LDIHI)) {
if ((imma > 15)||(imma < -16))
return false;
} else if ((imma > 7)||(imma < -8))
return false;
if ((opb == ZIPO_LDI)||(opb == ZIPO_LDIn)||(opb == ZIPO_LDILO)||(opb == ZIPO_LDIHI)) {
if ((immb > 15)||(immb < -16))
return false;
} else if ((immb > 7)||(immb < -8))
return false;
 
return true;
}
 
ZIPI ZPARSER::merge(const ZIPI a, const ZIPI b) {
assert(can_merge(a, b));
ZIPI ni;
 
ZIPCOND ca( (ZIPCOND)((a>>19)&0x007)), cb( (ZIPCOND)((b>>19)&0x007));
ZIPOP opa((ZIPOP)((a>>25)&0x012)), opb((ZIPOP)((b>>22)&0x01f));
 
if ((opa == ZIPO_LDI)||(opa == ZIPO_LDIn))
ca = ZIPC_ALWAYS;
if ((opb == ZIPO_LDI)||(opb == ZIPO_LDIn))
cb = ZIPC_ALWAYS;
 
ZIPIMM imma, immb;
imma = immediate(a);
immb = immediate(b);
 
ni = (opa << 26)|(opb<<9)|0x80000000;
if (ca != ZIPC_ALWAYS) {
ni |= (ca << 19);
if (cb == ca)
ni |= (1<<21);
}
 
// The result register(s)
ni |= (a & 0x78000000);
ni |= ((b>>27)&0x0f)<<5;
 
// Are we using the register form of opB?
switch(opa) {
case ZIPO_MOV: ni |= (a&0x078000); break; // Always a register
case ZIPO_LDI: case ZIPO_LDIn:
case ZIPO_LDILO: case ZIPO_LDIHI:
ni |= (imma & 0x01f)<<14;
break;
default:
if (a & 0x040000) {
ni |= (a&0x078000);
} else
ni |= (imma & 0x0f)<<14;
}
 
switch(opb) {
case ZIPO_MOV:
ni |= ((b>>14)&0x0f)|0x10; break;
case ZIPO_LDI: case ZIPO_LDIn:
case ZIPO_LDILO: case ZIPO_LDIHI:
ni |= (immb & 0x01f);
break;
default:
if (b & 0x040000) {
ni |= ((b>>14)&0x0f)|0x10;
} else
ni |= (immb & 0x0f);
}
 
return ni;
}
/zasm/zopcodes.h
8,7 → 8,7
// some of their shortcut synonyms.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/zasm/zparser.h
14,7 → 14,7
// in this file.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
59,11 → 59,27
} ZIPREG;
 
typedef enum {
ZIPC_ALWAYS, ZIPC_Z, ZIPC_NZ, ZIPC_GE, ZIPC_GT, ZIPC_LT,
ZIPC_C, ZIPC_V
ZIPC_ALWAYS, ZIPC_LT, ZIPC_Z, ZIPC_NZ,
ZIPC_GT, ZIPC_GE, ZIPC_C, ZIPC_V
} ZIPCOND;
 
typedef enum {
// 16 ALU instructions
ZIPO_SUB=0, ZIPO_AND, ZIPO_ADD, ZIPO_OR, // 5'h000xx
ZIPO_XOR, ZIPO_LSR, ZIPO_LSL, ZIPO_ASR, // 5'h001xx
ZIPO_LDIHI, ZIPO_LDILO, ZIPO_MPYU, ZIPO_MPYS, // 5'h010xx
ZIPO_BREV, ZIPO_POPC, ZIPO_ROL, ZIPO_MOV, // 5'h011xx
ZIPO_CMP, ZIPO_TST, // 5'h1000x
ZIPO_LOD, ZIPO_STO, // 5'h1001w
ZIPO_DIVU, ZIPO_DIVS, // 5'h1010s
ZIPO_LDI, ZIPO_LDIn, // 5'h1011x
// ZIPO_, ZIPO_DIVS, // 5'h11000
ZIPO_FPADD=0x18, ZIPO_FPSUB, // 5'h1100x
ZIPO_FPMUL, ZIPO_FPDIV, // 5'h1101x
ZIPO_FPCVT, ZIPO_FPINT, // 5'h1110x
} ZIPOP;
 
 
ZIPI op_cmp(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const;
ZIPI op_cmp(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
ZIPI op_cmp(ZIPIMM imm, ZIPREG b, ZIPREG a) const
92,6 → 108,7
 
ZIPI op_noop(void) const;
ZIPI op_break(void) const;
ZIPI op_lock(void) const;
 
ZIPI op_ldihi(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
ZIPI op_ldilo(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
121,6 → 138,20
ZIPI op_rol(ZIPIMM imm, ZIPREG a) const
{ return op_rol(ZIPC_ALWAYS, imm, a); }
 
ZIPI op_popc(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const;
ZIPI op_popc(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
ZIPI op_popc(ZIPIMM imm, ZIPREG b, ZIPREG a) const
{ return op_popc(ZIPC_ALWAYS, imm, b, a); }
ZIPI op_popc(ZIPIMM imm, ZIPREG a) const
{ return op_popc(ZIPC_ALWAYS, imm, a); }
 
ZIPI op_brev(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const;
ZIPI op_brev(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
ZIPI op_brev(ZIPIMM imm, ZIPREG b, ZIPREG a) const
{ return op_brev(ZIPC_ALWAYS, imm, b, a); }
ZIPI op_brev(ZIPIMM imm, ZIPREG a) const
{ return op_brev(ZIPC_ALWAYS, imm, a); }
 
ZIPI op_lod(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const;
ZIPI op_lod(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
ZIPI op_lod(ZIPIMM imm, ZIPREG b, ZIPREG a) const
224,12 → 255,12
{ return op_xor(cnd, 0, a, a); }
ZIPI op_clrf(ZIPREG a) const
{ return op_xor(ZIPC_ALWAYS, 0, a, a); }
ZIPI op_retn(ZIPCOND c) const
{ return op_lod(c, 1, ZIP_SP, ZIP_PC); }
// ZIPI op_retn(ZIPCOND c) const
// { return op_lod(c, 1, ZIP_SP, ZIP_PC); }
ZIPI op_halt(ZIPCOND c) const {
return op_or(c, 0x10, ZIP_CC); }
ZIPI op_wait(ZIPCOND c) const {
return op_or(c, 0x10, ZIP_CC); }
return op_or(c, 0x30, ZIP_CC); }
ZIPI op_halt(void) const {
return op_or(ZIPC_ALWAYS, 0x10, ZIP_CC); }
ZIPI op_wait(void) const {
255,6 → 286,15
ZIPI op_not(ZIPREG r) const
{ return op_xor(ZIPC_ALWAYS, -1, r); }
 
ZIPI op_divu(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const;
ZIPI op_divu(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
ZIPI op_divs(ZIPCOND cnd, ZIPIMM imm, ZIPREG b, ZIPREG a) const;
ZIPI op_divs(ZIPCOND cnd, ZIPIMM imm, ZIPREG a) const;
 
bool can_merge(const ZIPI a, const ZIPI b);
ZIPI merge(const ZIPI a, const ZIPI b);
ZIPIMM immediate(const ZIPI a);
 
};
 
#endif
/zasm/Makefile
18,7 → 18,7
#
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Tecnology, LLC
# Gisselquist Technology, LLC
#
################################################################################
#

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