OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk
    from Rev 110 to Rev 111
    Reverse comparison

Rev 110 → Rev 111

/sw/gas-script.sh
2,7 → 2,7
 
if [[ ! -d binutils-2.25 ]]
then
tar -xvjf ./binutils-2.25.tar.bz2
tar -xjf ./binutils-2.25.tar.bz2
cd binutils-2.25
patch -p1 <../binutils-2.25.patch
cd ..
26,5 → 26,3
--enable-gold=yes --enable-plugins --enable-threads \
--disable-werror
 
make
make install
/sw/gcc-script.sh
15,20 → 15,20
CLFS_HOST="x86_64-cross-linux-gnu"
CLFS_TARGET="zip"
INSTALL_BASE=`pwd`/install
mkdir -p ${INSTALL_BASE}/cross-tools
mkdir -p ${INSTALL_BASE}/cross-tools/bin
mkdir -p ${INSTALL_BASE}/tools/lib
mkdir -p ${INSTALL_BASE}/usr/include
mkdir -p build-gcc
cd build-gcc
 
AR_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-ar
AS_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-as
LD_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-ld
NM_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-nm
OBJCOPY_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-objcopy
OBJDUMP_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-objdump
READELF_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-readelf
STRIP_FOR_TARGET=${INSTALL_BASE}/cross-tools/zip-strip
AR_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-ar
AS_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-as
LD_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-ld
NM_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-nm
OBJCOPY_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-objcopy
OBJDUMP_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-objdump
READELF_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-readelf
STRIP_FOR_TARGET=${INSTALL_BASE}/cross-tools/bin/zip-strip
 
AS=as AR=ar ../gcc-5.3.0-zip/configure --with-gas \
--prefix=${INSTALL_BASE}/cross-tools \
/sw/gcc-zippatch.patch
46,6 → 46,23
esac
# If we aren't building newlib, then don't build libgloss, since libgloss
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
--- gcc-5.3.0-original/gcc/cgraphbuild.c 2015-01-09 15:18:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c 2016-03-24 22:13:24.815287808 -0400
@@ -62,6 +62,13 @@
#include "ipa-prop.h"
#include "ipa-inline.h"
+#ifdef DO_ZIP_DEBUGS
+extern void zip_debug_rtx(const_rtx);
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
+#else
+#define ZIP_DEBUG_LINE(STR,RTX)
+#endif
+
/* Context of record_reference. */
struct record_reference_ctx
{
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c 1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c 2016-02-14 00:54:31.821055716 -0500
103,7 → 120,7
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-03-25 10:21:47.127775498 -0400
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400
@@ -21,7 +21,7 @@
#ifndef GCC_AARCH64_LINUX_H
115,7 → 132,7
#undef ASAN_CC1_SPEC
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-03-25 10:21:47.127775498 -0400
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500
@@ -23,8 +23,8 @@
#define EXTRA_SPECS \
129,7 → 146,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
#elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500
@@ -68,8 +68,8 @@
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */
143,7 → 160,7
#define GLIBC_DYNAMIC_LINKER \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400
@@ -62,7 +62,7 @@
155,7 → 172,7
#define LINUX_TARGET_LINK_SPEC "%{h*} \
%{static:-Bstatic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -45,7 +45,7 @@
%{shared:-G -Bdynamic} \
167,7 → 184,7
#undef TARGET_SUPPORTS_SYNC_CALLS
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -102,7 +102,7 @@
#undef CRIS_DEFAULT_CPU_VERSION
179,7 → 196,7
#undef CRIS_LINK_SUBTARGET_SPEC
#define CRIS_LINK_SUBTARGET_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400
@@ -129,9 +129,9 @@
#endif
194,7 → 211,7
/* NOTE: The freebsd-spec.h header is included also for various
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -34,7 +34,7 @@
#define ENDFILE_SPEC \
206,7 → 223,7
#undef LINK_SPEC
#define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -22,7 +22,7 @@
#define GNU_USER_LINK_EMULATION "elf_i386"
218,7 → 235,7
#undef STARTFILE_SPEC
#if defined HAVE_LD_PIE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500
@@ -22,6 +22,6 @@
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
231,7 → 248,7
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -19,4 +19,4 @@
<http://www.gnu.org/licenses/>. */
240,7 → 257,7
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500
@@ -27,6 +27,6 @@
#define GNU_USER_LINK_EMULATION64 "elf_x86_64"
253,7 → 270,7
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -20,4 +20,4 @@
<http://www.gnu.org/licenses/>. */
262,7 → 279,7
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -55,7 +55,7 @@
/* Define this for shared library support because it isn't in the main
274,7 → 291,7
#undef LINK_SPEC
#define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -32,4 +32,4 @@
283,7 → 300,7
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
@@ -31,5 +31,4 @@
while (0)
293,7 → 310,7
-
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
--- gcc-5.3.0-original/gcc/config/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -73,10 +73,10 @@
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
311,7 → 328,7
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
@@ -67,7 +67,7 @@
%{shared:-shared} \
323,7 → 340,7
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -71,7 +71,7 @@
When the -shared link option is used a final link is not being
335,7 → 352,7
#undef LINK_SPEC
#define LINK_SPEC "-m m68kelf %{shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
@@ -28,7 +28,7 @@
#undef TLS_NEEDS_GOT
347,7 → 364,7
#define SUBTARGET_EXTRA_SPECS \
{ "dynamic_linker", DYNAMIC_LINKER }
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -22,20 +22,20 @@
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
377,7 → 394,7
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
#define GNU_USER_DYNAMIC_LINKERN32 \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -32,7 +32,7 @@
#undef ASM_SPEC
389,7 → 406,7
#undef LINK_SPEC
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-03-08 04:57:02.962902614 -0500
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400
@@ -37,7 +37,7 @@
/* Define this for shared library support because it isn't in the main
401,7 → 418,7
#undef LINK_SPEC
#define LINK_SPEC "\
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-03-25 10:21:47.243774882 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400
@@ -357,14 +357,14 @@
#undef LINK_OS_DEFAULT_SPEC
424,7 → 441,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
#elif DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400
@@ -757,8 +757,8 @@
438,7 → 455,7
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400
@@ -60,8 +60,8 @@
#define MULTILIB_DEFAULTS { "m31" }
452,7 → 469,7
#undef LINK_SPEC
#define LINK_SPEC \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -43,7 +43,7 @@
464,7 → 481,7
#undef SUBTARGET_LINK_EMUL_SUFFIX
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500
@@ -84,8 +84,8 @@
When the -shared link option is used a final link is not being
487,7 → 504,7
%{!static: \
%{rdynamic:-export-dynamic} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -83,7 +83,7 @@
When the -shared link option is used a final link is not being
499,7 → 516,7
#undef LINK_SPEC
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -41,7 +41,7 @@
%{!shared: \
511,7 → 528,7
#undef WCHAR_TYPE
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-03-08 04:57:02.966902587 -0500
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-03-25 10:21:47.315774500 -0400
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500
@@ -44,7 +44,7 @@
%{mlongcalls:--longcalls} \
661,8 → 678,8
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-03-08 04:27:14.906499512 -0500
@@ -0,0 +1,2175 @@
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-03-24 21:28:04.199373113 -0400
@@ -0,0 +1,2324 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: zip.c
773,6 → 790,8
+static int zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
+static bool zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
+static unsigned HOST_WIDE_INT zip_const_anchor = 0x20000;
+static HOST_WIDE_INT zip_min_opb_imm = -0x200000;
+static HOST_WIDE_INT zip_max_opb_imm = 0x1fffff;
+static HOST_WIDE_INT zip_min_anchor_offset = -0x20000;
+static HOST_WIDE_INT zip_max_anchor_offset = 0x1ffff;
+static HOST_WIDE_INT zip_min_mov_offset = -0x1000;
784,8 → 803,8
+ void zip_debug_rtx(const_rtx x);
+static void zip_override_options(void);
+static bool zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
+// static void zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
+static int zip_memory_move_cost(machine_mode, reg_class_t, bool);
+static rtx zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
+
+
+#define ALL_DEBUG_OFF false
908,9 → 927,11
+ }
+ break;
+ case PLUS:
+ if (!REG_P(XEXP(x, 0)))
+ if (!REG_P(XEXP(x, 0))) {
+ fprintf(stderr, "Unsupported address construct\n");
+ zip_debug_rtx(x);
+ abort();
+ if (CONST_INT_P(XEXP(x, 1))) {
+ } if (CONST_INT_P(XEXP(x, 1))) {
+ if (INTVAL(XEXP(x,1))!=0) {
+ fprintf(file, "%ld(%s)",
+ INTVAL(XEXP(x, 1)),
955,7 → 976,12
+ if (dbg) zip_debug_rtx(x);
+ zip_print_operand_address(file, XEXP(x, 0));
+ break;
+ case CONST_INT:
+ fprintf(file, "%ld",INTVAL(x));
+ break;
+ default:
+ fprintf(stderr, "Unknown address format\n");
+ zip_debug_rtx(x);
+ abort(); break;
+ // output_addr_const(file, x);
+ break;
1523,9 → 1549,6
+ CC_STATUS_INIT;
+ if (dbg) fprintf(stderr, "\tINIT-CC\n");
+ return;
+ } else if (ccr == CCRESULT_UNCHANGED) {
+ if (dbg) fprintf(stderr, "\tUnchanged CC\n");
+ return;
+ }
+
+ if ((GET_CODE(exp) == PARALLEL)&&(GET_CODE(XVECEXP(exp, 0, 0))==SET)) {
1544,6 → 1567,31
+ return;
+ }
+
+
+ if (ccr == CCRESULT_UNCHANGED) {
+ if (dbg) fprintf(stderr, "\tUnchanged CC\n");
+
+ // We can't just run away here ... even though the CC result
+ // hasn't changed, GCC's ability to recognize it as a valid
+ // result has changed. In other words, if we just 'set' a
+ // value contained within either value1 or value2, then we'll
+ // need to update those values so that they are no longer looked
+ // upon as potentially containing the current CC values.
+
+ if (dest) {
+ if (dest == cc0_rtx)
+ CC_STATUS_INIT;
+ else if ((REG_P(dest))&&(dest != pc_rtx)) {
+ // An example here might be a load instruction
+ if (reg_mentioned_p(dest, cc_status.value1))
+ cc_status.value1 = NULL_RTX;
+ if (reg_mentioned_p(dest, cc_status.value2))
+ cc_status.value2 = NULL_RTX;
+ }
+ }
+ return;
+ }
+
+ // Gotta wait on this test, until we know whether or not the
+ // conditionally executed instruction was designed to set the
+ // CC0 register.
1550,8 → 1598,16
+ conditionally_executed = get_attr_conditional(insn);
+ if ((conditionally_executed == CONDITIONAL_YES)&&(dest != cc0_rtx)) {
+ // cc_status is unchanged
+ // However, GCC's vision of it may have changed
+ //
+ // Initialize CC_STATUS
+ if (dbg) fprintf(stderr, "\tCC -- unchanged (conditional exec)\n");
+ CC_STATUS_INIT;
+ return;
+ } else if (GET_CODE(src)==IF_THEN_ELSE) {
+ // Same thing as above
+ CC_STATUS_INIT;
+ return;
+ }
+
+ if (ccr == CCRESULT_VALIDZN)
1865,14 → 1921,27
+ }}
+ */
+ zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
+ debug_rtx(x);
+ zip_debug_print(pfx, lvl, ")");
+ break;
+ case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
+ zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
+ zip_debug_print(pfx, lvl, ")");
+ /*
+ if (JUMP_LABEL(x)) {
+ zip_debug_print(pfx, lvl+1, "(w/Label)");
+ if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
+ char buf[64];
+ sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
+ zip_debug_print(pfx, lvl+1, buf);
+ } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
+ char buf[64];
+ sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
+ zip_debug_print(pfx, lvl+1, buf);
+ } else
+ zip_debug_print(pfx, lvl+1, "(w/Label))");
+ } else
+ zip_debug_print(pfx, lvl+1, "(NO label)");
+ zip_debug_print(pfx, lvl+1, "(NO label))");
+ debug_rtx(x);
+ */
+ break;
+ case CALL:
+ zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
1900,7 → 1969,7
+ case CODE_LABEL:
+ {
+ char buf[64];
+ sprintf(buf, "(CODE_LABEL %d)", CODE_LABEL_NUMBER(x));
+ sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
+ } break;
+ case SET:
1947,18 → 2016,26
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
+ zip_debug_print(pfx, lvl, ")");
+ break;
+ case CONST:
+ zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+ zip_debug_print(pfx, lvl, ")");
+ break;
+ case CONST_INT:
+ { char buf[25];
+ if (GET_MODE(x)==SImode)
+ sprintf(buf, "(CONST:SI %ld)", INTVAL(x));
+ sprintf(buf, "(CONST_INT:SI %ld)", INTVAL(x));
+ else if (GET_MODE(x)==VOIDmode)
+ sprintf(buf, "(CONST:V %ld)", INTVAL(x));
+ sprintf(buf, "(CONST_INT:V %ld)", INTVAL(x));
+ else
+ sprintf(buf, "(CONST:? %ld)", INTVAL(x));
+ sprintf(buf, "(CONST_INT:? %ld)", INTVAL(x));
+ zip_debug_print(pfx, lvl, buf);
+ } break;
+ case LABEL_REF:
+ zip_debug_print(pfx, lvl, "(LABEL)");
+ { char buf[256], *bp;
+ sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
+ zip_debug_print(pfx, lvl, buf);
+ }
+ break;
+ case SYMBOL_REF:
+ {
2083,12 → 2160,24
+ break;
+ case SUBREG:
+ { char buf[25];
+ sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
+ SUBREG_BYTE(x));
+ zip_debug_print(pfx, lvl, buf);
+ } break;
+ if (REG_P(XEXP(x,0))) {
+ sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
+ SUBREG_BYTE(x));
+ zip_debug_print(pfx, lvl, buf);
+ } else if (MEM_P(XEXP(x,0))) {
+ sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
+ zip_debug_print(pfx, lvl, buf);
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+ zip_debug_print(pfx, lvl, ")");
+ } else {
+ sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
+ zip_debug_print(pfx, lvl, buf);
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
+ zip_debug_print(pfx, lvl, ")");
+ }}
+ break;
+ default:
+ { char buf[25];
+ { char buf[128];
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
+ zip_debug_print(pfx, lvl, buf);
+ debug_rtx(x);
2123,55 → 2212,46
+
+
+static bool
+zip_legitimate_operand_address(const_rtx x, bool strict)
+zip_legitimate_opb(const_rtx x, bool strict)
+{
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS\n");
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
+ if (dbg) zip_debug_rtx_pfx("Test: ", x);
+
+ /*
+ * While this might seem to make sense, it sends GCC into an infinite
+ * loop.
+ *
+ if (GET_CODE(x) == MEM) {
+ return (zip_legitimate_operand_address(XEXP(x,0),strict));
+ }
+ */
+
+ /*
+ if (MEM_P(x)) {
+ if((REG_P(XEXP(x,0)))||(GET_CODE(XEXP(x,0))==PLUS))
+ return (zip_legitimate_operand_address(XEXP(x,0),strict));
+ } else
+ */
+
+ if (NULL_RTX == x)
+ return false;
+ else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode))
+ return false;
+ else if (REG_P(x)) {
+ bool res;
+ // Only insist the register b a valid register if strict is true
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (Reg)\n");
+ return (!strict)||(REGNO(x) != zip_CC);
+ res = (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) != zip_CC));
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> %s (Reg)\n",
+ (res)?"YES!":"No");
+ return res;
+ } else if ((!strict)&&(SUBREG_P(x))) {
+ // Only insist the register b a valid register if strict is true
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Subreg(Reg),recurse)\n");
+ return zip_legitimate_opb(XEXP(x,0), strict);
+ } else if ((CONST_INT_P(x))
+ &&(INTVAL(x) >= zip_min_opb_imm)
+ &&(INTVAL(x) <= zip_max_opb_imm)) {
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const)\n");
+ return true;
+ } else if (GET_CODE(x) == PLUS) {
+ // Is it a valid register?
+ /*
+ if (GET_CODE(XEXP(x,0))==PLUS) {
+ return (zip_legitimate_operand_address(XEXP(XEXP(x,0),0), strict))
+ &&(zip_const_address_operand(XEXP(XEXP(x,0),1)));
+ } */
+ if(!REG_P(XEXP(x,0))) {
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No (No reg in +%s)\n",
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+ return false;
+ } if ((strict)&&(REGNO(XEXP(x,0)) == zip_CC)) {
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+ } if ((strict)&&((!is_ZIP_REG(REGNO(XEXP(x,0))))||(REGNO(XEXP(x,0)) == zip_CC))) {
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+ return false;
+ } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
+ &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
+ &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (reg+int)\n");
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
+ // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
+ // gcc_unreachable();
+ return true;
2181,23 → 2261,24
+ // is that the symbol address could be anywhere, and we
+ // have no way of recovering if it's outside of our
+ // 14 allowable bits.
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No. (reg+lbl)\n");
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
+ return false;
+ } if ((GET_CODE(XEXP(x, 1)) == MINUS)
+ &&((GET_CODE(XEXP(XEXP(x,1),0)) == LABEL_REF)
+ ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
+ ||(GET_CODE(XEXP(XEXP(x,1),0)) == SYMBOL_REF))
+ &&((GET_CODE(XEXP(XEXP(x,1),1)) == LABEL_REF)
+ ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
+ ||(GET_CODE(XEXP(XEXP(x,1),1)) == SYMBOL_REF))
+ &&((GET_CODE(XEXP(XEXP(x,1),0)))
+ == (GET_CODE(XEXP(XEXP(x,1),1))))) {
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (lbl-lbl+reg)\n");
+ return true;
+ }
+ // if ((GET_CODE(XEXP(x, 1)) == MINUS)
+ // &&((GET_CODE(XEXP(XEXP(x,1),0)) == LABEL_REF)
+ // ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
+ // ||(GET_CODE(XEXP(XEXP(x,1),0)) == SYMBOL_REF))
+ // &&((GET_CODE(XEXP(XEXP(x,1),1)) == LABEL_REF)
+ // ||(GET_CODE(XEXP(XEXP(x,1),0)) == CONST_INT)
+ // ||(GET_CODE(XEXP(XEXP(x,1),1)) == SYMBOL_REF))
+ // &&((GET_CODE(XEXP(XEXP(x,1),0)))
+ // == (GET_CODE(XEXP(XEXP(x,1),1))))) {
+ // if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> YES! (lbl-lbl+reg)\n");
+ // return true;
+ //}
+ }
+
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPERAND-ADDRESS -> No\n");
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
+ if (dbg) zip_debug_rtx(x);
+ return false;
+}
2214,17 → 2295,20
+ else if (REG_P(x)) {
+ // Only insist the register b a valid register if strict is true
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> YES! (Reg)\n");
+ return (!strict)||(REGNO(x) != zip_CC);
+ return (!strict)||((is_ZIP_REG(REGNO(x)))&&(REGNO(x) !=zip_CC));
+ } else if (GET_CODE(x) == PLUS) {
+ // if (GET_CODE(XEXP(x,0))==PLUS) {
+ // return (zip_legitimate_opb(XEXP(x,0), strict))
+ // &&(zip_const_address_operand(XEXP(x,0)));
+ // }
+ // Is it a valid register?
+ if (GET_CODE(XEXP(x,0))==PLUS) {
+ return (zip_legitimate_operand_address(XEXP(x,0), strict))
+ &&(zip_const_address_operand(XEXP(x,0)));
+ } if(GET_CODE(XEXP(x,0)) != REG) {
+ if(GET_CODE(XEXP(x,0)) != REG) {
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (No reg in +%s)\n",
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
+ return false;
+ } if ((strict)&&(REGNO(XEXP(x,0)) == zip_CC)) {
+ } if ((strict)&&
+ ((!is_ZIP_REG(REGNO(XEXP(x,0))))
+ ||(REGNO(XEXP(x,0)) == zip_CC))) {
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> No (Wrong reg in +, %d)\n", REGNO(XEXP(x,0)));
+ return false;
+ } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
2250,21 → 2334,57
+}
+
+int
+zip_pd_mvimm_operand(rtx op)
+{
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
+ if (!CONST_INT_P(op))
+ return false;
+ if (INTVAL(op) > zip_max_mov_offset)
+ return false;
+ if (INTVAL(op) < zip_min_mov_offset)
+ return false;
+ return true;
+}
+
+int
+zip_pd_imm_operand(rtx op)
+{
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
+ if (!CONST_INT_P(op))
+ return false;
+ if (INTVAL(op) > zip_max_anchor_offset)
+ return false;
+ if (INTVAL(op) < zip_min_anchor_offset)
+ return false;
+ return true;
+}
+
+int
+zip_address_operand(rtx op)
+{
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
+ return zip_legitimate_operand_address(op, !can_create_pseudo_p());
+ if ((REG_P(op))&&(REGNO(op)==zip_CC))
+ return false;
+ else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
+ &&(REGNO(XEXP(op,0))==zip_CC))
+ return false;
+ else
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+
+int
+zip_pd_address_operand(rtx op)
+zip_pd_opb_operand(rtx op)
+{
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS(predicate) for OPERAND\n");
+ return zip_legitimate_operand_address(op, !can_create_pseudo_p());
+ if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+
+int
2273,7 → 2393,7
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
+ return zip_legitimate_operand_address(op, !can_create_pseudo_p());
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
+}
+
+int
2333,14 → 2453,35
+ if (dbg) zip_debug_rtx(x);
+
+ // Only insist the register be a valid register if strict is true
+ if (zip_legitimate_operand_address(x, strict))
+ if (zip_legitimate_opb(x, strict))
+ return true;
+ else if (zip_const_address_operand(x))
+ return true;
+ // else if (zip_const_address_operand(x))
+ // return true;
+
+ return false;
+}
+
+static rtx
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
+
+ if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
+ if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
+ return x;
+
+ if (GET_CODE(x)==PLUS) {
+ if (!REG_P(XEXP(x,0)))
+ XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
+ if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
+ &&(!CONST_INT_P(XEXP(x,1))))
+ x = force_reg(GET_MODE(x),x);
+ } else if (MEM_P(x))
+ x = force_reg(GET_MODE(x),x);
+
+ if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
+ return x;
+}
+
+void
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
+{
2392,7 → 2533,14
+}
+*/
+
+#define SREG_P(RTX) ((REG_P(RTX))||(SUBREG_P(RTX)))
+#define USE_SUBREG
+#ifdef USE_SUBREG
+#define SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
+#define SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
+#else
+#define SREG_P(RTX) false
+#define SMEM_P(RTX) false
+#endif
+
+bool zip_gen_move_rtl(rtx dst, rtx src) {
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2401,11 → 2549,15
+ if (dbg) zip_debug_rtx_pfx("FROM: ", src);
+ if (dbg) zip_debug_rtx_pfx("TO : ", dst);
+ if (dbg) fprintf(stderr, "PSEUDOs: %s\n", can_create_pseudo_p()?"true":"false");
+ if ((SREG_P(dst))&&(SREG_P(src))) {
+ if (((REG_P(dst))||(SREG_P(dst)))
+ &&((REG_P(src))||(SREG_P(src)))) {
+ // First type of move... register to register
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/REG -- EMIT\n");
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+ // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src));
+ emit_insn(gen_movsi_reg(dst, src));
+ } else if ((MEM_P(dst))&&(MEM_P(XEXP(dst,0)))) {
+ // An indirect store, (mem (mem (addr .))) = whatever ...
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(Pmode);
+ zip_gen_move_rtl(tmp, XEXP(dst,0));
2416,6 → 2568,7
+ return false;
+ }
+ } else if ((MEM_P(src))&&(MEM_P(XEXP(src,0)))) {
+ // If this is an indirect load, Rx = (mem (mem (addr)))
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(Pmode);
+ zip_gen_move_rtl(tmp, XEXP(src,0));
2425,9 → 2578,10
+ fprintf(stderr, "ZIP: Cannot move from mem(mem(ptr)) w/o pseudo\n");
+ return false;
+ }
+ } else if ((SREG_P(dst))&&(GET_CODE(src)==PLUS)
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src)==PLUS)
+ &&(REG_P(XEXP(src,0)))
+ &&(CONST_INT_P(XEXP(src,1)))) {
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+ // Second type of move... register plus offset to register
+ if ((INTVAL(XEXP(src, 1)) <= zip_max_mov_offset)
+ &&(INTVAL(XEXP(src, 1)) >= zip_min_mov_offset)) {
2460,17 → 2614,13
+ fprintf(stderr, "ZIP: Cannot move mem(A) to mem(B) w/o pseudo\n");
+ return false;
+ }
+ } else if ((SREG_P(dst))&&(MEM_P(src))) {
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(MEM_P(src))) {
+ // Memory load
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD\n");
+ if (zip_legitimate_operand_address(XEXP(src, 0), false)) {
+ if (zip_legitimate_opb(XEXP(src, 0), false)) {
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/SIMPLE-LOD(ADDR)\n");
+ if (dbg) zip_debug_rtx_pfx("Smple-Addr: ", src);
+ // if (REG_P(XEXP(src,0)))
+ // mark_reg_pointer(XEXP(src,0),0);
+ // else if ((GET_CODE(XEXP(src,0))==PLUS)
+ // &&(REG_P(XEXP(XEXP(src,0),0))))
+ // mark_reg_pointer(XEXP(XEXP(src,0),0),0);
+ emit_insn(gen_movsi_lod(dst, src));
+ } else if (zip_const_address_operand(XEXP(src,0))) {
+ if (can_create_pseudo_p()) {
2478,7 → 2628,6
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR)\n");
+ tmp = gen_reg_rtx(Pmode);
+ emit_insn(gen_movsi_ldi(tmp, XEXP(src,0)));
+ // mark_reg_pointer(tmp,0);
+ emit_insn(gen_movsi_lod(dst, gen_rtx_MEM(GET_MODE(src),tmp)));
+ } else {
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LOD(CONST-ADDR,SELF)\n");
2488,10 → 2637,11
+ } else {
+ internal_error("%s", "ZIP/No usable load\n");
+ }
+ } else if ((MEM_P(dst))&&(SREG_P(src))) {
+ } else if ((MEM_P(dst))&&((REG_P(src))||(SREG_P(src)))) {
+ // Memory store
+ // if (SREG_P(src)) src = gen_raw_REG(SImode,REGNO(XEXP(src,0))+SUBREG_BYTE(src));
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO\n");
+ if (zip_legitimate_operand_address(XEXP(dst, 0), false)) {
+ if (zip_legitimate_opb(XEXP(dst, 0), false)) {
+ // If it's a legitimate address already, do nothing mor
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/STO(Legit Addr)--EMIT\n");
+ // if (REG_P(XEXP(dst,0)))
2544,7 → 2694,8
+ fprintf(stderr, "ZIP/Cannot store constant into mem w/o pseudo\n");
+ return false;
+ }
+ } else if ((SREG_P(dst))&&(CONST_INT_P(src))) {
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(CONST_INT_P(src))) {
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+ // Load a constant into a register
+ // The assembler really takes care of all of this, since
+ // the assembler will split the constant if it doesn't fit
2563,6 → 2714,59
+ // into a single instruction.
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL->REG\n");
+ emit_insn(gen_movsi_ldi(dst, src));
+ } else if ((REG_P(dst))&&
+ ((GET_CODE(src)==PLUS)
+ &&((GET_CODE(XEXP(src,0))==SYMBOL_REF)
+ ||(GET_CODE(XEXP(src,0))==LABEL_REF))
+ &&(CONST_INT_P(XEXP(src,1))))) {
+ if (dbg) fprintf(stderr, "ZIP-GEN-MOVE/LABEL+OFFSET->REG\n");
+ if ((INTVAL(XEXP(src,1))>=zip_min_mov_offset)
+ &&(INTVAL(XEXP(src,1))<=zip_max_mov_offset)) {
+ emit_insn(gen_movsi_ldi(dst, XEXP(src,1)));
+ emit_insn(gen_movsi_reg_off(dst, dst, XEXP(src,1)));
+ } else if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(Pmode);
+ emit_insn(gen_movsi_ldi(tmp, XEXP(src,1)));
+ emit_insn(gen_movsi_ldi(dst, src));
+ emit_insn(gen_addsi3(dst,dst,tmp));
+ return true;
+ } else {
+ fprintf(stderr, "Cannot move LABEL+OFFSET -> dst w/o pseudo\n");
+ return false;
+ }
+ } else if (((REG_P(dst))||(SREG_P(dst)))&&(GET_CODE(src) == CONST)) {
+ // if (SREG_P(dst)) dst = gen_raw_REG(SImode,REGNO(XEXP(dst,0))+SUBREG_BYTE(dst));
+ zip_gen_move_rtl(dst, XEXP(src,0));
+ } else if (SMEM_P(dst)) {
+ rtx addr = XEXP(XEXP(dst,0),0);
+ if (REG_P(addr)) {
+ zip_gen_move_rtl(
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addr,
+ SUBREG_BYTE(dst),false)),src);
+ } else if ((GET_CODE(addr)==PLUS)
+ &&(REG_P(XEXP(addr,0)))
+ &&(CONST_INT_P(XEXP(addr,1)))) {
+ rtx addreg = XEXP(addr,0);
+ zip_gen_move_rtl(
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addreg,
+ INTVAL(XEXP(addr,1))+SUBREG_BYTE(dst),
+ false)),src);
+ } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n");
+ } else if (SMEM_P(src)) {
+ rtx addr = XEXP(XEXP(src,0),0);
+ if (REG_P(addr)) {
+ zip_gen_move_rtl(dst,
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addr,
+ SUBREG_BYTE(src),false)));
+ } else if ((GET_CODE(addr)==PLUS)
+ &&(REG_P(XEXP(addr,0)))
+ &&(CONST_INT_P(XEXP(addr,1)))) {
+ rtx addreg = XEXP(addr,0);
+ zip_gen_move_rtl(dst,
+ gen_rtx_MEM(SImode, plus_constant(Pmode,addreg,
+ INTVAL(XEXP(addr,1))+SUBREG_BYTE(src),
+ false)));
+ } else fprintf(stderr, "ZIP/Cannot understand SUBREG\n");
+ } else {
+ fprintf(stderr, "ZIP/No usable move\n");
+ zip_debug_rtx_pfx("TO : ", dst);
2683,7 → 2887,7
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
+ else if (zip_const_address_operand(iffalse))
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LDI", 3);
+ else if ((MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true)))
+ else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true)))
+ return zip_binary_movsicc(reverse_condition(GET_CODE(condition)), "LOD", 3);
+ else {
+ internal_error("MOVSICC Unsupported mode");
2697,7 → 2901,7
+ return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
+ else if (zip_const_address_operand(iffalse))
+ return zip_binary_movsicc(GET_CODE(condition), "LDI",2);
+ else if ((MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true)))
+ else if ((MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true)))
+ return zip_binary_movsicc(GET_CODE(condition), "LOD",2);
+ else {
+ internal_error("MOVSICC Unsupported mode");
2718,18 → 2922,28
+ return zip_tertiary_movsicc(condition, "MOV", "MOV");
+ }
+ if ((MEM_P(iftrue))
+ &&(zip_legitimate_operand_address(XEXP(iftrue,0), true))
+ &&(zip_legitimate_opb(XEXP(iftrue,0), true))
+ &&(zip_legitimate_move_operand_p(SImode, iffalse, true))) {
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C+D\n");
+ return zip_tertiary_movsicc(condition, "LOD", "MOV");
+ } if ((zip_legitimate_move_operand_p(SImode, iftrue, true))
+ &&(MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true))) {
+ &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) {
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A+B ELSE C[D]\n");
+ return zip_tertiary_movsicc(condition, "MOV", "LOD");
+ } if ((MEM_P(iftrue))&&(zip_legitimate_operand_address(XEXP(iftrue,0), true))
+ &&(MEM_P(iffalse))&&(zip_legitimate_operand_address(XEXP(iffalse,0), true))) {
+ } if ((MEM_P(iftrue))&&(zip_legitimate_opb(XEXP(iftrue,0), true))
+ &&(MEM_P(iffalse))&&(zip_legitimate_opb(XEXP(iffalse,0), true))) {
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE C[D]\n");
+ return zip_tertiary_movsicc(condition, "LOD", "LOD");
+ } if ((MEM_P(iftrue))
+ &&(zip_legitimate_opb(XEXP(iftrue,0),true))
+ &&(zip_const_address_operand(iffalse))) {
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) A[B] ELSE #x\n");
+ return zip_tertiary_movsicc(condition, "LOD", "LDI");
+ } if ((MEM_P(iffalse))
+ &&(zip_legitimate_opb(XEXP(iffalse,0),true))
+ &&(zip_const_address_operand(iftrue))) {
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- IF(X) #x ELSE A[B]\n");
+ return zip_tertiary_movsicc(condition, "LDI", "LOD");
+ }
+
+ internal_error("MOVSICC Operands not supported");
2781,54 → 2995,6
+ return "BREAK";
+}
+
+static void
+zip_canonicalize_comparison(int *code ATTRIBUTE_UNUSED, rtx *op0 ATTRIBUTE_UNUSED, rtx *op1 ATTRIBUTE_UNUSED, bool preserve_op0 ATTRIBUTE_UNUSED)
+{
+/*
+ * While I'd like to keep and have this code, it does absolutely nothing. The
+ * code apparently only gets called on non-CC0 targets.
+ *
+ *
+ const bool dbg = true;
+
+ if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
+ if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, cc0_rtx, const0_rtx));
+ if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
+ if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
+
+ if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
+ rtx tem = *op0;
+ *op0 = *op1;
+ *op1 = tem;
+ *code = (int)swap_condition((enum rtx_code)*code);
+ }
+
+ if ((*code == LE)||(*code == LEU)||(*code==GTU)) {
+ int offset = (*code == GTU) ? 1 : -1;
+ bool swap = false;
+ // A < B => A <= B-1
+ if (CONST_INT_P(*op1)) {
+ *op1 = GEN_INT(INTVAL(*op1)+offset);
+ swap = true;
+ } else if (REG_P(*op1)) {
+ *op1 = plus_constant(SImode, *op1, offset, true);
+ swap = true;
+ } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
+ *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
+ INTVAL(XEXP(*op1,1))+offset);
+ swap = true;
+ } if (swap) {
+ if (*code == LE)
+ (*code) = LT;
+ else if (*code == LEU)
+ (*code) = LTU;
+ else // (*code) == GTU
+ (*code) = GEU;
+ }
+ }
+*/
+}
+
+static int zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
+ int rv = 14;
+ if ((mode == DImode)||(mode == DFmode))
2840,8 → 3006,8
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-03-07 20:19:32.623843475 -0500
@@ -0,0 +1,3707 @@
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-03-19 12:03:33.888255495 -0400
@@ -0,0 +1,3889 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: gcc/config/zip/zip.h
2906,15 → 3072,6
+#define is_ZIP_GENERAL_REG(REGNO) ((REGNO)<13)
+#define is_ZIP_REG(REGNO) ((REGNO)<16)
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "_start"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC ""
+
+#undef LIB_SPEC
+#define LIB_SPEC "%{!g:-lc} %{g:-lg} -lzip"
+
+// #define zip_FP_PSEUDO 16
+#define zip_PC 15
+#define zip_CC 14
2927,12 → 3084,11
+
+#define ZIP_FIRST_ARG_REGNO 1
+#define ZIP_LAST_ARG_REGNO 5
+#define NUM_ARG_REGS 5
+#define MAX_PARM_REGS 5
+#define NUM_ARG_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+#define MAX_PARM_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
+
+/* The overall framework of an assembler file */
+
+#undef ASM_SPEC
+#define ASM_COMMENT_START ";"
+#define ASM_APP_ON ""
+#define ASM_APP_OFF ""
3056,6 → 3212,108
+ * (an RTX) is a legitimate memory address on the target machine for a memory
+ * operand of mode MODE.
+ */
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
+// DRIVER_SELF_SPECS
+// OPTION_DEFAULT_SPECS
+// CPP_SPEC
+// CPLUSPLUS_CPP_SPEC
+// CC1_SPEC
+// CC1PLUS_SPEC
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
+ * to pass to the assembler. It can also specify how to translate options you
+ * give to GCC into options for GCC to pass to the assembler. See the file
+ * 'sun3.h' for an example of this.
+ *
+ * Do not define thismacro if it does not need to do anything.
+ */
+// #undef ASM_SPEC
+// ASM_FINAL_SPEC
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
+
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
+ * to pass to the linker. It can also specify how to translate options you give
+ * to GCC into options for GCC to pass to the linker.
+ *
+ * Do not define this macro if it does not need to do anything.
+ */
+
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC. The
+ * difference between the two is that LIB_SPEC is used at the end of the
+ * command given to the linker.
+ *
+ * If this macro is not defined, a default is provided that loads the standard
+ * C library from the usual place. See 'gcc.c'.
+ */
+#undef LIB_SPEC
+// #define LIB_SPEC "%{!g:-lc} %{g:-lg} -lzip"
+#define LIB_SPEC ""
+
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
+ * line. This constant is placed both before and after the value of LIB_SPEC.
+ *
+ * If this macro is not defined, the GCC driver provides a default that passes
+ * the string '-lgcc' to the linker.
+ */
+#undef LIBGCC_SPEC
+#define LIBGCC_SPEC ""
+
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
+ * modified to refer to different versions of 'libgcc.a' depending on the
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
+ * and '-shared-libgcc'. On targets where these modifications are
+ * inappropriate, define REAL_LIBGCC_SPEC instead. REAL_LIBGCC_SPEC tells the
+ * driver how to place a reference to 'libgcc' on the link command line, but
+ * unlike LIBGCC_SPEC, it is used unmodified.
+ */
+#define REAL_LIBGCC_SPEC ""
+
+// USE_LD_AS_NEEDED
+// LINK_EH_SPEC
+
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC. The
+ * difference between the two is that STARTFILE_SPEC is used at the very
+ * beginning of the command given to the linker.
+ *
+ * If this macro is not defined, a default is provided that loads the standard
+ * C startup file from the usual place. See 'gcc.c'
+ */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC ""
+
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC. The
+ * difference between the two is that ENDFILE_SPEC is used at the very end
+ * of the command given to the linker.
+ *
+ * Do not define this macro if it does not do anything.
+ */
+// #undef ENDFILE_SPEC
+// #define ENDFILE_SPEC ""
+
+// THREAD_MODEL_SPEC
+// SYSROOT_SUFFIX_SPEC
+// SYSROOT_HEADERS_SUFFIX_SPEC
+// EXTRA_SPECS
+// LINK_LIBGCC_SPECIAL_1
+// LINK_GCC_C_SEQUENCE_SPEC
+// LINK_COMMAND_SPEC
+// TARGET_ALWAYS_STRIP_DOTDOT
+// MULTILIB_DEFAULTS
+// RELATIVE_PREFIX_NOT_LINKDIR
+// MD_EXEC_PREFIX
+// STANDARD_STARTFILE_PREFIX
+// STANDARD_STARTFILE_PREFIX_1
+// STANDARD_STARTFILE_PREFIX_2
+// MD_STARTFILE_PREFIX
+// MD_STARTFILE_PREFIX_1
+// INIT_ENVIRONMENT
+// LOCAL_INCLUDE_DIR
+#undef LOCAL_INCLUDE_DIR
+
+// NATIVE_SYSTEM_HEADER_COMPONENT
+// INCLUDE_DEFAULTS
+
+/* 17.03 Run-time Target Specification */
+
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
3801,8 → 4059,8
+ *
+ * Zip CPU does not support the base plus index addressing mode, thus ...
+ */
+#undef MODE_BASE_REG_REG_CLASS
+#define MODE_BASE_REG_REG_CLASS(MODE) NO_REGS
+// #undef MODE_BASE_REG_REG_CLASS
+// #define MODE_BASE_REG_REG_CLASS(MODE) NO_REGS
+
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
+ * which a valid index register must belong. An index register is one used in
3826,7 → 4084,7
+
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
+ * memory refgerence in MODE. You should define this macro if the mode of the
+ * memory reference in MODE. You should define this macro if the mode of the
+ * memory reference affects whether a register may be used as a base register.
+ *
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
3838,7 → 4096,7
+ * Use of this macro is deprecated.
+ */
+
+/* REGNO_MODE_CODE_OK_FRO_BASE_P(N,M,AS,OC,IC) ... A C expression which is
+/* REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) ... A C expression which is
+ * nonzero if a register number N is suitable for use as a base register in
+ * operand addresses, accessing memory in mode M in address space AS. This is
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
3851,7 → 4109,7
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
+ * num is suitable for use as an index register in opernad addressess. It may
+ * be either a suitable hard register or a pseudo register that has been
+ * allocated usch as a hard register.
+ * allocated such as a hard register.
+ *
+ * ZipCPU has no index registers, therefore we declare this to be zero.
+ */
3886,7 → 4144,7
+ * Sometimes returning a more restrictive class makes better code. For example,
+ * on the 68k, when x is an integer constant that is in range for a moveq
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
+ * includes the data registers. Requiring a Ddata register guarantees that a
+ * includes the data registers. Requiring a data register guarantees that a
+ * 'moveq' will be used.
+ *
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS. For
3940,7 → 4198,7
+ */
+
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
+ * priority number to which the register HARD_REGNO belongs to. THe bigger the
+ * priority number to which the register HARD_REGNO belongs to. The bigger the
+ * number
+ *
+ * The default version of this target hook returns always zero---good enough for
4906,11 → 5164,69
+
+/* 17.09.10 Caller-Saves Register Allocation */
+/* 17.09.11 Function Entry and Exit */
+// TARGET_ASM_FUNCTION_PROLOGUE
+// TARGET_ASM_FUNCTION_END_PROLOGUE
+// TARGET_ASM_FUNCCTION_BEGIN_EPILOGUE
+// TARGET_ASM_FUNCTION_EPILOGUE
+/* EXIT_IGNORE_STACK ... Define this macro as a C expression that is nonzero
+ * if the return instruction or the function epilogue ignores the value of the
+ * stack pointer; in other words, if it is safe to delete an instruction to
+ * adjust the stack pointer before a return from the function.
+ *
+ * The default is 0.
+ *
+ * Note that this macro's value is relevant only for functions for which frame
+ * pointers are maintained. It is never safe to delete a final stack adjustment
+ * in a function that has no frame pointer, and the compiler knows this
+ * regardless of EXIT_IGNORE_STACK.
+ *
+ * ZipCPU -- Thanks to the example of the m68k, and a careful selection of what
+ * our options otherwise could have been, our epilogue code does not use the
+ * stack register at all, but rather starts by moving the frame register into
+ * the stack register.
+ */
+#define EXIT_IGNORE_STACK 1
+// EPILOGUE_USES(regno)
+// EH_USES(regno)
+// TARGET_ASM_OUTPUT_MI_THUNK
+// TARGET_ASM_CAN_OUTPUT_MI_THUNK
+
+/* 17.09.12 Generating code for profiling */
+// FUNCTION_PROFILER
+// PROFILE_HOOK
+// NO_PROFILE_COUNTERS
+// PROFILE_BEFORE_PROLOGUE
+// TARGET_KEEP_LEAF_WHEN_PROFILED
+
+/* 17.09.13 Permitting tail calls*/
+
+/* TARGET_FUNCTION_OK_FOR_SIBCALL(DECL,EXP) ... True if it is OK to do sibling
+ * call optimizations for the specified call expression EXP. DECL will be the
+ * called function, or NULL if this is an indirect call.
+ *
+ * It is not uncommon for limitations of calling conventions to prevent tail
+ * calls to functions outside the current unit of translation, or during PIC
+ * compilation. The hook is used to enforce these restrictions, as the sibcall
+ * md pattern can not fail, or fall over to a 'normal' call. The criteria for
+ * successful sibling call optimization may vary greatly between different
+ * architectures.
+ *
+ * ?? What's a sibling call?
+ */
+
+// TARGET_EXTRA_LIVE_ON_ENTRY
+// TARGET_SET_UP_BY_PROLOGUE
+// TARGET_WARN_FUNC_RETURN
+
+/* 17.09.14 Stack smashing protection */
+// TARGET_STACK_PROTECT_GUARD
+// TARGET_STACK_PROTECT_FAIL
+// TARGET_SUPPORTS_SPLIT_STACK
+
+/* 17.09.15 Miscellaneous register hooks */
+
+// TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
+
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
+ * ZipCPU --- default is good enough for us.
+ */
5003,7 → 5319,7
+ */
+
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
+ * subroutine to do their work. THe macro should expand to a series of asm
+ * subroutine to do their work. The macro should expand to a series of asm
+ * statements which will be compiled with GCC. They go in a library function
+ * named __transfer_from_trampoline.
+ *
5126,14 → 5442,19
+// #undef CONSTANT_ADDRESS_P
+// #define CONSTANT_ADDRESS_P(X) (0)
+
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code, accepts integer values expressions whose values are not explicitly known, such as symbol_ref, label_ref, and high expressions and const arithmetic expressions, in addition to const_int and const_double expressions.
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code,
+ * accepts integer values expressions whose values are not explicitly known,
+ * such as symbol_ref, label_ref, and high expressions and const arithmetic
+ * expressions, in addition to const_int and const_double expressions.
+ *
+ * Huh???
+ */
+// #define CONSTANT_P(X) ???
+
+/* A number, the maximum number of registers that can appear in a valid memory
+ * address.
+/* MAX_REGS_PER_ADDRESS ... A number, the maximum number of registers that can
+ * appear in a valid memory address. Note that it is up to you to specify a
+ * value equal to the maximum number that TARGET_LEGITIMATE_ADDRESS_P would
+ * ever accept.
+ */
+#define MAX_REGS_PER_ADDRESS 1
+
5144,27 → 5465,6
+#undef TARGET_LEGITIMATE_ADDRESS_P
+#define TARGET_LEGITIMATE_ADDRESS_P zip_legitimate_address_p
+
+/* ECO32 suggested we do something like ... */
+#ifdef IGNORE_THIS_FOR_NOW
+#define TARGET_LEGITIMATE_ADDRESS_P(MODE,X,STRICT) \
+ do { \
+ if (GET_CODE(X) == PLUS) { \
+ rtx op1, op2; \
+ op1 = XEXP(X, 0); op2 = XEXP(X, 1); \
+ if ((GET_CODE(op1) == REG) \
+ &&(CONSTANT_ADDRESS_P(op2)) \
+ &&(REGNO_OK_FOR_BASE_P(REGNO(op1)))) \
+ goto LABEL; \
+ } if ((REG_P(X))&&(REGNO_OK_FOR_BASE_P(REGNO(X)))) \
+ goto LABEL; \
+ if ((GET_CODE(X) == SYMBOL_REF) \
+ ||(GET_CODE(X) == LABEL_REF) \
+ ||(GET_CODE(X) == CONST)) \
+ goto LABEL; \
+ } while(0)
+#endif
+
+
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
+ * default 'm' character for general memory addresses. This defines the
+ * constraint letter which matches the memory addresses accepted by
5193,10 → 5493,10
+ * break_out_memory_refs, and OLD will be the operand that was given to that
+ * function to produce RTX.
+ *
+ * ZipCPU -- this may be worth coming back to.
+ * ZipCPU --
+ */
+// #undef TARGET_LEGITIMIZE_ADDRESS
+// #define TARGET_LEGITIMIZE_ADDRESS zip_legitimize_address
+#undef TARGET_LEGITIMIZE_ADDRESS
+#define TARGET_LEGITIMIZE_ADDRESS zip_legitimize_address
+
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
+ * that attempts to replace X, which is an address that needs reloading, with
5219,7 → 5519,11
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
+#define TARGET_MODE_DEPENDENT_ADDRESS_P zip_mode_dependent_address_p
+
+/* TARGET_LEGITIMATE_CONSTANT_P
+/* TARGET_LEGITIMATE_CONSTANT_P(MODE,RTX) ... This hook returns true if x is a
+ * legitimate constant for a MODE-mode immediate operand on the target machine.
+ * You can assume the RTX satisfies CONSTANT_P, so you need not check this.
+ *
+ * The default definition returns true.
+ */
+
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
5233,6 → 5537,7
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
+ * MODE is the mode of X. The default version returns false.
+ */
+// #define TARGET_CANNOT_FORCE_CONST_MEM hook_bool_mode_rtx_false
+
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
+ * if pool entries for constant RTX can be placed in an object_block structure.
5417,7 → 5722,7
+#define TARGET_MEMORY_MOVE_COST zip_memory_move_cost
+
+// #warning "This needs to be double checked, and annotated"
+#define BRANCH_COST(SPEED,PREDICTABLE) ((SPEED)?2:5)
+#define BRANCH_COST(SPEED,PREDICTABLE) ((PREDICTABLE)?2:5)
+
+/* Define this macro as a C expression which is nonzero if accessing less than
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
5456,12 → 5761,20
+ */
+#define NO_FUNCTION_CSE
+
+/* TARGET_ADDRESS_COST ... This hook computes the cost of an addressing mode
+ * that contains address. If not defined, the cost is computed from the
+ * address expression and the TARGET_RTX_COST hook.
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
+ * the relative costs of RTL expressions.
+ *
+ * The cost may depend on the precise form of the expression, which is avaialble
+ * for examination in X, and the fact that X appears as operand OPNO of an
+ * expression with rtx code OUTER. That is, the hook can assume that there is
+ * some RTX Y such that GET_CODE(Y)==OUTER and such that either (a) XEXP(Y,OPNO)
+ * == X or (b) XVEC(Y,OPNO) contains X.
+ *
+ * ...
+ * The hook returns true when all subexpressions of x have been processed and
+ * false when rtx_cost should recurse.
+ */
+// We should define this for ZIP ... we're just not there yet
+// int TARGET_ADDRESS_COST(rtx address, machine_mode mode, addr_space_t as, bool speed)
+
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
+ * addressing mode that contains ADDR. If not defined, the cost is computed
+ * from the ADDR expression and the TARGET_RTX_COST hook. In cases where more
5693,6 → 6006,34
+
+/* 17.21 Controlling Debugging Information Format */
+/* 17.22 Cross Compilation and Floating Point */
+
+// REAL_VALUE_TYPE
+// REAL_VALUES_EQUAL
+// REAL_VALUES_LESS ... Tess whether x is less than y
+/* REAL_VALUE_FIX ... Truncates x to an unsigned integer, rouding toward zero.
+ * If x is negative, returns zero.
+ */
+// REAL_VALUE_ATOF
+// REAL_VALUE_NEGATIVE
+// REAL_VALUE_ISINF
+// REAL_VALUE_ISNAN
+/* REAL_ARITHMETIC(OUT,CODE,X,Y) ... (Macro) Calculates an arithmetic operation
+ * on two floating point values X and Y, storing the result in OUT (which must
+ * be a variable).
+ *
+ * The operation to be performed is specified by CODE. Only the following
+ * codes are supported: PLUS_EXPR, MINUS_EXPR, MULT_EXPR, RDIV_EXPR, MAX_EXPR,
+ * MIN_EXPR.
+ *
+ * If REAL_ARITHMETIC is asked to evaluate division by zero and the target's
+ * floating point format cannot represent infinity, it will call abort().
+ * Callers shoudl check for this situation first, using MODE_HAS_INFINITIES.
+ */
+/* REAL_VALUE_NEGATE(X) ... [Macro] Returns the negative of the floating point
+ * value X.
+ */
+/* REAL_VALUE_ABS(X) ... [Macro] Returns the absolute value of X.
+ */
+/* 17.23 Mode switching instructions */
+/* 17.24 Defining target-specific uses of __attribute__ */
+#undef TARGET_OPTION_OVERRIDE
6541,8 → 6882,15
+// extern void zip_print_operand_address(FILE *fp, rtx x);
+// extern bool zip_use_return_insn(void);
+
+#define UQQmode USQmode
+#define UHQmode USQmode
+#define UHAmode USAmode
+#define QQmode SQmode
+#define HQmode SQmode
+#define QImode SImode
+#define HImode SImode
+#define QAmode SAmode
+#define HAmode SAmode
+
+#include "insn-modes.h"
+#include "zip-protos.h"
6551,8 → 6899,8
+
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-03-07 18:21:44.060561458 -0500
@@ -0,0 +1,1736 @@
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-03-24 21:23:15.776993706 -0400
@@ -0,0 +1,1963 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Filename: zip.md
6594,11 → 6942,11
+;; 'O' -2^17 ... 2^17-1, or -131072 ... 131071 (OpB Immediate)
+;; 'R' 0...31 (Shift value)
+;; - Memory constraints
+;; 'Q' Op-B capable references to memory
+;; 'S' References to constant memory
+;; "Q" Op-B capable references to memory
+;; "S" References to constant memory
+;; - Address constraints
+;; 'P' Op-B capable references to memory
+;; 'T' Constant memory addresses
+;; "U" Op-B capable address that references to memory
+;; "T" Constant memory addresses
+(define_constraint "M"
+ "An 13-bit signed immediate such as a MOV instruction can handle"
+ (and (match_code "const_int")
6658,9 → 7006,21
+(define_predicate "zip_address_operand_p"
+ (match_code "reg,plus")
+{
+ return zip_pd_address_operand(op);
+ return zip_pd_opb_operand(op);
+})
+
+(define_predicate "zip_opb_operand_p"
+ (match_code "reg,plus,const_int")
+{
+ return zip_pd_opb_operand(op);
+})
+
+(define_predicate "zip_opb_single_operand_p"
+ (match_code "reg,const_int")
+{
+ return zip_pd_opb_operand(op);
+})
+
+(define_predicate "zip_mov_operand_p"
+ (match_code "reg,plus")
+{
6670,9 → 7030,39
+(define_predicate "zip_memory_operand_p"
+ (match_code "mem")
+{
+ return zip_pd_address_operand(XEXP(op,0));
+ return zip_pd_opb_operand(XEXP(op,0));
+})
+
+(define_predicate "zip_imm_operand_p"
+ (match_code "const_int")
+{
+ return zip_pd_imm_operand(op);
+})
+
+(define_predicate "zip_mvimm_operand_p"
+ (match_code "const_int")
+{
+ return zip_pd_mvimm_operand(op);
+})
+
+(define_predicate "zip_movdst_operand_p"
+ (match_code "mem,reg,subreg")
+{
+ if (MEM_P(op)) // Check for valid store address
+ return zip_pd_opb_operand(XEXP(op,0));
+ return 1;
+})
+
+(define_predicate "zip_movsrc_operand_p"
+ (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
+{
+ if (MEM_P(op))
+ return zip_pd_opb_operand(XEXP(op,0));
+ else if (GET_CODE(op)==PLUS)
+ return zip_pd_opb_operand(op);
+ return 1;
+})
+
+;; Constraints
+;
+(define_memory_constraint "S"
6750,15 → 7140,84
+;
+;
+(define_expand "mov<mode>"
+ [(set (match_operand:ZI 0 "nonimmediate_operand" "") ; =r,Q,r,r")
+ (match_operand:ZI 1 "general_operand" ""))] ; r,r,Q,i"))]
+ [(set (match_operand:ZI 0 "nonimmediate_operand" "")
+ (match_operand:ZI 1 "general_operand" ""))]
+ ""
+ {/* Everything except mem=const or mem=mem can be done easily */
+ if (zip_gen_move_rtl(operands[0], operands[1]))
+ DONE;
+ else internal_error("%s", "Zip/No usable movsi expansion\n");
+ {//; Everything except mem=const or mem=mem can be done easily
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
+ //; fprintf(stderr, "ZIP-GEN-MOVE\n");
+ //; zip_debug_rtx_pfx("FROM: ", operands[1]);
+ //; zip_debug_rtx_pfx("TO : ", operands[0]);
+
+ //; Need to load into a register between memory slots
+ if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
+ //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
+ emit_insn(gen_movsi(tmp,operands[1]));
+ operands[1] = tmp;
+ }
+ }
+
+ //; Op[0] has a bad address, need to legitimize it
+ if ((MEM_P(operands[0]))&&
+ ((zip_const_address_operand(XEXP(operands[0],0)))
+ ||(!zip_pd_opb_operand(XEXP(operands[0],0))))
+ )
+ {
+ //; fprintf(stderr, "GEN-MOVSI: Not to a MEM(REG)\n");
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(Pmode);
+ //; Load the address into a register
+ emit_insn(gen_movsi(tmp,XEXP(operands[0],0)));
+ XEXP(operands[0],0) = tmp;
+ mark_reg_pointer(tmp,1);
+ }
+ }
+ //; Op[1] is a constant. Need to load into a register before we can
+ //; place it into memory.
+ if ((MEM_P(operands[0]))&&
+ ((CONSTANT_P(operands[1]))
+ ||(CONST_INT_P(operands[1])))) {
+ //; fprintf(stderr, "GEN-MOVSI: CONST -> MEM\n");
+ //; zip_debug_rtx_pfx("MEM : ", operands[0]);
+ //; zip_debug_rtx_pfx("CONST: ", operands[1]);
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[0]));
+ emit_insn(gen_movsi(tmp,operands[1]));
+ operands[1] = tmp;
+ }
+ }
+ //; Op[1] has a bad address, need to legitimize it
+ if ((MEM_P(operands[1]))&&
+ //; (!REG_P(XEXP(operands[1],0)))
+ ((zip_const_address_operand(XEXP(operands[1],0)))
+ ||(!zip_pd_opb_operand(XEXP(operands[1],0))))
+ )
+ {
+ //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(Pmode);
+ emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
+ XEXP(operands[1],0) = tmp;
+ } else if (REG_P(operands[0])) { //; Can we steal Op[0]'s reg?
+ rtx tmp = operands[0];
+ emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
+ XEXP(operands[1],0) = tmp;
+ }
+ }
+ }
+ [(set_attr "ccresult" "unchanged")])
+(define_insn "movsi_raw"
+ [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
+ (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
+ "(REG_P(operands[0]))||(REG_P(operands[1]))"
+ "@
+ MOV\t%1,%0
+ STO\t%1,%0
+ LOD\t%1,%0
+ LDI\t%1,%0"
+ [(set_attr "ccresult" "unchanged")])
+(define_insn "mov<mode>_reg" ; Register to register move
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (match_operand:ZI 1 "register_operand" "r"))]
6768,7 → 7227,8
+(define_insn "mov<mode>_reg_off" ; Register to register move
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (plus:ZI (match_operand:ZI 1 "register_operand" "r")
+ (match_operand:ZI 2 "const_int_operand" "M")))]
+ (match_operand:ZI 2 "zip_mvimm_operand_p" "M")))
+ ]
+ ""
+ "MOV %2(%1),%0"
+ [(set_attr "ccresult" "unchanged")])
6790,35 → 7250,35
+ "")
+(define_insn "*movsi_lod"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (mem:SI (match_operand:SI 1 "register_operand" "r")))]
+ (match_operand:SI 1 "zip_memory_operand_p" ""))]
+ ""
+ "LOD\t%1,%0"
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_insn "*movsi_lod_off"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "const_int_operand" "N"))))]
+ ""
+ "LOD\t%2(%1),%0"
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+;(define_insn "*movsi_lod_off"
+ ;[(set (match_operand:SI 0 "register_operand" "=r")
+ ;(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
+ ;(match_operand:SI 2 "const_int_operand" "N"))))]
+ ;""
+ ;"LOD\t%2(%1),%0"
+ ;[(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_expand "mov<mode>_sto" ; Store into memory
+ [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
+ (match_operand:ZI 1 "register_operand" "r"))]
+ "")
+(define_insn "*movsi_sto"
+ [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
+ [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
+ (match_operand:SI 1 "register_operand" "r"))]
+ ""
+ "STO\t%1,(%0)"
+ "STO\t%1,%0"
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_insn "*movsi_sto_off"
+ [(set (mem:SI (plus:SI
+ (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "const_int_operand" "N")))
+ (match_operand:SI 2 "register_operand" "r"))]
+ ""
+ "STO\t%2,%1(%0)"
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+;(define_insn "*movsi_sto_off"
+ ;[(set (mem:SI (plus:SI
+ ;(match_operand:SI 0 "register_operand" "r")
+ ;(match_operand:SI 1 "const_int_operand" "N")))
+ ;(match_operand:SI 2 "register_operand" "r"))]
+ ;""
+ ;"STO\t%2,%1(%0)"
+ ;[(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
+(define_insn "mov<mode>_ldi" ; Load immediate
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (match_operand:ZI 1 "immediate_operand" "ipU"))]
6857,10 → 7317,14
+;
+;
+;
+(define_insn "add<mode>3" ; Fastest/best instruction always goes first
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+(define_insn "*addsi3_reg" ; Fastest/best instruction always goes first
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+ ]
+ ""
+ "ADD %2,%0"
6869,8 → 7333,7
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+ (match_operand:ZI 3 "const_int_operand" "N"))))
+ ]
+ (match_operand:ZI 3 "const_int_operand" "N"))))]
+ ""
+ "ADD %3+%2,%0"
+ [(set_attr "ccresult" "set")])
6880,12 → 7343,12
+(define_expand "sub<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "nonmemory_operand" "")))
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
+ ])
+(define_insn "*subsi3"
+(define_insn "sub<mode>3_reg"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
+ ]
+ ""
+ "SUB %2,%0"
6922,11 → 7385,16
+ ADD %3,%0"
+ [(set_attr "ccresult" "unknown")])
+
+(define_insn "div<mode>3"
+(define_expand "div<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]
+ "(ZIP_DIVIDE)")
+(define_insn "div<mode>3_reg"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+ ""
+ "(ZIP_DIVIDE)"
+ "DIVS %2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "div<mode>3_off"
6934,14 → 7402,19
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+ (match_operand:ZI 3 "const_int_operand" "N"))))]
+ ""
+ "(ZIP_DIVIDE)"
+ "DIVS %3+%2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "udiv<mode>3"
+(define_expand "udiv<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]
+ "(ZIP_DIVIDE)")
+(define_insn "udiv<mode>3_reg"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))]
+ ""
+ "(ZIP_DIVIDE)"
+ "DIVU %2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "udiv<mode>3_off"
6949,7 → 7422,7
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
+ (match_operand:ZI 3 "const_int_operand" "N"))))]
+ ""
+ "(ZIP_DIVIDE)"
+ "DIVU %3+%2,%0"
+ [(set_attr "ccresult" "set")])
+;;
6992,11 → 7465,14
+ "CMP %0,%2
+ MOV.LT %2,%0"
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "and<mode>3"
+(define_expand "and<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))
+ ]
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+(define_insn "and<mode>3_reg"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
+ (match_operand:ZI 2 "zip_opb_operand_p" "rO")))]
+ ""
+ "AND %2,%0"
+ [(set_attr "ccresult" "set")])
7009,9 → 7485,13
+ ""
+ "AND %3+%2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "ior<mode>3"
+(define_expand "ior<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+(define_insn "ior<mode>3_reg"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))
+ ]
+ ""
7026,9 → 7506,13
+ ""
+ "OR %3+%2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "xor<mode>3"
+(define_expand "xor<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
+(define_insn "xor<mode>3_reg"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
+ (match_operand:ZI 2 "nonmemory_operand" "rO")))
+ ]
+ ""
7078,6 → 7562,13
+ ""
+ "ASR %2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "ashl<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
+ (match_operand:ZI 2 "nonmemory_operand" "rR")))]
+ ""
+ "ASR %2,%0"
+ [(set_attr "ccresult" "set")])
+(define_insn "lshr<mode>3"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
7139,6 → 7630,55
+;
+;
+;
+(define_expand "movdi3"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (match_operand:DI 1 "general_operand" ""))])
+(define_insn "movdi_lod"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "r")))]
+ ""
+ {
+ if (REG_P(operands[0]))
+ return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
+ else if (GET_CODE(operands[0])==PLUS) {
+ if ((REG_P(XEXP(operands[0],0)))
+ &&(CONST_INT_P(XEXP(operands[0],1)))) {
+ static char buf[64];
+ sprintf(buf,
+ "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
+ INTVAL(XEXP(operands[0],1)),
+ INTVAL(XEXP(operands[0],1)+1));
+ return buf;
+ }
+ } else return "BREAK";
+ }
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "movdi_sto"
+ [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
+ (match_operand:DI 1 "register_operand" "r"))]
+ ""
+ {
+ if (REG_P(operands[0]))
+ return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
+ else if (GET_CODE(operands[0])==PLUS) {
+ if ((REG_P(XEXP(operands[0],0)))
+ &&(CONST_INT_P(XEXP(operands[0],1)))) {
+ static char buf[64];
+ sprintf(buf,
+ "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
+ INTVAL(XEXP(operands[0],1)),
+ INTVAL(XEXP(operands[0],1)+1));
+ return buf;
+ }
+ } else return "BREAK";
+ }
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "movdi_ldi"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operand:DI 1 "immediate_operand" "i"))]
+ ""
+ "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
+(define_insn "adddi3" ; Fastest/best instruction always goes first
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (plus:DI (match_operand:DI 1 "register_operand" "0")
7623,7 → 8163,7
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+ gen_rtx_COMPARE(VOIDmode, operands[1],
+ GEN_INT(INTVAL(operands[2])+1))));
+ emit_insn(gen_cbranch_jmp_lt(operands[3]));
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
+ DONE;
+ } else if ((GET_CODE(operands[0])==LEU)
+ &&(CONST_INT_P(operands[2]))
7632,7 → 8172,7
+ emit_insn(gen_rtx_SET(VOIDmode, cc0_rtx,
+ gen_rtx_COMPARE(VOIDmode, operands[1],
+ GEN_INT(INTVAL(operands[2])+1))));
+ emit_insn(gen_cbranch_jmp_ltu(operands[3]));
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
+ DONE;
+ }
+ })
7842,21 → 8382,14
+;
+(define_insn "void_call_const"
+ [(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+ (match_operand 1 "" ""))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (reg:SI RTN_REG))])]
+ ""
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;(define_insn "void_call_label"
+; [(parallel [(call (mem:SI (label_ref (match_operand 0 "" "")))
+; (match_operand 1 "" ""))
+; (clobber (reg:SI RTN_REG))])]
+; ""
+; "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "void_call_mem"
+ [(parallel [(call (mem:SI (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")))
+ (match_operand 1 "" ""))
+ [(parallel [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (reg:SI RTN_REG))])]
+ ""
+ "MOV .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
7865,19 → 8398,15
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+(define_insn "void_call_var"
+ [(parallel [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+ (match_operand 1 "" ""))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (reg:SI RTN_REG))])]
+ ""
+ "MOV .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+ ; emit_move_insn(??)
+ ; emit_jump(where);
+ ; emit_label(return_address);
+ ;
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_expand "call_value"
+ [(set (reg:SI RTNV_REG)
+ (call (match_operand:SI 1 "" "")
+ (match_operand 2 "" "")))
+ (match_operand 2 "const_int_operand" "n")))
+ (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))]
+ ""
+ {
7905,35 → 8434,28
+(define_insn "reg_call_const"
+ [(parallel [(set (reg:SI RTNV_REG)
+ (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
+ (match_operand 1 "" "")))
+ (match_operand 1 "const_int_operand" "n")))
+ (clobber (reg:SI RTN_REG))])]
+ ""
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;(define_insn "reg_call_label"
+; [(parallel [(set (reg:SI RTNV_REG)
+; (call (mem:SI (match_operand 0 "" ""))
+; (match_operand 1 "" "")))
+; (clobber (reg:SI RTN_REG))])]
+; ""
+; "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+(define_insn "reg_call_mem"
+ [(set (reg:SI RTNV_REG)
+ (call (mem:SI (mem:SI (match_operand:SI 0 "zip_address_operand_p" "")))
+ (match_operand 1 "" "")))
+ (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
+ (match_operand 1 "const_int_operand" "n")))
+ (clobber (reg:SI RTN_REG))]
+ ""
+ "MOV .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:" ; emit_label(return_lbl);
+ "MOV .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
+(define_insn "reg_call_var"
+ [(parallel [(set (reg:SI RTNV_REG)
+ (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
+ (match_operand 1 "" "")))
+ (match_operand 1 "const_int_operand" "n")))
+ (clobber (reg:SI RTN_REG))])]
+ ""
+ "MOV .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
+ "MOV .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
+;
+;
8112,6 → 8634,20
+ ""
+ "MOV\tCC,%0"
+ [(set_attr "ccresult" "unchanged")])
+(define_insn "zip_cc_sto"
+ [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
+ (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
+ ""
+ "STO\tCC,(%0)"
+ [(set_attr "ccresult" "unchanged")])
+(define_insn "zip_cc_sto_off"
+ [(set (mem:SI (plus:SI
+ (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "const_int_operand" "N")))
+ (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
+ ""
+ "STO\tCC,%1(%0)"
+ [(set_attr "ccresult" "unchanged")])
+(define_insn "ldilo"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
8158,7 → 8694,46
+ "(ZIP_FPU)"
+ "FPDIV %2,%0"
+ [(set_attr "ccresult" "unknown")])
+
+(define_expand "negsf2"
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (neg:SF (match_operand:SF 1 "register_operand" "0")))
+ ]
+ ""
+ {
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(SImode);
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
+ emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_XOR(SImode, operands[0], tmp)));
+ DONE;
+ } else {
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+ emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_IOR(SImode, operands[0],gen_int_mode(1,SImode))));
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+ DONE;
+ }
+ })
+(define_expand "abssf2"
+ [(set (match_operand:ZI 0 "register_operand" "=r")
+ (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
+ ]
+ ""
+ {
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
+ if (can_create_pseudo_p()) {
+ rtx tmp = gen_reg_rtx(SImode);
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
+ emit_insn(gen_rtx_SET(SImode, operands[0], gen_rtx_AND(SImode, operands[0], tmp)));
+ DONE;
+ } else {
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+ emit_insn(gen_rtx_SET(SImode, operands[0],
+ gen_rtx_AND(SImode, operands[0],
+ gen_int_mode(-2,SImode))));
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
+ DONE;
+ }
+ })
+;
+;
+;
8291,8 → 8866,8
+; pattern
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def 1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def 2016-03-04 17:13:26.438204784 -0500
@@ -0,0 +1,21 @@
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def 2016-03-08 12:10:21.982586940 -0500
@@ -0,0 +1,23 @@
+/*
+ * Commends in C-long comment form
+ * class
8300,6 → 8875,8
+ * PRECISION, BYTESIZE, COUNT ??
+ * FORMAT
+ * EXPR
+ *
+ * The manual says I need to define BITS_PER_UNIT here.
+ */
+// INT_MODE(QI, 1);
+// INT_MODE(HI, 1);
8316,8 → 8893,8
+// config directory.
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-03-02 10:35:53.661426308 -0500
@@ -0,0 +1,69 @@
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-03-12 17:39:02.331344108 -0500
@@ -0,0 +1,70 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: zip-protos.h
8377,13 → 8954,14
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+
+extern int zip_ct_address_operand(rtx op);
+extern int zip_pd_address_operand(rtx op);
+extern int zip_pd_opb_operand(rtx op);
+extern int zip_pd_mov_operand(rtx op);
+extern int zip_pd_imm_operand(rtx op);
+extern int zip_pd_mvimm_operand(rtx op);
+extern int zip_ct_const_address_operand(rtx op);
+extern int zip_pd_const_address_operand(rtx op);
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
+// extern void zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
+
+#endif
+
8419,11 → 8997,12
exit 1
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
--- gcc-5.3.0-original/gcc/cse.c 2015-02-03 15:41:38.000000000 -0500
+++ gcc-5.3.0-zip/gcc/cse.c 2016-03-05 20:34:50.226907590 -0500
@@ -634,6 +634,14 @@
+++ gcc-5.3.0-zip/gcc/cse.c 2016-03-19 12:28:45.584701098 -0400
@@ -634,6 +634,15 @@
/* Nonzero if X has the form (PLUS frame-pointer integer). */
+// #define DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#include <stdio.h>
+extern void zip_debug_rtx(const_rtx);
8435,14 → 9014,6
static bool
fixed_base_plus_p (rtx x)
{
@@ -2843,6 +2851,7 @@
enum rtx_code code;
const char *fmt;
+ ZIP_DEBUG_LINE("CANON-REG", insn);
if (x == 0)
return x;
@@ -2898,6 +2907,7 @@
validate_canon_reg (&XVECEXP (x, i, j), insn);
}
8777,6 → 9348,33
rtx
expand_expr_real (tree exp, rtx target, machine_mode tmode,
enum expand_modifier modifier, rtx *alt_rtl,
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/final.c 2016-03-24 22:12:00.263845620 -0400
@@ -109,6 +109,14 @@
#include "wide-int-print.h"
#include "rtl-iter.h"
+
+#ifdef DO_ZIP_DEBUGS
+extern void zip_debug_rtx(const_rtx);
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
+#else
+#define ZIP_DEBUG_LINE(STR,RTX)
+#endif
+
#ifdef XCOFF_DEBUGGING_INFO
#include "xcoffout.h" /* Needed for external data
declarations for e.g. AIX 4.x. */
@@ -2071,6 +2079,8 @@
/* Output the insns. */
for (insn = first; insn;)
{
+ ZIP_DEBUG_LINE("final()\n", insn);
+
if (HAVE_ATTR_length)
{
if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
--- gcc-5.3.0-original/gcc/genmodes.c 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/genmodes.c 2016-03-04 21:27:49.669147699 -0500
8861,7 → 9459,7
}
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
+++ gcc-5.3.0-zip/gcc/machmode.def 2016-03-04 22:47:59.406632941 -0500
+++ gcc-5.3.0-zip/gcc/machmode.def 2016-03-08 11:56:45.375491523 -0500
@@ -184,11 +184,11 @@
larger types, then corresponding modes must be added here. The
name OI is reserved for a 256-bit type (needed by some back ends).
8879,7 → 9477,7
/* No partial integer modes are defined by default. */
@@ -206,8 +206,8 @@
@@ -206,35 +206,35 @@
These are the IEEE mappings. They can be overridden with
RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE). */
8890,31 → 9488,54
/* Basic CC modes.
FIXME define this only for targets that need it. */
@@ -215,16 +215,16 @@
CC_MODE (CC);
/* Fixed-point modes. */
FRACT_MODE (QQ, 1, 7); /* s.7 */
-FRACT_MODE (QQ, 1, 7); /* s.7 */
-FRACT_MODE (HQ, 2, 15); /* s.15 */
-FRACT_MODE (SQ, 4, 31); /* s.31 */
-FRACT_MODE (DQ, 8, 63); /* s.63 */
-FRACT_MODE (TQ, 16, 127); /* s.127 */
+FRACT_MODE (HQ, 1, 15); /* s.15 */
+FRACT_MODE (SQ, 1, 31); /* s.31 */
+FRACT_MODE (DQ, 2, 63); /* s.63 */
+FRACT_MODE (TQ, 4, 127); /* s.127 */
UFRACT_MODE (UQQ, 1, 8); /* .8 */
-
-UFRACT_MODE (UQQ, 1, 8); /* .8 */
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
-UFRACT_MODE (USQ, 4, 32); /* .32 */
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
+UFRACT_MODE (UHQ, 1, 16); /* .16 */
-
-ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
-ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
-ACCUM_MODE (DA, 8, 32, 31); /* s32.31 */
-ACCUM_MODE (TA, 16, 64, 63); /* s64.63 */
-
-UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
-UACCUM_MODE (USA, 4, 16, 16); /* 16.16 */
-UACCUM_MODE (UDA, 8, 32, 32); /* 32.32 */
-UACCUM_MODE (UTA, 16, 64, 64); /* 64.64 */
+/* FRACT_MODE (QQ, 1, 7); /* s.7 */
+/* FRACT_MODE (HQ, 1, 15); /* s.15 */
+FRACT_MODE (SQ, 1, 31); /* s.31 */
+FRACT_MODE (DQ, 2, 63); /* s.63 */
+FRACT_MODE (TQ, 4, 127); /* s.127 */
+
+/* UFRACT_MODE (UQQ, 1, 8); /* .8 */
+/* UFRACT_MODE (UHQ, 1, 16); /* .16 */
+UFRACT_MODE (USQ, 1, 32); /* .32 */
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
+
+/* ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
+ACCUM_MODE (SA, 1, 16, 15); /* s16.15 */
+ACCUM_MODE (DA, 2, 32, 31); /* s32.31 */
+ACCUM_MODE (TA, 4, 64, 63); /* s64.63 */
+
+/* UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
+UACCUM_MODE (USA, 1, 16, 16); /* 16.16 */
+UACCUM_MODE (UDA, 2, 32, 32); /* 32.32 */
+UACCUM_MODE (UTA, 4, 64, 64); /* 64.64 */
ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
/* Allow the target to specify additional modes of various kinds. */
#if HAVE_EXTRA_MODES
@@ -246,9 +246,9 @@
COMPLEX_MODES (FLOAT);
8980,11 → 9601,12
if (type == long_integer_type_node)
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
+++ gcc-5.3.0-zip/gcc/postreload.c 2016-03-07 18:24:22.263499116 -0500
@@ -71,6 +71,13 @@
+++ gcc-5.3.0-zip/gcc/postreload.c 2016-03-24 21:30:23.402590035 -0400
@@ -71,6 +71,14 @@
#include "df.h"
#include "dbgcnt.h"
+// #define DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+extern void zip_debug_rtx(const_rtx);
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
8995,7 → 9617,7
static int reload_cse_noop_set_p (rtx);
static bool reload_cse_simplify (rtx_insn *, rtx);
static void reload_cse_regs_1 (void);
@@ -120,6 +127,8 @@
@@ -120,6 +128,8 @@
basic_block insn_bb = BLOCK_FOR_INSN (insn);
unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
9004,7 → 9626,7
if (GET_CODE (body) == SET)
{
int count = 0;
@@ -147,6 +156,7 @@
@@ -147,6 +157,7 @@
apply_change_group ();
else
reload_cse_simplify_operands (insn, testreg);
9012,7 → 9634,7
}
else if (GET_CODE (body) == PARALLEL)
{
@@ -205,6 +215,7 @@
@@ -205,6 +216,7 @@
apply_change_group ();
else
reload_cse_simplify_operands (insn, testreg);
9020,7 → 9642,7
}
done:
@@ -246,6 +257,7 @@
@@ -246,6 +258,7 @@
cfg_changed |= reload_cse_simplify (insn, testreg);
cselib_process_insn (insn);
9028,7 → 9650,7
}
/* Clean up. */
@@ -276,6 +288,8 @@
@@ -276,6 +289,8 @@
#endif
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
9037,7 → 9659,7
dreg = true_regnum (SET_DEST (set));
if (dreg < 0)
return 0;
@@ -427,6 +441,7 @@
@@ -427,6 +442,7 @@
/* Array of alternatives, sorted in order of decreasing desirability. */
int *alternative_order;
9045,7 → 9667,7
extract_constrain_insn (insn);
if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
@@ -519,6 +534,7 @@
@@ -519,6 +535,7 @@
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
}
9053,7 → 9675,7
alternative_mask preferred = get_preferred_alternatives (insn);
for (i = 0; i < recog_data.n_operands; i++)
{
@@ -617,6 +633,7 @@
@@ -617,6 +634,7 @@
}
}
}
9061,7 → 9683,7
/* Record all alternatives which are better or equal to the currently
matching one in the alternative_order array. */
@@ -666,6 +683,7 @@
@@ -666,6 +684,7 @@
validate_change (insn, recog_data.operand_loc[i],
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
}
9069,7 → 9691,7
for (i = recog_data.n_dups - 1; i >= 0; i--)
{
@@ -679,6 +697,7 @@
@@ -679,6 +698,7 @@
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
}
9079,8 → 9701,16
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-03-07 18:25:12.311162959 -0500
@@ -2271,11 +2271,11 @@
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-03-19 12:27:20.657324554 -0400
@@ -785,6 +785,7 @@
stream and a DCE pass should be run to elimiante them. Else the
return value is FALSE. */
+extern void zip_debug_rtx(const_rtx);
bool
reload (rtx_insn *first, int global)
{
@@ -2271,11 +2272,11 @@
&& spill_stack_slot_width[from_reg] >= total_size
&& (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
>= inherent_size)
9094,7 → 9724,7
{
/* Compute maximum size needed, both for inherent size
and for total size. */
@@ -3477,11 +3477,14 @@
@@ -3477,11 +3478,14 @@
/* Eliminate all eliminable registers occurring in operands that
can be handled by reload. */
extract_insn (insn);
9111,7 → 9741,7
{
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
--- gcc-5.3.0-original/gcc/reload.c 2015-01-15 08:28:42.000000000 -0500
+++ gcc-5.3.0-zip/gcc/reload.c 2016-02-19 08:15:17.546189655 -0500
+++ gcc-5.3.0-zip/gcc/reload.c 2016-03-19 12:28:30.592811127 -0400
@@ -2707,8 +2707,17 @@
no_output_reloads = 1;
9244,7 → 9874,7
}
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
--- gcc-5.3.0-original/gcc/var-tracking.c 2015-03-26 09:19:00.000000000 -0400
+++ gcc-5.3.0-zip/gcc/var-tracking.c 2016-03-05 20:43:22.535221161 -0500
+++ gcc-5.3.0-zip/gcc/var-tracking.c 2016-03-19 09:31:12.636242911 -0400
@@ -143,6 +143,13 @@
#include "rtl-iter.h"
#include "fibonacci_heap.h"
/sw/binutils-2.25.patch
1379,7 → 1379,7
}
diff -Naur '--exclude=*.swp' binutils-2.25-original/bfd/elflink.c binutils-2.25/bfd/elflink.c
--- binutils-2.25-original/bfd/elflink.c 2014-12-23 03:47:10.000000000 -0500
+++ binutils-2.25/bfd/elflink.c 2016-02-21 19:46:05.351518604 -0500
+++ binutils-2.25/bfd/elflink.c 2016-03-10 09:53:38.011710873 -0500
@@ -1348,7 +1348,7 @@
return FALSE;
1557,9 → 1557,9
{
if (strncmp (".end", name + len, 4) == 0)
{
+ // TODO: Octets per byte -- needs to adjust the calling
+ // convention, though, so that the BFD in question is available
+ // or otherwise so that we know the number of octets per byte.
+ // TODO: Octets per byte -- needs to adjust the calling
+ // convention, though, so that the BFD in question is available
+ // or otherwise so that we know the number of octets per byte.
+ // *result = curr->vma + curr->size / bfd_octets_per_byte(abfd);
*result = curr->vma + curr->size;
return TRUE;
1594,50 → 1594,44
if (size != dynamic_relocs->size)
return 0;
@@ -8290,6 +8295,7 @@
@@ -8289,8 +8294,11 @@
}
erel = o->contents;
erelend = o->contents + o->size;
/* FIXME: octets_per_byte. */
+fprintf(stderr, "INVALID-OCTETS-PER-BYTE-CODE - C\n");
p = sort + o->output_offset / ext_size * sort_elt;
- /* FIXME: octets_per_byte. */
- p = sort + o->output_offset / ext_size * sort_elt;
+ // output_offset is in bytes, not octets
+ // ext_size is the size of the relocation (file octets)
+ // sort_elt is in octets
+ // sort and p are both pointers to octets
+ p = sort + o->output_offset * bfd_octets_per_byte(abfd) / ext_size * sort_elt;
while (erel < erelend)
@@ -8335,6 +8341,7 @@
{
@@ -8334,8 +8342,11 @@
erel = o->contents;
erelend = o->contents + o->size;
/* FIXME: octets_per_byte. */
+fprintf(stderr, "INVALID-OCTETS-PER-BYTE-CODE - D\n");
p = sort + o->output_offset / ext_size * sort_elt;
- /* FIXME: octets_per_byte. */
- p = sort + o->output_offset / ext_size * sort_elt;
+ // output_offset is in bytes, not octets
+ // ext_size is the size of the relocation (file octets)
+ // sort_elt is in octets
+ // sort and p are both pointers to octets
+ p = sort + o->output_offset * bfd_octets_per_byte(abfd) / ext_size * sort_elt;
while (erel < erelend)
{
@@ -8439,7 +8446,7 @@
destshndx += bfd_get_symcount (flinfo->output_bfd);
}
- bed->s->swap_symbol_out (flinfo->output_bfd, elfsym, dest, destshndx);
+ bed->s->swap_symbol_out (flinfo->output_bfd, elfsym, dest, destshndx); //
flinfo->symbuf_count += 1;
bfd_get_symcount (flinfo->output_bfd) += 1;
@@ -9215,7 +9222,7 @@
struct elf_link_sort_rela *s = (struct elf_link_sort_rela *) p;
@@ -9215,7 +9226,7 @@
asection *o;
const struct elf_backend_data *bed;
struct elf_link_hash_entry **sym_hashes;
- bfd_size_type address_size;
+ bfd_size_type address_size_in_octets;
+ bfd_size_type address_size; // Octets
bfd_vma r_type_mask;
int r_sym_shift;
bfd_boolean have_file_sym = FALSE;
@@ -9246,7 +9253,7 @@
isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
if (isymbuf == NULL && locsymcount != 0)
{
- isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,
+ isymbuf = bfd_elf_get_elf_syms (input_bfd, symtab_hdr, locsymcount, 0,//
flinfo->internal_syms,
flinfo->external_syms,
flinfo->locsym_shndx);
@@ -9392,15 +9399,15 @@
@@ -9392,15 +9403,15 @@
we assume that they also have a reasonable value for
output_section. Any special sections must be set up to meet
these requirements. */
1656,12 → 1650,12
}
}
@@ -9416,13 +9423,13 @@
@@ -9416,13 +9427,13 @@
{
r_type_mask = 0xff;
r_sym_shift = 8;
- address_size = 4;
+ address_size_in_octets = 4;
+ address_size = 4; // Octets
}
else
{
1668,11 → 1662,11
r_type_mask = 0xffffffff;
r_sym_shift = 32;
- address_size = 8;
+ address_size_in_octets = 8;
+ address_size = 8; // Octets
}
/* Relocate the contents of each section. */
@@ -9485,7 +9492,7 @@
@@ -9485,7 +9496,7 @@
if (sym.st_shndx == SHN_BAD)
return FALSE;
1681,25 → 1675,16
indx = bfd_get_symcount (output_bfd);
ret = elf_link_output_sym (flinfo, name, &sym, o, NULL);
@@ -9551,7 +9558,7 @@
/* We need to reverse-copy input .ctors/.dtors sections if
they are placed in .init_array/.finit_array for output. */
- if (o->size > address_size
+ if (o->size > address_size_in_octets
&& ((strncmp (o->name, ".ctors", 6) == 0
&& strcmp (o->output_section->name,
".init_array") == 0)
@@ -9560,7 +9567,7 @@
@@ -9560,7 +9571,7 @@
".fini_array") == 0))
&& (o->name[6] == 0 || o->name[6] == '.'))
{
- if (o->size != o->reloc_count * address_size)
+ if (o->size != o->reloc_count * address_size_in_octets)
+ if (o->size != o->reloc_count * address_size) // Octets
{
(*_bfd_error_handler)
(_("error: %B: size of section %A is not "
@@ -9644,7 +9651,7 @@
@@ -9644,7 +9655,7 @@
&& !flinfo->info->relocatable)
{
bfd_vma val;
1708,7 → 1693,7
+ o->output_offset + o->output_section->vma);
#ifdef DEBUG
printf ("Encountered a complex symbol!");
@@ -9655,7 +9662,7 @@
@@ -9655,7 +9666,7 @@
r_symndx, sym_name);
printf (" reloc : info %8.8lx, addr %8.8lx\n",
(unsigned long) rel->r_info,
1717,7 → 1702,7
#endif
if (!eval_symbol (&val, &sym_name, input_bfd, flinfo, dot,
isymbuf, locsymcount, s_type == STT_SRELC))
@@ -9761,9 +9768,9 @@
@@ -9761,9 +9772,9 @@
* bed->s->int_rels_per_ext_rel);
rel_hash_list = rel_hash;
rela_hash_list = NULL;
1729,7 → 1714,7
for (next_erel = 0; irela < irelaend; irela++, next_erel++)
{
unsigned long r_symndx;
@@ -9793,19 +9800,19 @@
@@ -9793,19 +9804,19 @@
offset as the last reloc. elf_eh_frame.c and
bfd_elf_discard_info rely on reloc offsets
being ordered. */
1753,7 → 1738,7
r_symndx = irela->r_info >> r_sym_shift;
if (r_symndx == STN_UNDEF)
@@ -9875,7 +9882,7 @@
@@ -9875,7 +9886,7 @@
&& sec->kept_section->output_section != NULL)
{
osec = sec->kept_section->output_section;
1762,7 → 1747,7
}
if (!bfd_is_abs_section (osec))
@@ -9883,10 +9890,10 @@
@@ -9883,10 +9894,10 @@
r_symndx = osec->target_index;
if (r_symndx == STN_UNDEF)
{
1775,7 → 1760,7
r_symndx = osec->target_index;
}
}
@@ -9895,7 +9902,7 @@
@@ -9895,7 +9906,7 @@
/* Adjust the addend according to where the
section winds up in the output section. */
if (rela_normal)
1784,7 → 1769,7
}
else
{
@@ -9929,10 +9936,10 @@
@@ -9929,10 +9940,10 @@
if (sym.st_shndx == SHN_BAD)
return FALSE;
1797,7 → 1782,7
if (ELF_ST_TYPE (sym.st_info) == STT_TLS)
{
/* STT_TLS symbols are relative to PT_TLS
@@ -10018,33 +10025,32 @@
@@ -10018,33 +10029,32 @@
break;
default:
{
1814,21 → 1799,20
do
{
- todo -= address_size;
+ todo_octets -= address_size_in_octets;
+ todo_octets -= address_size;
if (! bfd_set_section_contents (output_bfd,
o->output_section,
- contents + todo,
- offset,
- address_size))
+ contents + todo_octets,
+ offset_octets,
+ address_size_in_octets))
address_size))
return FALSE;
- if (todo == 0)
+ if (todo_octets == 0)
break;
- offset += address_size;
+ offset_octets += address_size_in_octets;
+ offset_octets += address_size;
}
while (1);
}
1840,7 → 1824,7
return FALSE;
}
}
@@ -10086,7 +10092,7 @@
@@ -10086,7 +10096,7 @@
return FALSE;
}
1849,7 → 1833,7
if (esdo->rel.hdr)
reldata = &esdo->rel;
@@ -10128,7 +10134,7 @@
@@ -10128,7 +10138,7 @@
/* It seems that we ought to add the symbol value to the
addend here, but in practice it has already been added
because it was passed to constructor_callback. */
1858,7 → 1842,7
}
else if (h != NULL)
{
@@ -10187,7 +10193,9 @@
@@ -10187,7 +10197,9 @@
break;
}
ok = bfd_set_section_contents (output_bfd, output_section, buf,
1869,7 → 1853,7
free (buf);
if (! ok)
return FALSE;
@@ -10196,13 +10204,13 @@
@@ -10196,13 +10208,13 @@
/* The address of a reloc is relative to the section in a
relocatable file, and is a virtual address in an executable
file. */
1886,7 → 1870,7
irel[i].r_info = 0;
irel[i].r_addend = 0;
}
@@ -10220,7 +10228,7 @@
@@ -10220,7 +10232,7 @@
}
else
{
1895,7 → 1879,7
erel += reldata->count * bed->s->sizeof_rela;
(*bed->s->swap_reloca_out) (output_bfd, irel, erel);
}
@@ -10261,7 +10269,7 @@
@@ -10261,7 +10273,7 @@
else
{
s = elf_shdrp[elfsec]->bfd_section;
1904,7 → 1888,7
}
}
@@ -10364,15 +10372,14 @@
@@ -10364,15 +10376,14 @@
compare_link_order);
/* Change the offsets of the sections. */
1925,7 → 1909,7
}
free (sections);
@@ -11409,10 +11416,10 @@
@@ -11409,10 +11420,10 @@
continue;
if (strcmp (o->name, ".dynstr") != 0)
{
/sw/Makefile
1,14 → 1,141
all: binutils zasm
################################################################################
#
# Filename: Makefile
#
# Project: Zip CPU -- a small, lightweight, RISC CPU soft core
#
# Purpose: This makefile attempts to build the ZipCPU toolchain. This
# includes binutils and GCC. (Eventually, it will include the
# standard library as well ...) Configuration options for binutils and
# GCC can be found in the gas-script.sh and gcc-script.sh files
# respectively.
#
# Targets:
# make basic-install
# Attempts to build binutils, gcc, and the (now obsolete) zasm
# assembler, and to install them into INSTALL directory. This is
# also the default target.
#
# make all:
# Includes the basic-install target, but also the pdf
# documentation files that come with binutils and gcc. Building
# this target will require a LaTeX distribution in addition to the
# needs of the other targets. (These documents may also be found
# online, and have not been edited as part of the ZipCPU toolchain
# ... (yet).)
#
# make clean
#
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Technology, LLC
#
################################################################################
#
# Copyright (C) 2015, Gisselquist Technology, LLC
#
# This program is free software (firmware): you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
# by the Free Software Foundation, either version 3 of the License, or (at
# your option) any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# License: GPL, v3, as defined and found on www.gnu.org,
# http://www.gnu.org/licenses/gpl.html
#
#
################################################################################
#
basic-install: binutils-install gcc-install zasm-install
all: basic-install binutils-pdf-install gcc-pdf-install
 
BINUTILSD=binutils-2.25
BUILDGASD=build-gas
BUILDGCCD=build-gcc
INSTALL=`pwd`/install
PDFD=$(INSTALL)/usr/doc
ZASMD=zasm
 
binutils:
binutils-2.25: binutils-2.25.tar.bz2 binutils-2.25.patch
rm -rf binutils-2.25/
tar -xjf ./binutils-2.25.tar.bz2
bash -c "cd binutils-2.25; patch -p1 <../binutils-2.25.patch"
rm -rf $(BUILDGASD)
 
.PHONY: binutils
binutils: binutils-2.25
bash -c "if [ ! -e binutils-2.25 ]; then bash gas-script.sh; fi"
$(MAKE) --no-print-directory --directory=$(BINUTILSD)/build
$(MAKE) --no-print-directory --directory=$(BUILDGASD)
 
binutils-install:
$(MAKE) --no-print-directory --directory=$(BINUTILSD)/build install
.PHONY: binutils-install
binutils-install: binutils
$(MAKE) --no-print-directory --directory=$(BUILDGASD) install
 
.PHONY: binutils-pdf
binutils-pdf: binutils
$(MAKE) --no-print-directory --directory=$(BUILDGASD) pdf
 
.PHONY: binutils-pdf-install
binutils-pdf-install: binutils-pdf
mkdir -p $(PDFD)
find $(BUILDGASD) -name "*.pdf" -exec cp \{\} $(PDFD)/ \;
 
 
#
#
# Now let's try the same thing for GCC
#
#
gcc-5.3.0-zip: gcc-5.3.0.tar.bz2 gcc-5.3.0-specs-1.patch gcc-zippatch.patch
rm -rf gcc-5.3.0-zip/
tar -xjf ./gcc-5.3.0.tar.bz2 --transform s,gcc-5.3.0,gcc-5.3.0-zip,
bash -c "cd gcc-5.3.0-zip; patch -p1 <../gcc-5.3.0-specs-1.patch"
rm gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h.orig
bash -c "cd gcc-5.3.0-zip; patch -p1 <../gcc-zippatch.patch"
rm -rf $(BUILDGCCD)
.PHONY: gcc
gcc: gcc-5.3.0-zip
bash -c "if [[ ! -e $(BUILDGCCD) ]]; then gcc-script.sh; fi"
$(MAKE) --no-print-directory --directory=$(BUILDGCCD)/gcc
 
.PHONY: gcc-install
gcc-install: gcc
$(MAKE) --no-print-directory --directory=$(BUILDGCCD)/gcc install
 
.PHONY: gcc-pdf
gcc-pdf: gcc
$(MAKE) --no-print-directory --directory=$(BUILDGCCD) pdf
 
.PHONY: gcc-pdf-install
gcc-pdf-install: gcc-pdf
mkdir -p $(PDFD)
find $(BUILDGCCD) -name "*.pdf" -exec cp \{\} $(PDFD)/ \;
 
#
#
# Finally, can we build and install zasm?
#
#
zasm:
$(MAKE) --no-print-directory --directory=$(ZASMD)
 
zasm-install: zasm
$(MAKE) --no-print-directory --directory=$(ZASMD) install
 
#
#
# The clean target
#
#
.PHONY: clean
clean:
rm -rf $(INSTALL)
rm -rf binutils-2.25 gcc-5.3.0-zip
rm -rf $(BUILDGASD) $(BUILDGCCD)
$(MAKE) --no-print-directory --directory=$(ZASMD) clean
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.