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doc/gpl-3.0.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/spec.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/spec.pdf =================================================================== --- doc/spec.pdf (revision 21) +++ doc/spec.pdf (nonexistent)

doc/spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: doc/src/gqtekspec.cls =================================================================== --- doc/src/gqtekspec.cls (revision 21) +++ doc/src/gqtekspec.cls (nonexistent) @@ -1,296 +0,0 @@ -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/ -% -% Copyright (C) 2015, Gisselquist Technology, LLC -% -% This template is free software: you can redistribute it and/or modify it -% under the terms of the GNU General Public License as published by the -% Free Software Foundation, either version 3 of the License, or (at your -% option) any later version. -% -% This template is distributed in the hope that it will be useful, but WITHOUT -% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -% FITNESS FOR A PARTICULAR PURPOSE. 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It supercedes -%% any information about the instruction set or CPUs found -%% elsewhere. It's not nearly as interesting, though, as the PDF -%% file it creates, so I'd recommend reading that before diving -%% into this file. You should be able to find the PDF file in -%% the SVN distribution together with this PDF file and a copy of -%% the GPL-3.0 license this file is distributed under. If not, -%% just type 'make' in the doc directory and it (should) build -%% without a problem. -%% -%% -%% Creator: Dan Gisselquist -%% Gisselquist Technology, LLC -%% -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -%% -%% Copyright (C) 2015, Gisselquist Technology, LLC -%% -%% This program is free software (firmware): you can redistribute it and/or -%% modify it under the terms of the GNU General Public License as published -%% by the Free Software Foundation, either version 3 of the License, or (at -%% your option) any later version. -%% -%% This program is distributed in the hope that it will be useful, but WITHOUT -%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -%% for more details. -%% -%% You should have received a copy of the GNU General Public License along -%% with this program. (It's in the $(ROOT)/doc directory, run make with no -%% target there if the PDF file isn't present.) If not, see -%% for a copy. -%% -%% License: GPL, v3, as defined and found on www.gnu.org, -%% http://www.gnu.org/licenses/gpl.html -%% -%% -%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\documentclass{gqtekspec} -\project{Zip CPU} -\title{Specification} -\author{Dan Gisselquist, Ph.D.} -\email{dgisselq (at) opencores.org} -\revision{Rev.~0.1} -\begin{document} -\pagestyle{gqtekspecplain} -\titlepage -\begin{license} -Copyright (C) \theyear\today, Gisselquist Technology, LLC - -This project is free software (firmware): you can redistribute it and/or -modify it under the terms of the GNU General Public License as published -by the Free Software Foundation, either version 3 of the License, or (at -your option) any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License along -with this program. If not, see \hbox{} for a -copy. -\end{license} -\begin{revisionhistory} -0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline -\end{revisionhistory} -% Revision History -% Table of Contents, named Contents -\tableofcontents -% \listoffigures -\listoftables -\begin{preface} -Many people have asked me why I am building the Zip CPU. ARM processors are -good and effective. Xilinx makes and markets Microblaze, Altera Nios, and both -have better toolsets than the Zip CPU will ever have. OpenRISC is also -available. Why build a new processor? - -The easiest, most obvious answer is the simple one: Because I can. - -There's more to it, though. There's a lot that I would like to do with a -processor, and I want to be able to do it in a vendor independent fashion. -I would like to be able to generate Verilog code that can run equivalently -on both Xilinx and Altera chips, and that can be easily ported from one -manufacturer's chipsets to another. Even more, before purchasing a chip or a -board, I would like to know that my chip works. I would like to build a test -bench to test components with, and Verilator is my chosen test bench. This -forces me to use all Verilog, and it prevents me from using any proprietary -cores. For this reason, Microblaze and Nios are out of the question. - -Why not OpenRISC? That's a hard question. The OpenRISC team has done some -wonderful work on an amazing processor, and I'll have to admit that I am -envious of what they've accomplished. I would like to port binutils to the -Zip CPU, as I would like to port GCC and GDB. They are way ahead of me. The -OpenRISC processor, however, is complex and hefty at about 4,500 LUTs. It has -a lot of features of modern CPUs within it that ... well, let's just say it's -not the little guy on the block. The Zip CPU is lighter weight, costing only -about 2,000 LUTs with no peripherals, and 3,000 LUTs with some very basic -peripherals. - -My final reason is that I'm building the Zip CPU as a learning experience. The -Zip CPU has allowed me to learn a lot about how CPUs work on a very micro -level. For the first time, I am beginning to understand many of the Computer -Architecture lessons from years ago. - -To summarize: Because I can, because it is open source, because it is light -weight, and as an exercise in learning. - -\end{preface} - -\chapter{Introduction} -\pagenumbering{arabic} -\setcounter{page}{1} - - -The original goal of the ZIP CPU was to be a very simple CPU. You might -think of it as a poor man's alternative to the OpenRISC architecture. -For this reason, all instructions have been designed to be as simple as -possible, and are all designed to be executed in one instruction cycle per -instruction, barring pipeline stalls. Indeed, even the bus has been simplified -to a constant 32-bit width, with no option for more or less. This has -resulted in the choice to drop push and pop instructions, pre-increment and -post-decrement addressing modes, and more. - -For those who like buzz words, the Zip CPU is: -\begin{itemize} -\item A 32-bit CPU: All registers are 32-bits, addresses are 32-bits, - instructions are 32-bits wide, etc. -\item A RISC CPU. There is no microcode for executing instructions. -\item A Load/Store architecture. (Only load and store instructions - can access memory.) -\item Wishbone compliant. All peripherals are accessed just like - memory across this bus. -\item A Von-Neumann architecture. (The instructions and data share a - common bus.) -\item A pipelined architecture, having stages for {\bf Prefetch}, - {\bf Decode}, {\bf Read-Operand}, the {\bf ALU/Memory} - unit, and {\bf Write-back} -\item Completely open source, licensed under the GPL.\footnote{Should you - need a copy of the Zip CPU licensed under other terms, please - contact me.} -\end{itemize} - -Now, however, that I've worked on the Zip CPU for a while, it is not nearly -as simple as I originally hoped. Worse, I've had to adjust to create -capabilities that I was never expecting to need. These include: -\begin{itemize} -\item {\bf Extenal Debug:} Once placed upon an FPGA, some external means is - still necessary to debug this CPU. That means that there needs to be - an external register that can control the CPU: reset it, halt it, step - it, and tell whether it is running or not. Another register is placed - similar to this register, to allow the external controller to examine - registers internal to the CPU. - -\item {\bf Internal Debug:} Being able to run a debugger from within - a user process requires an ability to step a user process from - within a debugger. It also requires a break instruction that can - be substituted for any other instruction, and substituted back. - The break is actually difficult: the break instruction cannot be - allowed to execute. That way, upon a break, the debugger should - be able to jump back into the user process to step the instruction - that would've been at the break point initially, and then to - replace the break after passing it. - -\item {\bf Prefetch Cache:} My original implementation had a very - simple prefetch stage. Any time the PC changed the prefetch would go - and fetch the new instruction. While this was perhaps this simplest - approach, it cost roughly five clocks for every instruction. This - was deemed unacceptable, as I wanted a CPU that could execute - instructions in one cycle. I therefore have a prefetch cache that - issues pipelined wishbone accesses to memory and then pushes - instructions at the CPU. Sadly, this accounts for about 20\% of the - logic in the entire CPU, or 15\% of the logic in the entire system. - - -\item {\bf Operating System:} In order to support an operating system, - interrupts and so forth, the CPU needs to support supervisor and - user modes, as well as a means of switching between them. For example, - the user needs a means of executing a system call. This is the - purpose of the {\bf `trap'} instruction. This instruction needs to - place the CPU into supervisor mode (here equivalent to disabling - interrupts), as well as handing it a parameter such as identifying - which O/S function was called. - -My initial approach to building a trap instruction was to create - an external peripheral which, when written to, would generate an - interrupt and could return the last value written to it. This failed - timing requirements, however: the CPU executed two instructions while - waiting for the trap interrupt to take place. Since then, I've - decided to keep the rest of the CC register for that purpose so that a - write to the CC register, with the GIE bit cleared, could be used to - execute a trap. - -Modern timesharing systems also depend upon a {\bf Timer} interrupt - to handle task swapping. For the Zip CPU, this interrupt is handled - external to the CPU as part of the CPU System, found in - {\tt zipsystem.v}. The timer module itself is found in - {\tt ziptimer.v}. - -\item {\bf Pipeline Stalls:} My original plan was to not support pipeline - stalls at all, but rather to require the compiler to properly schedule - instructions so that stalls would never be necessary. After trying - to build such an architecture, I gave up, having learned some things: - - For example, in order to facilitate interrupt handling and debug - stepping, the CPU needs to know what instructions have finished, and - which have not. In other words, it needs to know where it can restart - the pipeline from. Once restarted, it must act as though it had - never stopped. This killed my idea of delayed branching, since - what would be the appropriate program counter to restart at? - The one the CPU was going to branch to, or the ones in the - delay slots? - - So I switched to a model of discrete execution: Once an instruction - enters into either the ALU or memory unit, the instruction is - guaranteed to complete. If the logic recognizes a branch or a - condition that would render the instruction entering into this stage - possibly inappropriate (i.e. a conditional branch preceeding a store - instruction for example), then the pipeline stalls for one cycle - until the conditional branch completes. Then, if it generates a new - PC address, the stages preceeding are all wiped clean. - - The discrete execution model allows such things as sleeping: if the - CPU is put to "sleep", the ALU and memory stages stall and back up - everything before them. Likewise, anything that has entered the ALU - or memory stage when the CPU is placed to sleep continues to completion. - To handle this logic, each pipeline stage has three control signals: - a valid signal, a stall signal, and a clock enable signal. In - general, a stage stalls if it's contents are valid and the next step - is stalled. This allows the pipeline to fill any time a later stage - stalls. - -\item {\bf Verilog Modules:} When examining how other processors worked - here on open cores, many of them had one separate module per pipeline - stage. While this appeared to me to be a fascinating and commendable - idea, my own implementation didn't work out quite so nicely. - - As an example, the decode module produces a {\em lot} of - control wires and registers. Creating a module out of this, with - only the simplest of logic within it, seemed to be more a lesson - in passing wires around, rather than encapsulating logic. - - Another example was the register writeback section. I would love - this section to be a module in its own right, and many have made them - such. However, other modules depend upon writeback results other - than just what's placed in the register (i.e., the control wires). - For these reasons, I didn't manage to fit this section into it's - own module. - - The result is that the majority of the CPU code can be found in - the {\tt zipcpu.v} file. -\end{itemize} - -With that introduction out of the way, let's move on to the instruction -set. - -\chapter{CPU Architecture}\label{chap:arch} - -The Zip CPU supports a set of two operand instructions, where the first operand -(always a register) is the result. The only exception is the store instruction, -where the first operand (always a register) is the source of the data to be -stored. - -\section{Register Set} -The Zip CPU supports two sets of sixteen 32-bit registers, a supervisor -and a user set. The supervisor set is used in interrupt mode, whereas -the user set is used otherwise. Of this register set, the Program Counter (PC) -is register 15, whereas the status register (SR) or condition code register -(CC) is register 14. By convention, the stack pointer will be register 13 and -noted as (SP)--although the instruction set allows it to be anything. -The CPU can access both register sets via move instructions from the -supervisor state, whereas the user state can only access the user registers. - -The status register is special, and bears further mention. The lower -8 bits of the status register form a set of condition codes. Writes to other -bits are preserved, and can be used as part of the trap architecture--examined -by the O/S upon any interrupt, cleared before returning. - -Of the eight condition codes, the bottom four are the current flags: - Zero (Z), - Carry (C), - Negative (N), - and Overflow (V). - -The next bit is a clock enable (0 to enable) or sleep bit (1 to put - the CPU to sleep). Setting this bit will cause the CPU to - wait for an interrupt (if interrupts are enabled), or to - completely halt (if interrupts are disabled). -The sixth bit is a global interrupt enable bit (GIE). When this - sixth bit is a '1' interrupts will be enabled, else disabled. When - interrupts are disabled, the CPU will be in supervisor mode, otherwise - it is in user mode. Thus, to execute a context switch, one only - need enable or disable interrupts. (When an interrupt line goes - high, interrupts will automatically be disabled, as the CPU goes - and deals with its context switch.) - -The seventh bit is a step bit. This bit can be - set from supervisor mode only. After setting this bit, should - the supervisor mode process switch to user mode, it would then - accomplish one instruction in user mode before returning to supervisor - mode. Then, upon return to supervisor mode, this bit will - be automatically cleared. This bit has no effect on the CPU while in - supervisor mode. - - This functionality was added to enable a userspace debugger - functionality on a user process, working through supervisor mode - of course. - - -The eighth bit is a break enable bit. This - controls whether a break instruction will halt the processor for an - external debuggerr (break enabled), or whether the break instruction - will simply set the STEP bit and send the CPU into interrupt mode. - This bit can only be set within supervisor mode. - -This functionality was added to enable an external debugger to - set and manage breakpoints. - -The ninth bit is reserved for a floating point enable bit. When set, the -arithmetic for the next instruction will be sent to a floating point unit. -Such a unit may later be added as an extension to the Zip CPU. If the -CPU does not support floating point instructions, this bit will never be set. - -The tenth bit is a trap bit. It is set whenever the user requests a soft -interrupt, and cleared on any return to userspace command. This allows the -supervisor, in supervisor mode, to determine whether it got to supervisor -mode from a trap or from an external interrupt or both. - -The status register bits are shown below: -\begin{table} -\begin{center} -\begin{tabular}{l|l} -Bit & Meaning \\\hline -9 & Soft trap, set on a trap from user mode, cleared when returing to user mode\\\hline -8 & (Reserved for) Floating point enable \\\hline -7 & Halt on break, to support an external debugger \\\hline -6 & Step, single step the CPU in user mode\\\hline -5 & GIE, or Global Interrupt Enable \\\hline -4 & Sleep \\\hline -3 & V, or overflow bit.\\\hline -2 & N, or negative bit.\\\hline -1 & C, or carry bit.\\\hline -0 & Z, or zero bit. \\\hline -\end{tabular} -\end{center} -\end{table} -\section{Conditional Instructions} -Most, although not quite all, instructions are conditionally executed. From -the four condition code flags, eight conditions are defined. These are shown -in Tbl.~\ref{tbl:conditions}. -\begin{table} -\begin{center} -\begin{tabular}{l|l|l} -Code & Mneumonic & Condition \\\hline -3'h0 & None & Always execute the instruction \\ -3'h1 & {\tt .Z} & Only execute when 'Z' is set \\ -3'h2 & {\tt .NE} & Only execute when 'Z' is not set \\ -3'h3 & {\tt .GE} & Greater than or equal ('N' not set, 'Z' irrelevant) \\ -3'h4 & {\tt .GT} & Greater than ('N' not set, 'Z' not set) \\ -3'h5 & {\tt .LT} & Less than ('N' not set) \\ -3'h6 & {\tt .C} & Carry set\\ -3'h7 & {\tt .V} & Overflow set\\ -\end{tabular} -\caption{Conditions for conditional operand execution}\label{tbl:conditions} -\end{center} -\end{table} -There is no condition code for less than or equal, not C or not V. Using -these conditions will take an extra instruction. -(Ex: \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)}) - -\section{Operand B} -Many instruction forms have a 21-bit source "Operand B" associated with them. -This Operand B is either equal to a register plus a signed immediate offset, -or an immediate offset by itself. This value is encoded as shown in -Tbl.~\ref{tbl:opb}. -\begin{table}\begin{center} -\begin{tabular}{|l|l|l|}\hline -Bit 20 & 19 \ldots 16 & 15 \ldots 0 \\\hline -1'b0 & \multicolumn{2}{l|}{Signed Immediate value} \\\hline -1'b1 & 4-bit Register & 16-bit Signed immediate offset \\\hline -\end{tabular} -\caption{Bit allocation for Operand B}\label{tbl:opb} -\end{center}\end{table} -\section{Address Modes} -The ZIP CPU supports two addressing modes: register plus immediate, and -immediate address. Addresses are therefore encoded in the same fashion as -Operand B's, shown above. - -A lot of long hard thought was put into whether to allow pre/post increment -and decrement addressing modes. Finding no way to use these operators without -taking two or more clocks per instruction, these addressing modes have been -removed from the realm of possibilities. This means that the Zip CPU has no -native way of executing push, pop, return, or jump to subroutine operations. - -\section{Move Operands} -The previous set of operands would be perfect and complete, save only that - the CPU needs access to non--supervisory registers while in supervisory - mode. Therefore, the MOV instruction is special and offers access - to these registers ... when in supervisory mode. To keep the compiler - simple, the extra bits are ignored in non-supervisory mode (as though - they didn't exist), rather than being mapped to new instructions or - additional capabilities. The bits indicating which register set each - register lies within are the A-Usr and B-Usr bits. When set to a one, - these refer to a user mode register. When set to a zero, these refer - to a register in the current mode, whether user or supervisor. - Further, because - a load immediate instruction exists, there is no move capability between - an immediate and a register: all moves come from either a register or - a register plus an offset. - -This actually leads to a bit of a problem: since the MOV instruction - encodes which register set each register is coming from or moving to, - how shall a compiler or assembler know how to compile a MOV instruction - without knowing the mode of the CPU at the time? For this reason, - the compiler will assume all MOV registers are supervisor registers, - and display them as normal. Anything with the user bit set will - be treated as a user register. The CPU will quietly ignore the - supervisor bits while in user mode, and anything marked as a user - register will always be valid. - -\section{Multiply Operations} -While the Zip CPU instruction set supports multiply operations, they are not -yet fully supported by the CPU. Two Multiply operations are supported, a -16x16 bit signed multiply (MPYS) and the same but unsigned (MPYU). In both -cases, the operand is a register plus a 16-bit immediate, subject to the -rule that the register cannot be the PC or CC registers. The PC register -field has been stolen to create a multiply by immediate instruction. The -CC register field is reserved. - -\section{Floating Point} -The ZIP CPU does not support floating point operations today. However, the -instruction set reserves a capability for a floating point operation. To -execute such an operation, simply set the floating point bit in the CC -register and the following instruction will interpret its registers as -a floating point instruction. Not all instructions, however, have floating -point equivalents. Further, the immediate fields do not apply in floating -point mode, and must be set to zero. Not all instructions make sense as -floating point operations. Therefore, only the CMP, SUB, ADD, and MPY -instructions may be issued as floating point instructions. Other instructions -allow the examining of the floating point bit in the CC register. In all -cases, the floating point bit is cleared one instruction after it is set. - -The architecture does not support a floating point not-implemented interrupt. -Any soft floating point emulation must be done deliberately. - -\section{Native Instructions} -The instruction set for the Zip CPU is summarized in -Tbl.~\ref{tbl:zip-instructions}. -\begin{table}\begin{center} -\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline -Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16} - & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0} - & Sets CC? \\\hline -CMP(Sub) & \multicolumn{4}{l|}{4'h0} - & \multicolumn{4}{l|}{D. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B} - & Yes \\\hline -BTST(And) & \multicolumn{4}{l|}{4'h1} - & \multicolumn{4}{l|}{D. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B} - & Yes \\\hline -MOV & \multicolumn{4}{l|}{4'h2} - & \multicolumn{4}{l|}{D. Reg} - & \multicolumn{3}{l|}{Cond.} - & A-Usr - & \multicolumn{4}{l|}{B-Reg} - & B-Usr - & \multicolumn{15}{l|}{15'bit signed offset} - & \\\hline -LODI & \multicolumn{4}{l|}{4'h3} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{24}{l|}{24'bit Signed Immediate} - & \\\hline -NOOP & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{4'he} - & \multicolumn{24}{l|}{24'h00} - & \\\hline -BREAK & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{4'he} - & \multicolumn{24}{l|}{24'h01} - & \\\hline -{\em Rsrd} & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{4'he} - & \multicolumn{24}{l|}{24'bits, but not 0 or 1.} - & \\\hline -LODIHI & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{4'hf} - & \multicolumn{3}{l|}{Cond.} - & 1'b1 - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{16}{l|}{16-bit Immediate} - & \\\hline -LODILO & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{4'hf} - & \multicolumn{3}{l|}{Cond.} - & 1'b0 - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{16}{l|}{16-bit Immediate} - & \\\hline -16-b MPYU & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & 1'b0 & \multicolumn{4}{l|}{Reg} - & \multicolumn{16}{l|}{16-bit Offset} - & Yes \\\hline -16-b MPYU(I) & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & 1'b0 & \multicolumn{4}{l|}{4'hf} - & \multicolumn{16}{l|}{16-bit Offset} - & Yes \\\hline -16-b MPYS & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & 1'b1 & \multicolumn{4}{l|}{Reg} - & \multicolumn{16}{l|}{16-bit Offset} - & Yes \\\hline -16-b MPYS(I) & \multicolumn{4}{l|}{4'h4} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & 1'b1 & \multicolumn{4}{l|}{4'hf} - & \multicolumn{16}{l|}{16-bit Offset} - & Yes \\\hline -ROL & \multicolumn{4}{l|}{4'h5} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits} - & \\\hline -LOD & \multicolumn{4}{l|}{4'h6} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B address} - & \\\hline -STO & \multicolumn{4}{l|}{4'h7} - & \multicolumn{4}{l|}{D. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B address} - & \\\hline -{\em Rsrd} & \multicolumn{4}{l|}{4'h8} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & 1'b0 - & \multicolumn{20}{l|}{Reserved} - & Yes \\\hline -SUB & \multicolumn{4}{l|}{4'h8} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & 1'b1 - & \multicolumn{4}{l|}{Reg} - & \multicolumn{16}{l|}{16'bit signed offset} - & Yes \\\hline -AND & \multicolumn{4}{l|}{4'h9} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B} - & Yes \\\hline -ADD & \multicolumn{4}{l|}{4'ha} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B} - & Yes \\\hline -OR & \multicolumn{4}{l|}{4'hb} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B} - & Yes \\\hline -XOR & \multicolumn{4}{l|}{4'hc} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B} - & Yes \\\hline -LSL/ASL & \multicolumn{4}{l|}{4'hd} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B, imm. trucated to 6 bits} - & Yes \\\hline -ASR & \multicolumn{4}{l|}{4'he} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B, imm. trucated to 6 bits} - & Yes \\\hline -LSR & \multicolumn{4}{l|}{4'hf} - & \multicolumn{4}{l|}{R. Reg} - & \multicolumn{3}{l|}{Cond.} - & \multicolumn{21}{l|}{Operand B, imm. trucated to 6 bits} - & Yes \\\hline -\end{tabular} -\caption{Zip CPU Instruction Set}\label{tbl:zip-instructions} -\end{center}\end{table} - -As you can see, there's lots of room for instruction set expansion. The -NOOP and BREAK instructions leave 24~bits of open instruction address -space, minus the two instructions NOOP and BREAK. The Subtract leaves half -of its space open, since a subtract immediate is the same as an add with a -negated immediate. - -\section{Derived Instructions} -The ZIP CPU supports many other common instructions, but not all of them -are single instructions. The derived instruction tables, -Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, and~\ref{tbl:derived-3}, -help to capture some of how these other instructions may be implemented on -the ZIP CPU. Many of these instructions will have assembly equivalents, -such as the branch instructions, to facilitate working with the CPU. -\begin{table}\begin{center} -\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline -Mapped & Actual & Notes \\\hline -\parbox[t]{1.4in}{ADD Ra,Rx\\ADDC Rb,Ry} - & \parbox[t]{1.5in}{Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry} - & Add with carry \\\hline -BRA.Cond +/-\$Addr - & Mov.cond \$Addr+PC,PC - & Branch or jump on condition. Works for 14 bit - address offsets.\\\hline -BRA.Cond +/-\$Addr - & \parbox[t]{1.5in}{LDI \$Addr,Rx \\ ADD.cond Rx,PC} - & Branch/jump on condition. Works for - 23 bit address offsets, but costs a register, an extra instruction, - and setsthe flags. \\\hline -BNC PC+\$Addr - & \parbox[t]{1.5in}{Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC} - & Example of a branch on an unsupported - condition, in this case a branch on not carry \\\hline -BUSY & MOV \$-1(PC),PC & Execute an infinite loop \\\hline -CLRF.NZ Rx - & XOR.NZ Rx,Rx - & Clear Rx, and flags, if the Z-bit is not set \\\hline -CLR Rx - & LDI \$0,Rx - & Clears Rx, leaves flags untouched. This instruction cannot be - conditional. \\\hline -EXCH.W Rx - & ROL \$16,Rx - & Exchanges the top and bottom 16'bit words of Rx \\\hline -HALT - & Or \$SLEEP,CC - & Executed while in interrupt mode. In user mode this is simply a - wait until interrupt instructioon. \\\hline -INT & LDI \$0,CC - & Since we're using the CC register as a trap vector as well, this - executes TRAP \#0. \\\hline -IRET - & OR \$GIE,CC - & Also an RTU instruction (Return to Userspace) \\\hline -JMP R6+\$Addr - & MOV \$Addr(R6),PC - & \\\hline -JSR PC+\$Addr - & \parbox[t]{1.5in}{SUB \$1,SP \\\ - MOV \$3+PC,R0 \\ - STO R0,1(SP) \\ - MOV \$Addr+PC,PC \\ - ADD \$1,SP} - & Jump to Subroutine. \\\hline -JSR PC+\$Addr - & \parbox[t]{1.5in}{MOV \$3+PC,R12 \\ MOV \$addr+PC,PC} - &This is the high speed - version of a subroutine call, necessitating a register to hold the - last PC address. In its favor, this method doesn't suffer the - mandatory memory access of the other approach. \\\hline -LDI.l \$val,Rx - & \parbox[t]{1.5in}{LDIHI (\$val$>>$16)\&0x0ffff, Rx \\ - LDILO (\$val \& 0x0ffff)} - & Sadly, there's not enough instruction - space to load a complete immediate value into any register. - Therefore, fully loading any register takes two cycles. - The LDIHI (load immediate high) and LDILO (load immediate low) - instructions have been created to facilitate this. \\\hline -\end{tabular} -\caption{Derived Instructions}\label{tbl:derived-1} -\end{center}\end{table} -\begin{table}\begin{center} -\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline -Mapped & Actual & Notes \\\hline -LOD.b \$addr,Rx - & \parbox[t]{1.5in}{% - LDI \$addr,Ra \\ - LDI \$addr,Rb \\ - LSR \$2,Ra \\ - AND \$3,Rb \\ - LOD (Ra),Rx \\ - LSL \$3,Rb \\ - SUB \$32,Rb \\ - ROL Rb,Rx \\ - AND \$0ffh,Rx} - & \parbox[t]{3in}{This CPU is designed for 32'bit word - length instructions. Byte addressing is not supported by the CPU or - the bus, so it therefore takes more work to do. - - Note also that in this example, \$Addr is a byte-wise address, where - all other addresses are 32-bit wordlength addresses. For this reason, - we needed to drop the bottom two bits. This also limits the address - space of character accesses using this method from 16 MB down to 4MB.} - \\\hline -\parbox[t]{1.5in}{LSL \$1,Rx\\ LSLC \$1,Ry} - & \parbox[t]{1.5in}{LSL \$1,Ry \\ - LSL \$1,Rx \\ - OR.C \$1,Ry} - & Logical shift left with carry. Note that the - instruction order is now backwards, to keep the conditions valid. - That is, LSL sets the carry flag, so if we did this the othe way - with Rx before Ry, then the condition flag wouldn't have been right - for an OR correction at the end. \\\hline -\parbox[t]{1.5in}{LSR \$1,Rx \\ LSRC \$1,Ry} - & \parbox[t]{1.5in}{CLR Rz \\ - LSR \$1,Ry \\ - LDIHI.C \$8000h,Rz \\ - LSR \$1,Rx \\ - OR Rz,Rx} - & Logical shift right with carry \\\hline -NEG Rx & \parbox[t]{1.5in}{XOR \$-1,Rx \\ ADD \$1,Rx} & \\\hline -NOOP & NOOP & While there are many - operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these - operations have consequences in that they might stall the bus if - Rx isn't ready yet. For this reason, we have a dedicated NOOP - instruction. \\\hline -NOT Rx & XOR \$-1,Rx & \\\hline -POP Rx - & \parbox[t]{1.5in}{LOD \$-1(SP),Rx \\ ADD \$1,SP} - & Note - that for interrupt purposes, one can never depend upon the value at - (SP). Hence you read from it, then increment it, lest having - incremented it firost something then comes along and writes to that - value before you can read the result. \\\hline -PUSH Rx - & \parbox[t]{1.5in}{SUB \$1,SPa \\ - STO Rx,\$1(SP)} - & \\\hline -RESET - & \parbox[t]{1in}{STO \$1,\$watchdog(R12)\\NOOP\\NOOP} - & \parbox[t]{3in}{This depends upon the peripheral base address being - in R12. - - Another opportunity might be to jump to the reset address from within - supervisor mode.}\\\hline -RET & \parbox[t]{1.5in}{LOD \$-1(SP),R0 \\ - MOV \$-1+SP,SP \\ - MOV R0,PC} - & An alternative might be to LOD \$-1(SP),PC, followed - by depending upon the calling program to ADD \$1,SP. \\\hline -\end{tabular} -\caption{Derived Instructions, continued}\label{tbl:derived-2} -\end{center}\end{table} -\begin{table}\begin{center} -\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline -RET & MOV R12,PC - & This is the high(er) speed version, that doesn't touch the stack. - As such, it doesn't suffer a stall on memory read/write to the stack. - \\\hline -STEP Rr,Rt - & \parbox[t]{1.5in}{LSR \$1,Rr \\ XOR.C Rt,Rr} - & Step a Galois implementation of a Linear Feedback Shift Register, Rr, - using taps Rt \\\hline -STO.b Rx,\$addr - & \parbox[t]{1.5in}{% - LDI \$addr,Ra \\ - LDI \$addr,Rb \\ - LSR \$2,Ra \\ - AND \$3,Rb \\ - SUB \$32,Rb \\ - LOD (Ra),Ry \\ - AND \$0ffh,Rx \\ - AND \$-0ffh,Ry \\ - ROL Rb,Rx \\ - OR Rx,Ry \\ - STO Ry,(Ra) } - & \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized - for byte-wise operations. - - Note that in this example, \$addr is a - byte-wise address, whereas in all of our other examples it is a - 32-bit word address. This also limits the address space - of character accesses from 16 MB down to 4MB.F - Further, this instruction implies a byte ordering, - such as big or little endian.} \\\hline -SWAP Rx,Ry - & \parbox[t]{1.5in}{ - XOR Ry,Rx \\ - XOR Rx,Ry \\ - XOR Ry,Rx} - & While no extra registers are needed, this example - does take 3-clocks. \\\hline -TRAP \#X - & LDILO \$x,CC - & This approach uses the unused bits of the CC register as a TRAP - address. If these bits are zero, no trap has occurred. Unlike my - previous approach, which was to use a trap peripheral, this approach - has no delay associated with it. To work, the supervisor will need - to clear this register following any trap, and the user will need to - be careful to only set this register prior to a trap condition. - Likewise, when setting this value, the user will need to make certain - that the SLEEP and GIE bits are not set in \$x. LDI would also work, - however using LDILO permits the use of conditional traps. (i.e., - trap if the zero flag is set.) Should you wish to trap off of a - register value, you could equivalently load \$x into the register and - then MOV it into the CC register. \\\hline -TST Rx - & TST \$-1,Rx - & Set the condition codes based upon Rx. Could also do a CMP \$0,Rx, - ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc. The TST and CMP - approaches won't stall future pipeline stages looking for the value - of Rx. \\\hline -WAIT - & Or \$SLEEP,CC - & Wait 'til interrupt. In an interrupts disabled context, this - becomes a HALT instruction. - -\end{tabular} -\caption{Derived Instructions, continued}\label{tbl:derived-3} -\end{center}\end{table} -\iffalse -\fi -\section{Pipeline Stages} -\begin{enumerate} -\item {\bf Prefetch}: Read instruction from memory (cache if possible). This - stage is actually pipelined itself, and so it will stall if the PC - ever changes. Stalls are also created here if the instruction isn't - in the prefetch cache. -\item {\bf Decode}: Decode instruction into op code, register(s) to read, and - immediate offset. -\item {\bf Read Operands}: Read registers and apply any immediate values to - them. This stage will stall if any source operand is pending. - A proper optimizing compiler, therefore, will schedule an instruction - between the instruction that produces the result and the instruction - that uses it. -\item Split into two tracks: An {\bf ALU} which will accomplish a simple - instruction, and the {\bf MemOps} stage which accomplishes memory - read/write. - \begin{itemize} - \item Loads stall instructions that access the register until it is - written to the register set. - \item Condition codes are available upon completion - \item Issuing an instruction to the memory while the memory is busy will - stall the bus. If the bus deadlocks, only a reset will - release the CPU. (Watchdog timer, anyone?) - \end{itemize} -\item {\bf Write-Back}: Conditionally write back the result to register set, - applying the condition. This routine is bi-re-entrant: either the - memory or the simple instruction may request a register write. -\end{enumerate} - -\section{Pipeline Logic} -How the CPU handles some instruction combinations can be telling when -determining what happens in the pipeline. The following lists some examples: -\begin{itemize} -\item {\bf Delayed Branching} - - I had originally hoped to implement delayed branching. However, what - happens in debug mode? - That is, what happens when a debugger tries to single step an - instruction? While I can easily single step the computer in either - user or supervisor mode from externally, this processor does not appear - able to step the CPU in user mode from within user mode--gosh, not even - from within supervisor mode--such as if a process had a debugger - attached. As the processor exists, I would have one result stepping - the CPU from a debugger, and another stepping it externally. - - This is unacceptable, and so this CPU does not support delayed - branching. - -\item {\bf Register Result:} {\tt MOV R0,R1; MOV R1,R2 } - - What value does - R2 get, the value of R1 before the first move or the value of R0? - Placing the value of R0 into R1 requires a pipeline stall, and possibly - two, as I have the pipeline designed. - - The ZIP CPU architecture requires that R2 must equal R0 at the end of - this operation. This may stall the pipeline 1-2 cycles. - -\item {\bf Condition Codes Result:} {\tt CMP R0,R1;Mov.EQ \$x,PC} - - - At issue is the same item as above, save that the CMP instruction - updates the flags that the MOV instruction depends - upon. - - The Zip CPU architecture requires that condition codes must be updated - and available immediately for the next instruction without stalling the - pipeline. - -\item {\bf Condition Codes Register Result:} {\tt CMP R0,R1; MOV CC,R2} - - At issue is the - fact that the logic supporting the CC register is more complicated than - the logic supporting any other register. - - The ZIP CPU will stall 1--2 cycles on this instruction, until the - CC register is valid. - -\item {\bf Delayed Branching: } {\tt ADD \$x,PC; MOV R0,R1} - - At issues is whether or not the instruction following the jump will - take place before the jump. In other words, is the MOV to the PC - register handled differently from an ADD to the PC register? - - In the Zip architecture, MOV'es and ADD's use the same logic - (simplifies the logic). -\end{itemize} - -As I've studied this, I find several approaches to handling pipeline - issues. These approaches (and their consequences) are listed below. - -\begin{itemize} -\item {\bf All All issued instructions complete, Stages stall individually} - - What about a slow pre-fetch? - - Nominally, this works well: any issued instruction - just runs to completion. If there are four issued instructions in the - pipeline, with the writeback instruction being a write-to-PC - instruction, the other three instructions naturally finish. - - This approach fails when reading instructions from the flash, - since such reads require N clocks to clocks to complete. Thus - there may be only one instruction in the pipeline if reading from flash, - or a full pipeline if reading from cache. Each of these approaches - would produce a different response. - -\item {\bf Issued instructions may be canceled} - - Stages stall individually - - First problem: - Memory operations cannot be canceled, even reads may have side effects - on peripherals that cannot be canceled later. Further, in the case of - an interrupt, it's difficult to know what to cancel. What happens in - a \hbox{\tt MOV.C \$x,PC} followed by a \hbox{\tt MOV \$y,PC} - instruction? Which get - canceled? - - Because it isn't clear what would need to be canceled, - this instruction combination is not recommended. - -\item {\bf All issued instructions complete.} - - All stages are filled, or the entire pipeline - stalls. - - What about debug control? What about - register writes taking an extra clock stage? MOV R0,R1; MOV R1,R2 - should place the value of R0 into R2. How do you restart the pipeline - after an interrupt? What address do you use? The last issued - instruction? But the branch delay slots may make that invalid! - - Reading from the CPU debug port in this case yields inconsistent - results: the CPU will halt or step with instructions stuck in the - pipeline. Reading registers will give no indication of what is going - on in the pipeline, just the results of completed operations, not of - operations that have been started and not yet completed. - Perhaps we should just report the state of the CPU based upon what - instructions (PC values) have successfully completed? Thus the - debug instruction is the one that will write registers on the next - clock. - - Suggestion: Suppose we load extra information in the two - CC register(s) for debugging intermediate pipeline stages? - - The next problem, though, is how to deal with the read operand - pipeline stage needing the result from the register pipeline.a - -\item {\bf Memory instructions must complete} - - All instructions that enter into the memory module *must* - complete. Issued instructions from the prefetch, decode, or operand - read stages may or may not complete. Jumps into code must be valid, - so that interrupt returns may be valid. All instructions entering the - ALU complete. - - This looks to be the simplest approach. - While the logic may be difficult, this appears to be the only - re-entrant approach. - - A {\tt new\_pc} flag will be high anytime the PC changes in an - unpredictable way (i.e., it doesn't increment). This includes jumps - as well as interrupts and interrupt returns. Whenever this flag may - go high, memory operations and ALU operations will stall until the - result is known. When the flag does go high, anything in the prefetch, - decode, and read-op stage will be invalidated. - -\end{itemize} - - - -\chapter{Peripherals}\label{chap:periph} -\section{Interrupt Controller} -\section{Counter} - -The Zip Counter is a very simple counter: it just counts. It cannot be -halted. When it rolls over, it issues an interrupt. Writing a value to the -counter just sets the current value, and it starts counting again from that -value. - -Eight counters are implemented in the Zip System for process accounting. -This may change in the future, as nothing as yet uses these counters. - -\section{Timer} - -The Zip Timer is also very simple: it simply counts down to zero. When it -transitions from a one to a zero it creates an interrupt. - -Writing any non-zero value to the timer starts the timer. If the high order -bit is set when writing to the timer, the timer becomes an interval timer and -reloads its last start time on any interrupt. Hence, to mark seconds, one -might set the timer to 100~million (the number of clocks per second), and -set the high bit. Ever after, the timer will interrupt the CPU once per -second (assuming a 100~MHz clock). - -\section{Watchdog Timer} - -The watchdog timer is no different from any of the other timers, save for one -critical difference: the interrupt line from the watchdog -timer is tied to the reset line of the CPU. Hence writing a `1' to the -watchdog timer will always reset the CPU. -To stop the Watchdog timer, write a '0' to it. To start it, -write any other number to it---as with the other timers. - -While the watchdog timer supports interval mode, it doesn't make as much sense -as it did with the other timers. - -\section{Jiffies} - -This peripheral is motivated by the Linux use of `jiffies' whereby a process -can request to be put to sleep until a certain number of `jiffies' have -elapsed. Using this interface, the CPU can read the number of `jiffies' -from the peripheral (it only has the one location in address space), add the -sleep length to it, and write teh result back to the peripheral. The zipjiffies -peripheral will record the value written to it only if it is nearer the current -counter value than the last current waiting interrupt time. If no other -interrupts are waiting, and this time is in the future, it will be enabled. -(There is currently no way to disable a jiffie interrupt once set, other -than to disable the register in the interrupt controller.) The processor -may then place this sleep request into a list among other sleep requests. -Once the timer expires, it would write the next Jiffy request to the peripheral -and wake up the process whose timer had expired. - -Indeed, the Jiffies register is nothing more than a glorified counter with -an interrupt. Unlike the other counters, the Jiffies register cannot be set. -Writes to the jiffies register create an interrupt time. When the Jiffies -register later equals the value written to it, an interrupt will be asserted -and the register then continues counting as though no interrupt had taken -place. - -The purpose of this register is to support alarm times within a CPU. To -set an alarm for a particular process $N$ clocks in advance, read the current -Jiffies value, and $N$, and write it back to the Jiffies register. The -O/S must also keep track of values written to the Jiffies register. Thus, -when an `alarm' trips, it should be remoed from the list of alarms, the list -should be sorted, and the next alarm in terms of Jiffies should be written -to the register. - -\chapter{Operation}\label{chap:ops} - -\chapter{Registers}\label{chap:regs} - -\chapter{Wishbone Datasheet}\label{chap:wishbone} -The Zip System supports two wishbone accesses, a slave debug port and a master -port for the system itself. These are shown in Tbl.~\ref{tbl:wishbone-slave} -\begin{table}[htbp] -\begin{center} -\begin{wishboneds} -Revision level of wishbone & WB B4 spec \\\hline -Type of interface & Slave, Read/Write, single words only \\\hline -Port size & 32--bit \\\hline -Port granularity & 32--bit \\\hline -Maximum Operand Size & 32--bit \\\hline -Data transfer ordering & (Irrelevant) \\\hline -Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline -Signal Names & \begin{tabular}{ll} - Signal Name & Wishbone Equivalent \\\hline - {\tt i\_clk} & {\tt CLK\_I} \\ - {\tt i\_dbg\_cyc} & {\tt CYC\_I} \\ - {\tt i\_dbg\_stb} & {\tt STB\_I} \\ - {\tt i\_dbg\_we} & {\tt WE\_I} \\ - {\tt i\_dbg\_addr} & {\tt ADR\_I} \\ - {\tt i\_dbg\_data} & {\tt DAT\_I} \\ - {\tt o\_dbg\_ack} & {\tt ACK\_O} \\ - {\tt o\_dbg\_stall} & {\tt STALL\_O} \\ - {\tt o\_dbg\_data} & {\tt DAT\_O} - \end{tabular}\\\hline -\end{wishboneds} -\caption{Wishbone Datasheet}\label{tbl:wishbone-slave} -\end{center}\end{table} -and Tbl.~\ref{tbl:wishbone-master} respectively. -\begin{table}[htbp] -\begin{center} -\begin{wishboneds} -Revision level of wishbone & WB B4 spec \\\hline -Type of interface & Master, Read/Write, sometimes pipelined \\\hline -Port size & 32--bit \\\hline -Port granularity & 32--bit \\\hline -Maximum Operand Size & 32--bit \\\hline -Data transfer ordering & (Irrelevant) \\\hline -Clock constraints & Works at 100~MHz on a Basys--3 board\\\hline -Signal Names & \begin{tabular}{ll} - Signal Name & Wishbone Equivalent \\\hline - {\tt i\_clk} & {\tt CLK\_O} \\ - {\tt o\_wb\_cyc} & {\tt CYC\_O} \\ - {\tt o\_wb\_stb} & {\tt STB\_O} \\ - {\tt o\_wb\_we} & {\tt WE\_O} \\ - {\tt o\_wb\_addr} & {\tt ADR\_O} \\ - {\tt o\_wb\_data} & {\tt DAT\_O} \\ - {\tt i\_wb\_ack} & {\tt ACK\_I} \\ - {\tt i\_wb\_stall} & {\tt STALL\_I} \\ - {\tt i\_wb\_data} & {\tt DAT\_I} - \end{tabular}\\\hline -\end{wishboneds} -\caption{Wishbone Datasheet}\label{tbl:wishbone-master} -\end{center}\end{table} -I do not recommend that you connect these together through the interconnect. - -The big thing to notice is that both the real time clock and the real time -date modules act as wishbone slaves, and that all accesses to the registers of -either module are 32--bit reads and writes. The address bus does not offer -byte level, but rather 32--bit word level resolution. Select lines are not -implemented. Bit ordering is the normal ordering where bit~31 is the most -significant bit and so forth. - -\chapter{Clocks}\label{chap:clocks} - -This core is based upon the Basys--3 design. The Basys--3 development board -contains one external 100~MHz clock, which is sufficient to run the ZIP CPU -core. -\begin{table}[htbp] -\begin{center} -\begin{clocklist} -i\_clk & External & 100~MHz & 100~MHz & System clock.\\\hline -\end{clocklist} -\caption{List of Clocks}\label{tbl:clocks} -\end{center}\end{table} -I hesitate to suggest that the core can run faster than 100~MHz, since I have -had struggled with various timing violations to keep it at 100~MHz. So, for -now, I will only state that it can run at 100~MHz. - - -\chapter{I/O Ports}\label{chap:ioports} -The I/O ports for this clock are shown in Tbls.~\ref{tbl:iowishbone} -\begin{table}[htbp] -\begin{center} -\begin{portlist} -i\_clk & 1 & Input & System clock, used for time and wishbone interfaces.\\\hline -i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline -i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline -i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline -i\_wb\_addr & 5 & Input & Wishbone address.\\\hline -i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing - (configuring) the core from the bus.\\\hline -o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or - signifying valid data in the case of a wishbone read request. - \\\hline -o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another - wishbone access, effectively stalling the bus.\\\hline -o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read - from the interface.\\\hline -\end{portlist} -\caption{Wishbone I/O Ports}\label{tbl:iowishbone} -\end{center}\end{table} -and~Tbl.~\ref{tbl:ioother}. -\begin{table}[htbp] -\begin{center} -\begin{portlist} -o\_sseg & 32 & Output & Lines to control a seven segment display, to be - sent to that display's driver. Each eight bit byte controls - one digit in the display, with the bottom bit in the byte - controlling the decimal point.\\\hline -o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting - from zero to all ones each minute, and synchronized with each - minute so as to create an indicator of when the next minute - will take place when only the hours and minutes can be - displayed.\\\hline -o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the - clock needs to generate an interrupt, it will set this line - high for one clock cycle. \\\hline -o\_ppd & 1 & Output & A `pulse per day' signal which can be fed into the - real--time date module. This line will be high on the clock before - the stroke of midnight, allowing the date module to turn over to the - next day at exactly the same time the clock module turns over to the - next day.\\\hline -i\_hack & 1 & Input & When this line is raised, copies are made of the - internal state registers on the next clock. These registers can then - be used for an accurate time hack regarding the state of the clock - at the time this line was strobed.\\\hline -\end{portlist} -\caption{Other I/O Ports}\label{tbl:ioother} -\end{center}\end{table} -Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in -Chapt.~\ref{chap:wishbone}, and so need no further discussion here. - - -% Appendices -% Index -\end{document} - - Index: doc/src/gpl-3.0.tex =================================================================== --- doc/src/gpl-3.0.tex (revision 21) +++ doc/src/gpl-3.0.tex (nonexistent) @@ -1,719 +0,0 @@ -\documentclass[11pt]{article} - -\title{GNU GENERAL PUBLIC LICENSE} -\date{Version 3, 29 June 2007} - -\begin{document} -\maketitle - -\begin{center} -{\parindent 0in - -Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/} - -\bigskip -Everyone is permitted to copy and distribute verbatim copies of this - -license document, but changing it is not allowed.} - -\end{center} - -\renewcommand{\abstractname}{Preamble} -\begin{abstract} -The GNU General Public License is a free, copyleft license for -software and other kinds of works. - -The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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If not, see . -\end{verbatim} -} - -Also add information on how to contact you by electronic and paper mail. - -If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - -{\footnotesize -\begin{verbatim} - Copyright (C) - -This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. -This is free software, and you are welcome to redistribute it -under certain conditions; type `show c' for details. -\end{verbatim} -} - -The hypothetical commands {\tt show w} and {\tt show c} should show -the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an ``about box''. - -You should also get your employer (if you work as a programmer) or -school, if any, to sign a ``copyright disclaimer'' for the program, if -necessary. For more information on this, and how to apply and follow -the GNU GPL, see \texttt{http://www.gnu.org/licenses/}. - -The GNU General Public License does not permit incorporating your -program into proprietary programs. If your program is a subroutine -library, you may consider it more useful to permit linking proprietary -applications with the library. If this is what you want to do, use -the GNU Lesser General Public License instead of this License. But -first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}. - -\end{enumerate} - -\end{document} Index: doc/src/GT.eps =================================================================== --- doc/src/GT.eps (revision 21) +++ doc/src/GT.eps (nonexistent) @@ -1,94 +0,0 @@ -%!PS-Adobe-3.0 EPSF-3.0 -%%BoundingBox: 0 0 504 288 -%%Creator: Gisselquist Technology LLC -%%Title: Gisselquist Technology Logo -%%CreationDate: 11 Mar 2014 -%%EndComments -%%BeginProlog -/black { 0 setgray } def -/white { 1 setgray } def -/height { 288 } def -/lw { height 8 div } def -%%EndProlog -% %%Page: 1 - -false { % A bounding box - 0 setlinewidth - newpath - 0 0 moveto - 0 height lineto - 1.625 height mul lw add 0 rlineto - 0 height neg rlineto - closepath stroke -} if - -true { % The "G" - newpath - height 2 div 1.25 mul height moveto - height 2 div height 4 div sub height lineto - 0 height 3 4 div mul lineto - 0 height 4 div lineto - height 4 div 0 lineto - height 3 4 div mul 0 lineto - height height 4 div lineto - height height 2 div lineto - % - height lw sub height 2 div lineto - height lw sub height 4 div lw 2 div add lineto - height 3 4 div mul lw 2 div sub lw lineto - height 4 div lw 2 div add lw lineto - lw height 4 div lw 2 div add lineto - lw height 3 4 div mul lw 2 div sub lineto - height 4 div lw 2 div add height lw sub lineto - height 2 div 1.25 mul height lw sub lineto - closepath fill - newpath - height 2 div height 2 div moveto - height 2 div 0 rlineto - 0 height 2 div neg rlineto - lw neg 0 rlineto - 0 height 2 div lw sub rlineto - height 2 div height 2 div lw sub lineto - closepath fill -} if - -height 2 div 1.25 mul lw add 0 translate -false { - newpath - 0 height moveto - height 0 rlineto - 0 lw neg rlineto - height lw sub 2 div neg 0 rlineto - 0 height lw sub neg rlineto - lw neg 0 rlineto - 0 height lw sub rlineto - height lw sub 2 div neg 0 rlineto - 0 lw rlineto - closepath fill -} if - -true { % The "T" of "GT". - newpath - 0 height moveto - height lw add 2 div 0 rlineto - 0 height neg rlineto - lw neg 0 rlineto - 0 height lw sub rlineto - height lw sub 2 div neg 0 rlineto - closepath fill - - % The right half of the top of the "T" - newpath - % (height + lw)/2 + lw - height lw add 2 div lw add height moveto - % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw - height 3 lw mul sub 2 div 0 rlineto - 0 lw neg rlineto - height 3 lw mul sub 2 div neg 0 rlineto - closepath fill -} if - - -grestore -showpage -%%EOF Index: doc/Makefile =================================================================== --- doc/Makefile (revision 21) +++ doc/Makefile (nonexistent) @@ -1,20 +0,0 @@ -all: gpl-3.0.pdf spec.pdf -DSRC := src - -gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex - latex $(DSRC)/gpl-3.0.tex - latex $(DSRC)/gpl-3.0.tex - dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi - ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf - rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps - -spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps - cd $(DSRC)/; latex spec.tex - cd $(DSRC)/; latex spec.tex - dvips -q -z -t letter -P pdf -o spec.ps $(DSRC)/spec.dvi - ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf - rm $(DSRC)/spec.dvi $(DSRC)/spec.log - rm $(DSRC)/spec.aux $(DSRC)/spec.toc - rm $(DSRC)/spec.lot # $(DSRC)/spec.lof - rm spec.ps -