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     \chapter{I/O Ports}\label{chap:ioports} The I/O ports for this clock are shown in Tbls.~\ref{tbl:iowishbone} \begin{table}[htbp] \begin{center} \begin{portlist} i\_clk & 1 & Input & System clock, used for time and wishbone interfaces.\\\hline i\_wb\_cyc & 1 & Input & Wishbone bus cycle wire.\\\hline i\_wb\_stb & 1 & Input & Wishbone strobe.\\\hline i\_wb\_we & 1 & Input & Wishbone write enable.\\\hline i\_wb\_addr & 5 & Input & Wishbone address.\\\hline i\_wb\_data & 32 & Input & Wishbone bus data register for use when writing  (configuring) the core from the bus.\\\hline o\_wb\_ack & 1 & Output & Return value acknowledging a wishbone write, or  signifying valid data in the case of a wishbone read request.  \\\hline o\_wb\_stall & 1 & Output & Indicates the device is not yet ready for another  wishbone access, effectively stalling the bus.\\\hline o\_wb\_data & 32 & Output & Wishbone data bus, returning data values read  from the interface.\\\hline \end{portlist} \caption{Wishbone I/O Ports}\label{tbl:iowishbone} \end{center}\end{table} and~Tbl.~\ref{tbl:ioother}.  \begin{table}[htbp] \begin{center} \begin{portlist} o\_sseg & 32 & Output & Lines to control a seven segment display, to be  sent to that display's driver. Each eight bit byte controls  one digit in the display, with the bottom bit in the byte  controlling the decimal point.\\\hline o\_led & 16 & Output & Output LED's, consisting of a 16--bit counter counting  from zero to all ones each minute, and synchronized with each  minute so as to create an indicator of when the next minute  will take place when only the hours and minutes can be  displayed.\\\hline o\_interrupt & 1 & Output & A pulsed/strobed interrupt line. When the  clock needs to generate an interrupt, it will set this line  high for one clock cycle. \\\hline o\_ppd & 1 & Output & A pulse per day' signal which can be fed into the  real--time date module. This line will be high on the clock before  the stroke of midnight, allowing the date module to turn over to the  next day at exactly the same time the clock module turns over to the  next day.\\\hline i\_hack & 1 & Input & When this line is raised, copies are made of the  internal state registers on the next clock. These registers can then  be used for an accurate time hack regarding the state of the clock  at the time this line was strobed.\\\hline \end{portlist} \caption{Other I/O Ports}\label{tbl:ioother} \end{center}\end{table} Tbl.~\ref{tbl:iowishbone} reiterates the wishbone I/O values just discussed in Chapt.~\ref{chap:wishbone}, and so need no further discussion here.     % Appendices % Index \end{document}`