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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu
    from Rev 122 to Rev 123
    Reverse comparison

Rev 122 → Rev 123

/trunk/sw/zasm/test.S
91,6 → 91,7
#define CONDITIONAL_EXECUTION_TEST
#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
#define BCMEM_TEST // Do memory and conditions work well together?
#define PIPELINE_MEMORY_RACE_CONDITIONS
test:
#ifdef DO_TEST_ASSEMBLER
; We start out by testing our assembler. We give it some instructions, which
406,6 → 407,7
sto r0,(r12)
rtu
mov ucc,r0
and 0x0ffff,r0
CMP sys.cctrap+sys.gie,r0
bnz test_failure
halt
744,6 → 746,12
WORD 0
end_bcmemtest:
#endif
 
#ifdef PIPELINE_MEMORY_RACE_CONDITIONS
LDI 0x14000,R11
FJSR(pipeline_memory_race_test,R0)
#endif // PIPELINE_MEMORY_RACE_CONDITIONS
 
// Return success / Test the trap interrupt
clr r11
trap r11 // FAILS HERE FAILS FAILS FAILS !!!!!!!!!!!
985,7 → 993,59
JMP R0
#endif // NOWAIT_PIPELINE_TEST
 
#ifdef PIPELINE_MEMORY_RACE_CONDITIONS
pipeline_memory_race_test:
SUB 3,SP
STO R0,(SP)
STO R1,1(SP)
STO R2,2(SP)
 
MOV pipeline_memory_test_data(PC),R0
LOD (R0),R0
LOD (R0),R0
CMP 275,R0
MOV.NZ R11,CC
 
MOV pipeline_memory_test_data(PC),R0
; Here's the test sequence
LOD (R0),R1
LOD 1(R0),R2
STO R2,1(R1)
; Make sure we clear the load pipeline
LOD (R0),R1
; Load our written value
LOD 2(R0),R2
CMP 275,R2
MOV.NZ R11,CC
 
;
; Next failing sequence:
; LOD -x(R12),R0
; LOD y(R0),R0
MOV pipeline_memory_test_data(PC),R0
MOV 1(R0),R1
STO R1,1(R0)
LDI 3588,R2 ; Just some random value
STO R2,2(R0)
MOV R0,R1
; Here's the test sequence
LOD (R0),R1
LOD 1(R1),R1
CMP R2,R1
MOV.NZ R11,CC
 
LOD (SP),R0
LOD 1(SP),R1
LOD 2(SP),R2
ADD 3,SP
JMP R0
pipeline_memory_test_data:
.dat __here__+0x0100000+1
.dat 275
.dat 0
#endif
 
fill 512,0
stack: // Must point to a valid word initially
word 0

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