URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu
- from Rev 129 to Rev 130
- ↔ Reverse comparison
Rev 129 → Rev 130
/trunk/rtl/core/idecode.v
75,7 → 75,8
output reg [3:0] o_cond; |
output reg o_wF; |
output reg [3:0] o_op; |
output reg o_ALU, o_M, o_DV, o_FP, o_break, o_lock; |
output reg o_ALU, o_M, o_DV, o_FP, o_break; |
output wire o_lock; |
output reg o_wR, o_rA, o_rB; |
output wire o_early_branch; |
output wire [(AW-1):0] o_branch_pc; |
86,10 → 87,13
wire o_dcd_early_branch; |
wire [(AW-1):0] o_dcd_branch_pc; |
reg o_dcdI, o_dcdIz; |
`ifdef OPT_PIPELINED |
reg r_lock; |
`endif |
|
|
wire [4:0] w_op; |
wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU; |
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev; |
wire [4:0] w_dcdR, w_dcdB, w_dcdA; |
wire w_dcdR_pc, w_dcdR_cc; |
wire w_dcdA_pc, w_dcdA_cc; |
123,8 → 127,9
assign w_op= iword[26:22]; |
assign w_mov = (w_op == 5'h0f); |
assign w_ldi = (w_op[4:1] == 4'hb); |
assign w_brev = (w_op == 5'hc); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldixx = (w_op[4:1] == 4'h4); |
assign w_ldilo = (w_op[4:0] == 5'h9); |
assign w_ALU = (~w_op[4]); |
|
// 4 LUTs |
176,7 → 181,7
||(w_op[4:1]== 4'h8); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx))); |
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi)); |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = ((w_dcdM)&&(w_op[0])) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
189,7 → 194,7
// and writes to the PC/CC register(s). |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldixx) |
||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev) |
&&(iword[30:28] != 3'h7)))); |
|
// Bottom 13 bits: no LUT's |
272,8 → 277,10
|
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7) |
&&( |
(w_op[2:0] != 3'h2) // LOCK |
&&(w_op[2:0] != 3'h1) // BREAK |
(w_op[2:0] != 3'h1) // BREAK |
`ifdef OPT_PIPELINED |
&&(w_op[2:0] != 3'h2) // LOCK |
`endif |
&&(w_op[2:0] != 3'h0))) // NOOP |
o_illegal <= 1'b1; |
end |
332,7 → 339,9
o_FP <= w_dcdFP; |
|
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001); |
o_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010); |
`ifdef OPT_PIPELINED |
r_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010); |
`endif |
`ifdef OPT_VLIW |
r_nxt_half <= { iword[31], iword[13:5], |
((iword[21])? iword[20:19] : 2'h0), |
340,6 → 349,12
`endif |
end |
|
`ifdef OPT_PIPELINED |
assign o_lock = r_lock; |
`else |
assign o_lock = 1'b0; |
`endif |
|
generate |
if (EARLY_BRANCHING!=0) |
begin |
416,6 → 431,7
o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31]) |
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22]) |
&&(i_instruction[17:14] == o_dcdB[3:0]) |
&&(i_instruction[17:14] != o_dcdA[3:0]) |
&&(i_gie == o_gie) |
&&((i_instruction[21:19]==o_cond[2:0]) |
||(o_cond[2:0] == 3'h0)) |