URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu
- from Rev 30 to Rev 29
- ↔ Reverse comparison
Rev 30 → Rev 29
/trunk/rtl/core/zipcpu.v
294,6 → 294,10
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
||((~opF[8])&&( |
((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG})) |
// Do I need this last condition? |
||(wr_flags_ce))) |
// Or waiting for a write to the PC register |
// Or CC register, since that can change the |
// PC as well |
567,7 → 571,7
opB_rd <= dcdB_rd; |
op_pc <= dcd_pc; |
// |
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie)); |
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)); |
end |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
|
595,18 → 599,16
`endif |
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&( |
`define DONT_STALL_ON_OPA |
`ifdef DONT_STALL_ON_OPA |
`define DONT_STALL_ON_OPB |
`ifdef DONT_STALL_ON_OPB |
// Skip the requirement on writing back opA |
// Stall on memory, since we'll always need to stall for a |
// memory access anyway |
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))|| |
((opvalid_alu)&&(opF_wr)&&(dcdA_cc))|| |
`else |
((opvalid)&&(opR_wr)&&(opR == dcdA))|| |
`endif |
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))); |
`define DONT_STALL_ON_OPB |
`ifdef DONT_STALL_ON_OPB |
reg opB_alu; |
always @(posedge i_clk) |
618,13 → 620,15
`endif |
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&( |
((opvalid)&&(opR_wr)&&(opR == dcdB) |
&&((opvalid_mem)||(dcdI != 0))) |
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc)) |
`ifdef DONT_STALL_ON_OPB |
&&((opvalid_mem)||(dcdI != 0)) |
`endif |
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))); |
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc)) |
&&(opvalid)&&(opR_cc); |
)|| |
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))); |
assign dcdF_stall = (dcdvalid)&&( |
(((~dcdF[3]) ||(dcdA_cc) ||(dcdB_cc)) |
&&(opvalid)&&((opR_cc)||(opF_wr))) |
||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr))); |
// |
// |
// PIPELINE STAGE #4 :: Apply Instruction |