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Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path 
    /zipcpu
    from Rev 62 to Rev 63
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  •

Rev 62 → Rev 63

/trunk/rtl/core/pipemem.v
108,8 → 108,8
begin
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
end else if ((i_pipe_stb)&&(~i_wb_stall))
begin
// end else if ((i_pipe_stb)&&(~i_wb_stall))
// begin
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
end
/trunk/rtl/core/prefetch.v
78,21 → 78,14
initial o_wb_stb = 1'b0;
initial o_wb_addr= 0;
always @(posedge i_clk)
if (i_rst)
if ((i_rst)||(i_wb_ack))
begin
o_wb_cyc <= 1'b0;
if (o_wb_cyc)
o_wb_addr <= 0;
end else if ((i_ce)&&(~o_wb_cyc)&&(o_wb_addr == i_pc))
begin // Single value cache check
o_aux <= i_aux;
// o_i was already set during the last bus cycle
o_wb_stb <= 1'b0;
end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
begin
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
o_wb_addr <= i_pc;
o_aux <= i_aux;
end else if (o_wb_cyc) // Independent of ce
begin
if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
102,7 → 95,15
end
 
always @(posedge i_clk)
if (i_rst) // Set the address to guarantee the result is invalid
o_wb_addr <= 1'b0;
else if ((i_ce)&&(~o_wb_cyc))
o_wb_addr <= i_pc;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
o_aux <= i_aux;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
o_i <= i_wb_data;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
/trunk/rtl/core/pipefetch.v
75,8 → 75,6
input i_wb_request;
output wire o_illegal;
 
assign o_illegal = 1'b0;
 
// Fixed bus outputs: we read from the bus only, never write.
// Thus the output data is ... irrelevant and don't care. We set it
// to zero just to set it to something.
119,7 → 117,7
initial r_cache_base = RESET_ADDRESS;
always @(posedge i_clk)
begin
if ((i_rst)||(i_clear_cache))
if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
188,6 → 186,7
end
end
 
initial r_nvalid = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
238,7 → 237,7
end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
else if ((o_wb_stb)&&(~i_wb_stall)) // && o_wb_cyc
o_wb_addr <= o_wb_addr + 1;
 
initial r_acks_waiting = 0;
245,9 → 244,10
always @(posedge i_clk)
if (~o_wb_cyc)
r_acks_waiting <= 0;
else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
// o_wb_cyc *must* be true for all following
else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)
r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc)
r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
 
always @(posedge i_clk)
287,4 → 287,13
if ((~o_v)||((i_stall_n)&&(o_v)))
o_pc <= r_addr;
 
reg [(AW-1):0] ill_address;
initial ill_address = 0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_err))
ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
 
assign o_illegal = (o_pc == ill_address);
 
 
endmodule

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