URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/bench
- from Rev 151 to Rev 152
- ↔ Reverse comparison
Rev 151 → Rev 152
/asm/zipdhry.S
50,6 → 50,8
// DMIPS: 8.2 100 MHz (sim) 0.08 // 20151104--!pipelined |
// DMIPS: 60.1 100 MHz (sim) 0.60 // 20151215 (New PF) |
// DMIPS: 60.0 100 MHz (sim) 0.60 // 20151226 (BugFix) |
// DMIPS: 100 MHz (sim) 0.67 // 20160406 (??) |
// DMIPS: 100 MHz (sim) 0.58 // 20160409 (BugFix) |
// On real hardware: |
// DMIPS: 24.7 100 MHz (basys) 0.25 // Initial baseline |
// DMIPS: 30.6 100 MHz (basys) 0.31 // 20151017 |
839,7 → 841,7
STO R3,1(R5) |
STO R2,30(R5) |
MOV R2,R5 |
MPYU 50,R5 ; R5 = 50 * R2 = 50 * loc |
MPY 50,R5 ; R5 = 50 * R2 = 50 * loc |
ADD R1,R5 ; R5 = &b[loc][0] |
MOV R5,R6 ; R6 = &b[loc][0] |
ADD R2,R5 ; R5 = &b[loc][loc] |
1382,8 → 1384,7
dhrystone_while_loop: |
// lcl_int_3 = 5 * lcl_int_1 - lcl_int_2; |
MOV R5,R7 |
LDI 5,R0 |
MPYS R0,R7 |
MPY 5,R7 |
SUB R6,R7 |
STO R7,lcl_int_3(SP) |
#ifndef SKIP_SHORT_CIRCUITS |
1505,7 → 1506,7
// |
// lcl_int_2 = lcl_int_2 * lcl_int_1; |
LOD lcl_int_1(SP),R5 |
MPYS R5,R6 ; lcl_int_2 = |
MPY R5,R6 ; lcl_int_2 = |
// lcl_int_1 = lcl_int_2 / lcl_int_3; |
#ifdef HARDWARE_DIVIDE |
LOD lcl_int_3(SP),R1 |
1525,7 → 1526,7
// lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1; |
LOD lcl_int_3(SP),R2 |
SUB R2,R6 |
MPYS 7,R6 |
MPY 7,R6 |
SUB R0,R6 |
// proc_2(&lcl_int_1); |
#ifndef SKIP_SHORT_CIRCUITS |