OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/bench
    from Rev 42 to Rev 43
    Reverse comparison

Rev 42 → Rev 43

/cpp/zippy_tb.cpp
37,6 → 37,7
#include <signal.h>
#include <time.h>
#include <unistd.h>
#include <poll.h>
 
#include <ctype.h>
#include <ncurses.h>
71,11 → 72,11
MEMSIM m_mem;
// QSPIFLASHSIM m_flash;
FILE *dbg_fp;
bool dbg_flag, bomb;
bool dbg_flag, bomb, m_show_user_timers;
int m_cursor;
 
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
if (true) {
if (false) {
dbg_fp = fopen("dbg.txt", "w");
dbg_flag = true;
} else {
84,6 → 85,7
}
bomb = false;
m_cursor = 0;
m_show_user_timers = false;
}
 
void reset(void) {
217,11 → 219,20
showval(ln,40, "TMRB", m_core->v__DOT__timer_c__DOT__r_value, (m_cursor==6));
showval(ln,60, "JIF ", m_core->v__DOT__jiffies__DOT__r_counter, (m_cursor==7));
 
ln++;
showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
if (!m_show_user_timers) {
ln++;
showval(ln, 0, "MTSK", m_core->v__DOT__mtc_data, (m_cursor==8));
showval(ln,20, "MOST", m_core->v__DOT__moc_data, (m_cursor==9));
showval(ln,40, "MPST", m_core->v__DOT__mpc_data, (m_cursor==10));
showval(ln,60, "MICT", m_core->v__DOT__mic_data, (m_cursor==11));
} else {
ln++;
showval(ln, 0, "UTSK", m_core->v__DOT__utc_data, (m_cursor==8));
showval(ln,20, "UOST", m_core->v__DOT__uoc_data, (m_cursor==9));
showval(ln,40, "UPST", m_core->v__DOT__upc_data, (m_cursor==10));
showval(ln,60, "UICT", m_core->v__DOT__uic_data, (m_cursor==11));
}
 
ln++;
mvprintw(ln, 40, "%s %s",
292,7 → 303,8
 
showreg(ln, 0, "uR12", 28, (m_cursor==40));
showreg(ln,20, "uSP ", 29, (m_cursor==41));
mvprintw(ln,40, "uCC :%s%s%s%s%s%s%s%s",
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s",
(m_cursor == 42)?'>':' ',
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ",
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ",
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ",
366,11 → 378,11
#ifdef OPT_PIPELINED_BUS_ACCESS
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
(m_core->v__DOT__thecpu__DOT__mem_ce),
(m_core->v__DOT__thecpu__DOT__master_ce),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
(!m_core->v__DOT__thecpu__DOT__clear_pipeline),
(m_core->v__DOT__thecpu__DOT__set_cond),
(!m_core->v__DOT__thecpu__DOT__mem_stalled),
(m_core->v__DOT__thecpu__DOT__master_ce), //1
(m_core->v__DOT__thecpu__DOT__opvalid_mem), //0
(!m_core->v__DOT__thecpu__DOT__clear_pipeline), //1
(m_core->v__DOT__thecpu__DOT__set_cond), //1
(!m_core->v__DOT__thecpu__DOT__mem_stalled), //1
 
(m_core->v__DOT__thecpu__DOT__mem_stalled),
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
395,6 → 407,10
(m_core->v__DOT__thecpu__DOT__r_opI));
#endif
mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__instruction);
printw(" A:%c%c B:%c",
(m_core->v__DOT__thecpu__DOT__opA_alu)?'A':'-',
(m_core->v__DOT__thecpu__DOT__opA_mem)?'M':'-',
(m_core->v__DOT__thecpu__DOT__opB_alu)?'A':'-');
 
 
showins(ln, "I ",
485,6 → 501,10
zop_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
}
 
void show_user_timers(bool v) {
m_show_user_timers = v;
}
 
unsigned int cmd_read(unsigned int a) {
if (dbg_fp) {
dbg_flag= true;
555,10 → 575,17
showval(ln,60, "JIF ", cmd_read(32+ 7), (m_cursor==7));
 
ln++;
showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
if (!m_show_user_timers) {
showval(ln, 0, "UTSK", cmd_read(32+8), (m_cursor==8));
showval(ln,20, "UMST", cmd_read(32+9), (m_cursor==9));
showval(ln,40, "UPST", cmd_read(32+10), (m_cursor==10));
showval(ln,60, "UICT", cmd_read(32+11), (m_cursor==11));
} else {
showval(ln, 0, "UTSK", cmd_read(32+12), (m_cursor==8));
showval(ln,20, "UMST", cmd_read(32+13), (m_cursor==9));
showval(ln,40, "UPST", cmd_read(32+14), (m_cursor==10));
showval(ln,60, "UICT", cmd_read(32+15), (m_cursor==11));
}
 
ln++;
ln++;
803,6 → 830,11
m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)
&&((m_core->o_wb_addr & (~((1<<20)-1))) != 0x100000))
m_core->i_wb_err = 1;
else
m_core->i_wb_err = 0;
TESTB<Vzipsystem>::tick();
}
if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) {
868,9 → 900,17
#endif
 
bool test_failure(void) {
if (m_core->v__DOT__thecpu__DOT__sleep)
return 0;
else if (m_core->v__DOT__thecpu__DOT__gie)
return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x2f0f7fff);
else
return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x2f0f7fff);
/*
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
&&(m_mem[alu_pc()] == 0x2f0f7fff)
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
*/
}
 
void wb_write(unsigned a, unsigned int v) {
1091,6 → 1131,12
printf("\t\t\'t\'\tClock a single tick through the system.\n");
}
 
bool signalled = false;
 
void sigint(int v) {
signalled = true;
}
 
int main(int argc, char **argv) {
Verilated::commandArgs(argc, argv);
ZIPPY_TB *tb = new ZIPPY_TB();
1099,6 → 1145,8
// mem[0x00000] = 0xbe000010; // Halt instruction
unsigned int mptr = 0;
 
signal(SIGINT, sigint);
 
if (argc <= 1) {
usage();
exit(-1);
1159,6 → 1207,7
*/
 
done = (tb->test_success())||(tb->test_failure());
done = done || signalled;
}
} else if (autostep) {
bool done = false;
1168,6 → 1217,7
while(!done) {
tb->wb_write(CMD_REG, CMD_STEP);
done = (tb->test_success())||(tb->test_failure());
done = done || signalled;
}
} else { // Interactive
initscr();
1182,7 → 1232,8
 
int chv = 'q';
 
bool done = false, halted = true, manual = true;
bool done = false, halted = true, manual = true,
high_speed = false;
 
halfdelay(1);
// tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1190,7 → 1241,17
// tb->show_state();
 
while(!done) {
chv = getch();
if ((high_speed)&&(!manual)&&(!halted)) {
struct pollfd fds[1];
fds[0].fd = STDIN_FILENO;
fds[0].events = POLLIN;
if (poll(fds, 1, 0) > 0)
chv = getch();
else
chv = ERR;
} else {
chv = getch();
}
switch(chv) {
case 'h': case 'H':
tb->wb_write(CMD_REG, CMD_HALT);
1198,7 → 1259,9
erase();
halted = true;
break;
case 'g': case 'G':
case 'G':
high_speed = true;
case 'g':
tb->wb_write(CMD_REG, 0);
if (halted)
erase();
1205,6 → 1268,9
halted = false;
manual = false;
break;
case 'm':
tb->show_user_timers(false);
break;
case 'q': case 'Q':
done = true;
break;
1222,6 → 1288,7
tb->wb_write(CMD_REG, CMD_STEP);
manual = false;
halted = true;
high_speed = false;
break;
case 'S':
if ((!manual)||(halted))
1228,6 → 1295,7
erase();
manual = true;
halted = true;
high_speed = false;
tb->m_core->v__DOT__cmd_halt = 0;
tb->m_core->v__DOT__cmd_step = 1;
tb->eval();
1238,6 → 1306,7
erase();
manual = true;
halted = true;
high_speed = false;
tb->m_core->v__DOT__cmd_halt = 1;
tb->m_core->v__DOT__cmd_step = 0;
tb->eval();
1248,11 → 1317,15
erase();
manual = true;
halted = false;
high_speed = false;
// tb->m_core->v__DOT__thecpu__DOT__step = 0;
// tb->m_core->v__DOT__cmd_halt = 0;
// tb->m_core->v__DOT__cmd_step = 0;
tb->tick();
break;
case 'u':
tb->show_user_timers(true);
break;
case KEY_IC: case KEY_ENTER: case KEY_RETURN:
get_value(tb);
break;
1278,7 → 1351,7
 
if (tb->m_core->i_rst)
done =true;
if (tb->bomb)
if ((tb->bomb)||(signalled))
done = true;
 
if (exit_on_done) {
1302,12 → 1375,16
break;
else if (tb->test_failure())
break;
else if (signalled)
break;
}
}
#endif
 
printf("\n");
printf("Clocks used : %08x\n", tb->m_core->v__DOT__mtc_data);
printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
printf("Tick Count : %08lx\n", tb->m_tickcount);
if (tb->m_core->v__DOT__mtc_data != 0)
printf("Instructions / Clock: %.2f\n",
(double)tb->m_core->v__DOT__mic_data
1324,6 → 1401,7
printf("TEST FAILED!\n");
} else
printf("User quit\n");
delete tb;
exit(rcode);
}
 
/cpp/testb.h
43,7 → 43,7
unsigned long m_tickcount;
 
TESTB(void) { m_core = new VA; }
~TESTB(void) { delete m_core; m_core = NULL; }
virtual ~TESTB(void) { delete m_core; m_core = NULL; }
 
virtual void eval(void) {
m_core->eval();
/cpp/Makefile
45,6 → 45,7
RAWLIB := /usr/share/verilator/include/verilated.cpp ../../rtl/obj_dir/Vzipsystem__ALL.a
LIBS := $(RAWLIB) -lncurses
TESTF := ../../sw/zasm/z.out
DHRYSTONEF := ../asm/zipdhry.z
 
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h
zippy_tb: $(RTLD)/cpudefs.h
62,6 → 63,10
test: zippy_tb stest
./zippy_tb -a $(TESTF)
 
.PHONY: dhrystone
dhrystone: zippy_tb
./zippy_tb -a $(DHRYSTONEF)
 
.PHONY: clean
clean:
rm ./zippy_tb

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.