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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/rtl/aux
    from Rev 36 to Rev 56
    Reverse comparison

Rev 36 → Rev 56

/wbpriarbiter.v
45,7 → 45,7
//
///////////////////////////////////////////////////////////////////////////
//
module wbpriarbiter(i_clk, i_rst,
module wbpriarbiter(i_clk,
// Bus A
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
// Bus B
53,9 → 53,8
// Both buses
o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err);
parameter DW=32, AW=32;
// Wishbone doesn't use an i_ce signal. While it could, they dislike
// what it would (might) do to the synchronous reset signal, i_rst.
input i_clk, i_rst;
//
input i_clk;
// Bus A
input i_a_cyc, i_a_stb, i_a_we;
input [(AW-1):0] i_a_adr;

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