URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl/core
- from Rev 18 to Rev 25
- ↔ Reverse comparison
Rev 18 → Rev 25
/cpuops.v
50,6 → 50,13
assign w_lsr_result = (|i_b[31:5])? 34'h00 |
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR |
|
|
wire signed [16:0] w_mpy_a_input, w_mpy_b_input; |
wire signed [33:0] w_mpy_result; |
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] }; |
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] }; |
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input; |
|
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
always @(posedge i_clk) |
67,7 → 74,8
casez(i_op) |
4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB |
4'b?001: o_c <= i_a & i_b; // BTST/And |
// 4'h4: o_c <= i_a[15:0] * i_b[15:0]; |
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S |
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S |
4'h5: o_c <= w_rol_result; // ROL |
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI |
/zipcpu.v
106,8 → 106,9
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_CC_REG 4'he |
`define CPU_TRAP_BIT 9 |
`define CPU_BREAK_BIT 7 |
`define CPU_STEP_BIT 6 |
`define CPU_GIE_BIT 5 |
132,7 → 133,7
// Debug interface -- outputs |
output reg o_dbg_stall; |
output reg [31:0] o_dbg_reg; |
output reg [3:0] o_dbg_cc; |
output reg [1:0] o_dbg_cc; |
output wire o_break; |
// Wishbone interface -- outputs |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
144,15 → 145,15
output wire o_op_stall; |
output wire o_pf_stall; |
output wire o_i_count; |
|
|
|
// Registers |
reg [31:0] regset [0:31]; |
|
// Condition codes |
reg [3:0] flags, iflags; // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
wire [7:0] w_uflags, w_iflags; |
reg break_en, step, gie, sleep; |
reg [3:0] flags, iflags; // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
wire [9:0] w_uflags, w_iflags; |
reg trap, break_en, step, gie, sleep; |
|
// The master chip enable |
wire master_ce; |
163,9 → 164,9
// Variable declarations |
// |
reg [31:0] pf_pc; |
reg new_pc; |
reg new_pc, op_break; |
wire clear_pipeline; |
assign clear_pipeline = new_pc || i_clear_pf_cache; |
assign clear_pipeline = new_pc || i_clear_pf_cache || op_break; |
|
wire dcd_stalled; |
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall; |
179,10 → 180,11
// Variable declarations |
// |
// |
reg opvalid, op_wr_pc, op_break; |
reg opvalid, opvalid_mem, opvalid_alu, op_wr_pc; |
wire op_stall, dcd_ce; |
reg [3:0] dcdOp; |
reg [4:0] dcdA, dcdB; |
reg dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc; |
reg [3:0] dcdF; |
reg dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid, |
dcdM, dcdF_wr, dcd_gie, dcd_break; |
203,12 → 205,12
reg [4:0] alu_reg; |
reg [3:0] opn; |
reg [4:0] opR; |
reg [1:0] opA_cc, opB_cc; |
reg [31:0] r_opA, r_opB, op_pc; |
wire [31:0] w_opA, w_opB; |
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opM, opF_wr, op_gie, |
reg opR_wr, opR_cc, opF_wr, op_gie, |
opA_rd, opB_rd; |
wire [7:0] opFl; |
wire [9:0] opFl; |
reg [6:0] r_opF; |
wire [8:0] opF; |
wire op_ce; |
247,7 → 249,7
// PIPELINE STAGE #5 :: Write-back |
// Variable declarations |
// |
wire wr_reg_ce, wr_flags_ce, wr_write_pc; |
wire wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc; |
wire [4:0] wr_reg_id; |
wire [31:0] wr_reg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
272,32 → 274,34
assign dcd_stalled = (dcdvalid)&&( |
(op_stall) |
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall)) |
||((opvalid)&&(op_wr_pc))); |
||((opvalid)&&((op_wr_pc)||(opR_cc)))); |
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
assign op_stall = (opvalid)&&( |
((mem_stalled)&&(opM)) |
||((alu_stall)&&(~opM))); |
assign op_stall = ((mem_stalled)&&(opvalid_mem)) |
||((alu_stall)&&(opvalid_alu)); |
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall)); |
|
// |
// PIPELINE STAGE #4 :: ALU / Memory |
// Calculate stall conditions |
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid)&&(~opM)) |
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id == { op_gie, `CPU_PC_REG })); |
assign alu_ce = (master_ce)&&(opvalid)&&(~opM)&&(~alu_stall)&&(~clear_pipeline); |
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) |
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie) |
&&(wr_write_pc)||(wr_write_cc)); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline); |
// |
assign mem_ce = (master_ce)&&(opvalid)&&(opM)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond); |
assign mem_stalled = (mem_busy)||((opvalid)&&(opM)&&( |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond); |
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
(~master_ce) |
// Stall waiting for flags to be valid |
||((~opF[8])&&( |
((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG})))) |
((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG})) |
// Do I need this last condition? |
//||((wr_flags_ce)&&(alu_gie==op_gie)))) |
||(wr_flags_ce))) |
// Or waiting for a write to the PC register |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&(wr_write_pc)))); |
// Or CC register, since that can change the |
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc))))); |
|
|
// |
344,9 → 348,12
// Default values |
dcdA[4:0] <= { instruction_gie, instruction[27:24] }; |
dcdB[4:0] <= { instruction_gie, instruction[19:16] }; |
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG); |
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG); |
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG); |
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG); |
dcdM <= 1'b0; |
dcdF_wr <= 1'b1; |
dcd_break <= 1'b0; |
|
// Set the condition under which we do this operation |
// The top four bits are a mask, the bottom four the |
374,8 → 381,9
dcdF <= 4'h8; // This is unconditional |
dcdOp <= 4'h2; |
end |
4'h4: begin // Load immediate special |
dcdF_wr <= 1'b0; // Don't write flags |
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK |
// Don't write flags except for multiplies |
dcdF_wr <= (instruction[27:25] != 3'h7); |
r_dcdI <= { 8'h00, instruction[15:0] }; |
if (instruction[27:24] == 4'he) |
begin |
384,7 → 392,6
dcdA_rd <= 1'b0; |
dcdB_rd <= 1'b0; |
dcdOp <= 4'h2; |
dcd_break <= 1'b1;//Could be a break ins |
end else if (instruction[27:24] == 4'hf) |
begin // Load partial immediate(s) |
dcdA_wr <= 1'b1; |
391,9 → 398,15
dcdA_rd <= 1'b1; |
dcdB_rd <= 1'b0; |
dcdA[4:0] <= { instruction_gie, instruction[19:16] }; |
dcdA_cc <= (instruction[19:16] == `CPU_CC_REG); |
dcdA_pc <= (instruction[19:16] == `CPU_PC_REG); |
dcdOp <= { 3'h3, instruction[20] }; |
end else begin |
; // Multiply instruction place holder |
// Actual multiply instruction |
r_dcdI <= { 8'h00, instruction[15:0] }; |
dcdA_rd <= 1'b1; |
dcdB_rd <= (instruction[19:16] != 4'hf); |
dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3; |
end end |
4'b011?: begin // Load/Store |
dcdF_wr <= 1'b0; // Don't write flags |
407,8 → 420,6
dcdM <= 1'b1; // Memory operation |
end |
default: begin |
dcdA <= { instruction_gie, instruction[27:24] }; |
dcdB <= { instruction_gie, instruction[19:16] }; |
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5); |
dcdA_rd <= 1'b1; |
dcdB_rd <= instruction[20]; |
422,6 → 433,11
|
dcd_gie <= instruction_gie; |
end |
always @(posedge i_clk) |
if (dcd_ce) |
dcd_break <= (instruction[31:0] == 32'h4e000001); |
else |
dcd_break <= 1'b0; |
|
|
// |
429,18 → 445,21
// PIPELINE STAGE #3 :: Read Operands (Registers) |
// |
// |
|
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
always @(posedge i_clk) |
if (op_ce) // &&(dcdvalid)) |
begin |
if ((wr_reg_ce)&&(wr_reg_id == dcdA)) |
r_opA <= wr_reg_vl; |
else if (dcdA == { dcd_gie, `CPU_PC_REG }) |
else if ((dcdA_pc)&&(dcdA[4] == dcd_gie)) |
r_opA <= dcd_pc; |
else if (dcdA[3:0] == `CPU_PC_REG) |
r_opA <= (dcdA[4])?upc:ipc; |
else if (dcdA_pc) |
r_opA <= upc; |
else if (dcdA_cc) |
r_opA <= { w_opA[31:10], (dcd_gie)?w_uflags:w_iflags }; |
else |
r_opA <= regset[dcdA]; |
r_opA <= w_opA; |
end |
wire [31:0] dcdI; |
assign dcdI = { {(8){r_dcdI[23]}}, r_dcdI }; |
451,10 → 470,12
r_opB <= dcdI; |
else if ((wr_reg_ce)&&(wr_reg_id == dcdB)) |
r_opB <= wr_reg_vl + dcdI; |
else if (dcdB == { dcd_gie, `CPU_PC_REG }) |
else if ((dcdB_pc)&&(dcdB[4] == dcd_gie)) |
r_opB <= dcd_pc + dcdI; |
else if (dcdB[3:0] == `CPU_PC_REG) |
r_opB <= ((dcdB[4])?upc:ipc) + dcdI; |
else if (dcdB_pc) // & dcdB[4] != dcd_gie thus is user |
r_opB <= upc + dcdI; |
else if (dcdB_cc) |
r_opB <= { w_opB[31:10], (dcd_gie)?w_uflags:w_iflags} + dcdI; |
else |
r_opB <= regset[dcdB] + dcdI; |
end |
468,8 → 489,6
// these two bits are redundant. Hence the convoluted expression |
// below, arriving at what we finally want in the (now wire net) |
// opF. |
`define NEWCODE |
`ifdef NEWCODE |
always @(posedge i_clk) |
if (op_ce) |
begin // Set the flag condition codes |
485,27 → 504,15
endcase |
end |
assign opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
`else |
always @(posedge i_clk) |
if (op_ce) |
begin // Set the flag condition codes |
case(dcdF[2:0]) |
3'h0: opF <= 9'h100; // Always |
3'h1: opF <= 9'h011; // Z |
3'h2: opF <= 9'h010; // NE |
3'h3: opF <= 9'h040; // GE (!N) |
3'h4: opF <= 9'h050; // GT (!N&!Z) |
3'h5: opF <= 9'h044; // LT |
3'h6: opF <= 9'h022; // C |
3'h7: opF <= 9'h088; // V |
endcase |
end |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
opvalid <= 1'b0; |
else if (op_ce) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
end else if (op_ce) |
begin |
// Do we have a valid instruction? |
// The decoder may vote to stall one of its |
// instructions based upon something we currently |
515,8 → 522,14
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
else if ((~op_stall)||(clear_pipeline)) |
opvalid <= 1'b0; |
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
end else if ((~op_stall)||(clear_pipeline)) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
end |
|
// Here's part of our debug interface. When we recognize a break |
// instruction, we set the op_break flag. That'll prevent this |
526,25 → 539,26
// condition, replace the break instruction with what it is supposed |
// to be, step through it, and then replace it back. In this fashion, |
// a debugger can step through code. |
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
initial op_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
op_break <= 1'b0; |
else if (op_ce) |
op_break <= (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
else if ((~op_stall)||(clear_pipeline)) |
op_break <= 1'b0; |
if (i_rst) op_break <= 1'b0; |
else if (op_ce) op_break <= (dcd_break); |
else if ((clear_pipeline)||(~opvalid)) |
op_break <= 1'b0; |
|
always @(posedge i_clk) |
if (op_ce) |
begin |
opn <= dcdOp; // Which ALU operation? |
opM <= dcdM; // Is this a memory operation? |
// opM <= dcdM; // Is this a memory operation? |
// Will we write the flags/CC Register with our result? |
opF_wr <= dcdF_wr; |
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr)); |
// Will we be writing our results into a register? |
opR_wr <= dcdA_wr; |
// What register will these results be written into? |
opR <= dcdA; |
opR_cc <= (dcdA_wr)&&(dcdA_cc); |
// User level (1), vs supervisor (0)/interrupts disabled |
op_gie <= dcd_gie; |
|
553,13 → 567,11
// assign so that there's no wait state between an |
// ALU or memory result and the next register that may |
// use that value. |
opA_cc <= {dcdA[4], (dcdA[3:0] == `CPU_CC_REG) }; |
opA_rd <= dcdA_rd; |
opB_cc <= {dcdB[4], (dcdB[3:0] == `CPU_CC_REG) }; |
opB_rd <= dcdB_rd; |
op_pc <= dcd_pc; |
// |
op_wr_pc <= ((dcdA_wr)&&(dcdA[3:0] == `CPU_PC_REG)); |
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)); |
end |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
|
575,24 → 587,48
// We'll create a flag here to start our coordination. Once we |
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&& |
(((opvalid)&&(opR_wr)&&(opR == dcdA)) |
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)) |
||((mem_valid)&&(mem_wreg == dcdA))); |
assign dcdB_stall = (dcdvalid)&&(dcdB_rd) |
&&(((opvalid)&&(opR_wr)&&(opR == dcdB)) |
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)) |
||((mem_valid)&&(mem_wreg == dcdB))); |
assign dcdF_stall = (dcdvalid)&&(((dcdF[3]) |
||(dcdA[3:0]==`CPU_CC_REG) |
||(dcdB[3:0]==`CPU_CC_REG)) |
&&((opvalid)&&(opR[3:0] == `CPU_CC_REG)) |
`define DONT_STALL_ON_OPA |
`ifdef DONT_STALL_ON_OPA |
reg opA_alu; |
always @(posedge i_clk) |
if (op_ce) |
opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd); |
assign opA = (opA_alu) ? alu_result : r_opA; |
`else |
assign opA = r_opA; |
`endif |
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&( |
`define DONT_STALL_ON_OPB |
`ifdef DONT_STALL_ON_OPB |
// Skip the requirement on writing back opA |
// Stall on memory, since we'll always need to stall for a |
// memory access anyway |
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))|| |
`else |
((opvalid)&&(opR_wr)&&(opR == dcdA))|| |
`endif |
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))); |
`ifdef DONT_STALL_ON_OPB |
reg opB_alu; |
always @(posedge i_clk) |
if (op_ce) |
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0); |
assign opB = (opB_alu) ? alu_result : r_opB; |
`else |
assign opB = r_opB; |
`endif |
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&( |
((opvalid)&&(opR_wr)&&(opR == dcdB) |
`ifdef DONT_STALL_ON_OPB |
&&((opvalid_mem)||(dcdI != 0)) |
`endif |
)|| |
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))); |
assign dcdF_stall = (dcdvalid)&&( |
(((~dcdF[3]) ||(dcdA_cc) ||(dcdB_cc)) |
&&(opvalid)&&((opR_cc)||(opF_wr))) |
||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr))); |
assign opA = { r_opA[31:8], ((opA_cc[0]) ? |
((opA_cc[1])?w_uflags:w_iflags) : r_opA[7:0]) }; |
assign opB = { r_opB[31:8], ((opB_cc[0]) ? |
((opB_cc[1])?w_uflags:w_iflags) : r_opB[7:0]) }; |
|
// |
// |
// PIPELINE STAGE #4 :: Apply Instruction |
599,7 → 635,7
// |
// |
cpuops doalu(i_clk, i_rst, alu_ce, |
(opvalid)&&(~opM), opn, opA, opB, |
(opvalid_alu), opn, opA, opB, |
alu_result, alu_flags, alu_valid); |
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]); |
630,8 → 666,7
initial alu_pc_valid = 1'b0; |
always @(posedge i_clk) |
alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline) |
&&((~opM) |
||(~mem_stalled)); |
&&((opvalid_alu)||(~mem_stalled)); |
|
memops domem(i_clk, i_rst, mem_ce, |
(opn[0]), opB, opA, opR, |
672,6 → 707,8
assign wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid); |
// Which register shall be written? |
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg; |
// Are we writing to the CC register? |
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG); |
// Are we writing to the PC? |
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG); |
// What value to write? |
687,12 → 724,12
// When shall we write to our flags register? alF_wr already |
// includes the set condition ... |
assign wr_flags_ce = (alF_wr)&&(alu_valid); |
assign w_uflags = { 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
assign w_uflags = { trap, 1'b0, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { trap, 1'b0, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
// What value to write? |
always @(posedge i_clk) |
// If explicitly writing the register itself |
if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG })) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc)) |
flags <= wr_reg_vl[3:0]; |
// Otherwise if we're setting the flags from an ALU operation |
else if ((wr_flags_ce)&&(alu_gie)) |
702,7 → 739,7
flags <= i_dbg_data[3:0]; |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG })) |
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
iflags <= wr_reg_vl[3:0]; |
else if ((wr_flags_ce)&&(~alu_gie)) |
iflags <= alu_flags; |
729,20 → 766,30
always @(posedge i_clk) |
if ((i_rst)||(i_halt)) |
break_en <= 1'b0; |
else if ((wr_reg_ce)&&(wr_reg_id[4:0] == {1'b0, `CPU_CC_REG})) |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
break_en <= wr_reg_vl[`CPU_BREAK_BIT]; |
assign o_break = (break_en)&&(op_break); |
assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy); |
|
|
// The sleep register. Setting the sleep register causes the CPU to |
// sleep until the next interrupt. Setting the sleep register within |
// interrupt mode causes the processor to halt until a reset. This is |
// a panic/fault halt. |
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
always @(posedge i_clk) |
if ((i_rst)||((i_interrupt)&&(gie))) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)) |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
// In supervisor mode, we have no protections. The |
// supervisor can set the sleep bit however he wants. |
sleep <= wr_reg_vl[`CPU_SLEEP_BIT]; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT])) |
// In user mode, however, you can only set the sleep |
// mode while remaining in user mode. You can't switch |
// to sleep mode *and* supervisor mode at the same |
// time, lest you halt the CPU. |
sleep <= wr_reg_vl[`CPU_SLEEP_BIT]; |
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG })) |
sleep <= i_dbg_data[`CPU_SLEEP_BIT]; |
750,7 → 797,7
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
step <= 1'b0; |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4:0] == {1'b1,`CPU_CC_REG})) |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc)) |
step <= wr_reg_vl[`CPU_STEP_BIT]; |
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG })) |
766,10 → 813,10
||((master_ce)&&(alu_pc_valid)&&(step)) |
// If we encounter a break instruction, if the break |
// enable isn't not set. |
||((master_ce)&&(op_break)) |
||((master_ce)&&(op_break)&&(~break_en)) |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4:0] == { 1'b1, `CPU_CC_REG })) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
// Or if, in debug mode, we write to the CC register |
||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT]) |
&&(i_dbg_reg == { 1'b1, `CPU_CC_REG})) |
777,7 → 824,7
assign w_release_from_interrupt = (~gie)&&(~i_interrupt) |
// Then if we write the CC register |
&&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4:0] == { 1'b0, `CPU_CC_REG })) |
&&(~wr_reg_id[4])&&(wr_write_cc)) |
// Or if, in debug mode, we write the CC register |
||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT]) |
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG})) |
790,6 → 837,19
else if (w_release_from_interrupt) |
gie <= 1'b1; |
|
initial trap = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
trap <= 1'b0; |
else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
trap <= 1'b1; |
else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG) |
&&(~i_dbg_data[`CPU_GIE_BIT])) |
trap <= i_dbg_data[`CPU_TRAP_BIT]; |
else if (w_release_from_interrupt) |
trap <= 1'b0; |
|
// |
// Write backs to the PC register, and general increments of it |
// We support two: upc and ipc. If the instruction is normal, |
859,16 → 919,16
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
o_dbg_reg <= { 25'h00, step, gie, sleep, |
((i_dbg_reg[4])?flags:iflags) }; |
o_dbg_reg[9:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
end |
always @(posedge i_clk) |
o_dbg_cc <= { break_en, step, gie, sleep }; |
o_dbg_cc <= { gie, sleep }; |
|
always @(posedge i_clk) |
o_dbg_stall <= (~i_halt)||(pf_cyc)||(mem_cyc)||(mem_busy) |
o_dbg_stall <= (i_halt)&&( |
(pf_cyc)||(mem_cyc)||(mem_busy) |
||((~opvalid)&&(~i_rst)) |
||((~dcdvalid)&&(~i_rst)); |
||((~dcdvalid)&&(~i_rst))); |
|
// |
// |