URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl/core
- from Rev 30 to Rev 34
- ↔ Reverse comparison
Rev 30 → Rev 34
/zipcpu.v
270,7 → 270,7
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
assign dcd_ce = (pf_valid)&&(~dcd_stalled); |
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline); |
assign dcd_stalled = (dcdvalid)&&( |
(op_stall) |
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall)) |
764,6 → 764,9
break_en <= 1'b0; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc)) |
break_en <= wr_reg_vl[`CPU_BREAK_BIT]; |
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG })) |
break_en <= i_dbg_data[`CPU_BREAK_BIT]; |
assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy); |
|
|
886,7 → 889,7
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_reg_vl; |
else if ((i_halt)&&(i_dbg_we) |
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG})) |
&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG})) |
pf_pc <= i_dbg_data; |
else if (dcd_ce) |
pf_pc <= pf_pc + 1; |
902,7 → 905,7
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else if ((i_halt)&&(i_dbg_we) |
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG})) |
&&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG})) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |