URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl/core
- from Rev 56 to Rev 62
- ↔ Reverse comparison
Rev 56 → Rev 62
/cpuops.v
41,25 → 41,18
output reg o_valid; |
output wire o_illegal; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
`ifndef NEW_NOT_OLD_CODE |
wire [33:0] w_lsr_result, w_asr_result; |
wire signed [33:0] w_ia_input; |
assign w_ia_input = { i_a[31], i_a, 1'b0 }; |
assign w_asr_result = (|i_b[31:5])? {(34){i_a[31]}} |
: ( w_ia_input >>> (i_b[4:0]) );// ASR |
assign w_lsr_result = (|i_b[31:5])? 34'h00 |
: { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR |
`else |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result; |
assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}} |
: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR |
assign w_lsr_result = (|i_b[31:5])? 33'h00 |
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR |
`endif |
|
|
wire z, n, v; |
72,6 → 65,12
||(i_op == 4'hd) // LSL |
||(i_op == 4'hf)); // LSR |
|
|
// A 4-way multiplexer can be done in one 6-LUT. |
// A 16-way multiplexer can therefore be done in 4x 6-LUT's with |
// the Xilinx multiplexer fabric that follows. |
// Given that we wish to apply this multiplexer approach to 33-bits, |
// this will cost a minimum of 132 6-LUTs. |
generate |
if (IMPLEMENT_MPY == 0) |
begin |
81,21 → 80,26
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB |
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB |
4'b?001: o_c <= i_a & i_b; // BTST/And |
// 4'h3: There's a hole here for the unimplemented MPYU, |
// 4'h4: and here for the unimplemented MPYS |
4'h5: o_c <= w_rol_result; // ROL |
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI |
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
4'ha: { c, o_c } <= i_a + i_b; // Add |
4'hb: o_c <= i_a | i_b; // Or |
4'hc: o_c <= i_a ^ i_b; // Xor |
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'he: { o_c, c } <= w_asr_result[32:0];// ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR |
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR |
default: o_c <= i_b; // MOV, LDI |
endcase |
end |
end else begin |
// |
// Multiply pre-logic |
// |
wire signed [16:0] w_mpy_a_input, w_mpy_b_input; |
wire signed [33:0] w_mpy_result; |
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] }; |
102,6 → 106,10
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] }; |
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input; |
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// |
// The master ALU case statement |
// |
always @(posedge i_clk) |
if (i_ce) |
begin |
108,19 → 116,19
pre_sign <= (i_a[31]); |
c <= 1'b0; |
casez(i_op) |
4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB |
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB |
4'b?001: o_c <= i_a & i_b; // BTST/And |
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S |
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S |
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU |
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS |
4'h5: o_c <= w_rol_result; // ROL |
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'h7: o_c <= { i_b[15:0], i_a[15:0] }; // LODIHI |
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI |
4'ha: { c, o_c } <= i_a + i_b; // Add |
4'hb: o_c <= i_a | i_b; // Or |
4'hc: o_c <= i_a ^ i_b; // Xor |
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL |
4'he: { o_c, c } <= w_asr_result[32:0];// ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR |
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR |
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR |
default: o_c <= i_b; // MOV, LDI |
endcase |
end |
131,7 → 139,7
begin |
reg r_illegal; |
always @(posedge i_clk) |
r_illegal <= (i_op == 4'h3)||(i_op == 4'h4); |
r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4)); |
assign o_illegal = r_illegal; |
end else |
assign o_illegal = 1'b0; |