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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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    /zipcpu/trunk/rtl/core
    from Rev 65 to Rev 69
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Rev 65 → Rev 69

/pipemem.v
13,7 → 13,7
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
35,7 → 35,7
//
///////////////////////////////////////////////////////////////////////////
//
module pipemem(i_clk, i_rst, i_pipe_stb,
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
i_op, i_addr, i_data, i_oreg,
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
42,9 → 42,9
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH = 24, AW=ADDRESS_WIDTH;
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
input i_clk, i_rst;
input i_pipe_stb;
input i_pipe_stb, i_lock;
// CPU interface
input i_op;
input [31:0] i_addr;
58,8 → 58,10
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output reg o_wb_cyc_gbl, o_wb_stb_gbl;
output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl, o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
// Wishbone inputs
66,6 → 68,7
input i_wb_ack, i_wb_stall, i_wb_err;
input [31:0] i_wb_data;
 
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
reg [3:0] rdaddr, wraddr;
wire [3:0] nxt_rdaddr;
reg [(5-1):0] fifo_oreg [0:15];
92,13 → 95,13
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
initial cyc = 0;
initial o_wb_cyc_lcl = 0;
initial o_wb_cyc_gbl = 0;
initial r_wb_cyc_lcl = 0;
initial r_wb_cyc_gbl = 0;
always @(posedge i_clk)
if (i_rst)
begin
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
cyc <= 1'b0;
116,14 → 119,14
 
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
begin
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
cyc <= 1'b0;
end
end else if (i_pipe_stb) // New memory operation
begin // Grab the wishbone
o_wb_cyc_lcl <= lcl_stb;
o_wb_cyc_gbl <= gbl_stb;
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
o_wb_stb_lcl <= lcl_stb;
o_wb_stb_gbl <= gbl_stb;
cyc <= 1'b1;
162,4 → 165,26
 
assign o_pipe_stalled = (cyc)
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
 
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
 
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl));
end
 
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
 
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
 
endmodule
/idecode_deprecated.v
0,0 → 1,306
///////////////////////////////////////////////////////////////////////////////
//
// Filename: idecode_deprecated.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This RTL file specifies how the original instruction set was
// to be decoded into a machine understandable microcode. It has
// been drawn out of zipcpu.v in an effort to provide some encapsulation,
// some of measuring its performance independently, and some means of
// updating it without impacting everything else (much).
//
// It has since been deprecated by a newer version of the instruction
// set architecture.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////////
//
//
//
//
`define CPU_CC_REG 4'he
`define CPU_PC_REG 4'hf
//
//
//
module idecode_deprecated(i_clk, i_rst, i_ce, i_stalled,
i_instruction, i_gie, i_pc, i_pf_valid, i_illegal,
o_phase, o_illegal,
o_pc, o_gie, o_R, o_A, o_B,
o_I, o_zI, o_cond, o_wF, o_op,
o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
o_wR, o_rA, o_rB,
o_early_branch, o_branch_pc
);
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
IMPLEMENT_DIVIDE=0, IMPLEMENT_FPU=0, AW=ADDRESS_WIDTH;
input i_clk, i_rst, i_ce, i_stalled;
input [31:0] i_instruction;
input i_gie;
input [(AW-1):0] i_pc;
input i_pf_valid, i_illegal;
output wire o_phase;
output reg o_illegal;
output reg [(AW-1):0] o_pc;
output reg o_gie;
output wire [6:0] o_R;
output reg [6:0] o_A, o_B;
output wire [31:0] o_I;
output reg o_zI;
output reg [3:0] o_cond;
output reg o_wF;
output reg [3:0] o_op;
output wire o_ALU, o_DV, o_FP;
output reg o_M, o_break, o_lock;
output reg o_wR, o_rA, o_rB;
output wire o_early_branch;
output wire [(AW-1):0] o_branch_pc;
 
 
assign o_phase = 1'b0;
assign o_R = { (o_A[6]), (o_A[5]), o_A[4:0] };
 
//
//
// PIPELINE STAGE #2 :: Instruction Decode
// Variable declarations
//
//
reg [23:0] r_I;
reg r_zI; // true if dcdI == 0
 
generate
if (EARLY_BRANCHING != 0)
begin
reg r_early_branch;
reg [(AW-1):0] r_branch_pc;
assign o_early_branch = r_early_branch;
assign o_branch_pc = r_branch_pc;
 
always @(posedge i_clk)
if ((i_ce)&&(i_instruction[27:24]==`CPU_PC_REG))
begin
r_early_branch <= 1'b0;
// First case, a move to PC instruction
if ((i_instruction[31:28] == 4'h2)
// Offsets of the PC register *only*
&&(i_instruction[19:16] == `CPU_PC_REG)
&&((i_gie)
||((~i_instruction[20])&&(~i_instruction[15])))
&&(i_instruction[23:21]==3'h0)) // Unconditional
begin
r_early_branch <= 1'b1;
end else // Next case, an Add Imm -> PC instruction
if ((i_instruction[31:28] == 4'ha) // Add
&&(~i_instruction[20]) // Immediate
&&(i_instruction[23:21]==3'h0)) // Always
begin
r_early_branch <= 1'b1;
end else // Next case: load Immediate to PC
if (i_instruction[31:28] == 4'h3)
begin
r_early_branch <= 1'b1;
end
end else
begin
if (i_ce) r_early_branch <= 1'b0;
end
 
if (AW == 24)
begin
always @(posedge i_clk)
if (i_ce)
begin
if (i_instruction[31]) // Add
begin
r_branch_pc <= i_pc
+ { {(AW-20){i_instruction[19]}}, i_instruction[19:0] }
+ {{(AW-1){1'b0}},1'b1};
end else if (~i_instruction[28]) // 4'h2 = MOV
r_branch_pc <= i_pc+{ {(AW-15){i_instruction[14]}}, i_instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
else // if (i_instruction[28]) // 4'h3 = LDI
r_branch_pc <= i_pc+{ i_instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
end
end else begin
always @(posedge i_clk)
if (i_ce)
begin
if (i_instruction[31]) // Add
begin
r_branch_pc <= i_pc
+ { {(AW-20){i_instruction[19]}}, i_instruction[19:0] }
+ {{(AW-1){1'b0}},1'b1};
end else if (~i_instruction[28]) // 4'h2 = MOV
begin
r_branch_pc <= i_pc+{ {(AW-15){i_instruction[14]}}, i_instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
end else // if (i_instruction[28]) // 4'h3 = LDI
begin
r_branch_pc <= i_pc+{ {(AW-24){i_instruction[23]}}, i_instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
end
end
end end else begin // No early branching
// wire o_early_branch;
// wire [(AW-1):0] o_branch_pc;
assign o_early_branch = 1'b0;
assign o_branch_pc = {(AW){1'b0}};
end endgenerate
 
wire [4:0] w_A, w_B;
wire w_mpy, w_wF, w_ldixx, w_zI;
wire [3:0] w_op;
wire [23:0] w_I;
 
assign w_op= i_instruction[31:28];
assign w_I = (w_op == 4'h2) ?
{ {(9){i_instruction[14]}},i_instruction[14:0] }
: ((w_op == 4'h3) ? { i_instruction[23:0] }
: ((w_op == 4'h4) ? { 8'h00, i_instruction[15:0] }
: (((w_op[3:1]==3'h3)&&(i_instruction[20])) ?
{ {(8){i_instruction[15]}},i_instruction[15:0] }
: (((w_op[3:1]==3'h3)&&(~i_instruction[20])) ?
{ {(4){i_instruction[19]}},i_instruction[19:0] }
: (i_instruction[20]) ?
{ {(8){i_instruction[15]}},i_instruction[15:0] }
: { {(4){i_instruction[19]}},i_instruction[19:0] }
))));
assign w_zI = (w_I == 0);
 
assign w_mpy = ((w_op == 4'h4)&&(i_instruction[27:25]!=3'h7));
assign w_ldixx = ((w_op == 4'h4)&&(i_instruction[27:24]==4'hf));
 
// 4 LUTs
assign w_A = { (((w_op==4'h2)&&(~i_gie))?i_instruction[20]:i_gie),
(w_ldixx)?(i_instruction[19:16]):(i_instruction[27:24])};
 
// 1 LUT
assign w_B = { (((w_op==4'h2)&&(~i_gie))?i_instruction[15]:i_gie),
(i_instruction[19:16]) };
 
// Don't change the flags on conditional instructions,
// UNLESS: the conditional instruction was a CMP or TST instruction.
// 8 LUTs
assign w_wF= (w_op[3:1]==3'h0)
||((i_instruction[23:21]==3'h0)&&((w_op[3])||(w_mpy)));
 
 
always @(posedge i_clk)
if (i_ce)
begin
o_pc <= i_pc +{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
 
// Record what operation we are doing
o_op <= (w_op == 4'h3) ? 4'h2
: ((w_op == 4'h4) ?
((i_instruction[27:24]==4'he) ? 4'h2
:((i_instruction[27:24]==4'hf) ?
(i_instruction[20]? 4'h7:4'h6)
:(i_instruction[20]? 4'h4:4'h3)))
: w_op);
 
// Default values
o_A <= {(w_A[3:0]==`CPU_CC_REG),(w_A[3:0]==`CPU_PC_REG),w_A};
o_B <= {(w_B[3:0]==`CPU_CC_REG),(w_B[3:0]==`CPU_PC_REG),w_B};
o_M <= (w_op[3:1] == 3'h3);
r_I <= w_I;
o_zI<= w_zI;
 
o_wF <= w_wF;
 
// 4 LUTs
o_rA <= (w_op[3:0] != 4'h2)
&&(w_op[3:0] != 4'h3)
&&((w_op[3:0] != 4'h4)||(i_instruction[27:24]!=4'he))
&&(w_op[3:0] != 4'h6);
 
// function of 11 bits, -- ugly
o_rB <= (w_op[3:0] != 4'h3) // Don't read for LDI
// Don't read for LODxx, NOOP, or MPYxI
&&((w_op[3:0] != 4'h4)
||(i_instruction[27:25]!=3'h7)
&&(i_instruction[19:16]!=4'hf))
// Always read on MOVE, or when OpB requests it
&&((w_op[3:0]==4'h2)||(i_instruction[20])
||(w_op[3:0]==4'h4));
 
// Always write back ... unless we are doing a store,
// CMP/TST, or a NOOP/BREAK
// 4 LUTs
o_wR <= (w_op[3:1] != 3'h0)
&&(w_op[3:0] != 4'h7)
&&((w_op[3:0] != 4'h4)
||(i_instruction[27:24] != 4'he));
 
o_illegal <= i_illegal;
 
// Set the condition under which we do this operation
// The top four bits are a mask, the bottom four the
// value the flags must equal once anded with the mask
o_cond <= (i_instruction[31:28]==4'h3)? 4'h8
: { (i_instruction[23:21]==3'h0),
i_instruction[23:21]};
casez(i_instruction[31:28])
4'h2: begin // Move instruction
end
4'h3: begin // Load immediate
o_op <= 4'h2;
end
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
if (i_instruction[27:24] == 4'he)
begin
// NOOP instruction
// Might also be a break. Big
// instruction set hole here.
o_illegal <= (i_illegal)||(i_instruction[23:3] != 0);
end else if (i_instruction[27:24] == 4'hf)
begin // Load partial immediate(s)
// o_op <= { 3'h3, instruction[20] };
end else begin
// Actual multiply instruction
// dcdA_rd <= 1'b1;
// dcdB_rd <= (i_instruction[19:16] != 4'hf);
// o_op[3:0] <= (i_instruction[20])? 4'h4:4'h3;
end end
default: begin
end
endcase
o_gie <= i_gie;
end
 
initial o_break = 1'b0;
initial o_lock = 1'b0;
always @(posedge i_clk)
if (i_ce)
begin // 6 LUTs
o_break <= (i_instruction[31:0] == 32'h4e000001);
o_lock <= (i_instruction[31:0] == 32'h4e000002);
end
 
assign o_I = { {(32-24){r_I[23]}}, r_I};
assign o_ALU = (~o_M);
assign o_DV = 1'b0;
assign o_FP = 1'b0;
 
endmodule
/idecode.v
0,0 → 1,359
///////////////////////////////////////////////////////////////////////////////
//
// Filename: idecode.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This RTL file specifies how instructions are to be decoded
// into their underlying meanings. This is specifically a version
// designed to support a "Next Generation", or "Version 2" instruction
// set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
// in cpudefs.v.
//
// I expect to (eventually) retire the old instruction set, at which point
// this will become the default instruction set decoder.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////////
//
//
//
`define CPU_CC_REG 4'he
`define CPU_PC_REG 4'hf
//
`include "cpudefs.v"
//
//
//
module idecode(i_clk, i_rst, i_ce, i_stalled,
i_instruction, i_gie, i_pc, i_pf_valid,
i_illegal,
o_phase, o_illegal,
o_pc, o_gie,
o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
o_cond, o_wF,
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
o_wR, o_rA, o_rB,
o_early_branch, o_branch_pc
);
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
input i_clk, i_rst, i_ce, i_stalled;
input [31:0] i_instruction;
input i_gie;
input [(AW-1):0] i_pc;
input i_pf_valid, i_illegal;
output wire o_phase;
output reg o_illegal;
output reg [(AW-1):0] o_pc;
output reg o_gie;
output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
output wire [31:0] o_I;
output reg o_zI;
output reg [3:0] o_cond;
output reg o_wF;
output reg [3:0] o_op;
output reg o_ALU, o_M, o_DV, o_FP, o_break, o_lock;
output reg o_wR, o_rA, o_rB;
output wire o_early_branch;
output wire [(AW-1):0] o_branch_pc;
 
wire dcdA_stall, dcdB_stall, dcdF_stall;
wire o_dcd_early_branch;
wire [(AW-1):0] o_dcd_branch_pc;
reg o_dcdI, o_dcdIz;
 
 
wire [4:0] w_op;
wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
wire [4:0] w_dcdR, w_dcdB, w_dcdA;
wire w_dcdR_pc, w_dcdR_cc;
wire w_dcdA_pc, w_dcdA_cc;
wire w_dcdB_pc, w_dcdB_cc;
wire [3:0] w_cond;
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
wire w_wR, w_rA, w_rB, w_wR_n;
 
 
wire [31:0] iword;
`ifdef OPT_VLIW
reg [16:0] r_nxt_half;
assign iword = (o_phase)
// set second half as a NOOP ... but really
// shouldn't matter
? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
: i_instruction;
`else
assign iword = { 1'b0, i_instruction[30:0] };
`endif
 
assign w_op= iword[26:22];
assign w_mov = (w_op == 5'h0f);
assign w_ldi = (w_op[4:1] == 4'hb);
assign w_cmptst = (w_op[4:1] == 4'h8);
assign w_ldixx = (w_op[4:1] == 4'h4);
assign w_ALU = (~w_op[4]);
 
// 4 LUTs
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
iword[30:27] };
// 4 LUTs
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
iword[17:14] };
 
// 0 LUTs
assign w_dcdA = w_dcdR;
// 2 LUTs, 1 delay each
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
// 0 LUTs
assign w_dcdA_pc = w_dcdR_pc;
assign w_dcdA_cc = w_dcdR_cc;
// 2 LUTs, 1 delays each
assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
 
// Under what condition will we execute this
// instruction? Only the load immediate instruction
// is completely unconditional.
//
// 3+4 LUTs
assign w_cond = (w_ldi) ? 4'h8 :
(iword[31])?{(iword[20:19]==2'b00),
1'b0,iword[20:19]}
: { (iword[21:19]==3'h0), iword[21:19] };
 
// 1 LUT
assign w_dcdM = (w_op[4:1] == 4'h9);
// 1 LUT
assign w_dcdDV = (w_op[4:1] == 4'ha);
// 1 LUT
assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
assign w_rA = (w_dcdFP)
// Divide's read A
||(w_dcdDV)
// ALU read's A, unless it's a MOV to A
// This includes LDIHI/LDILO
||((~w_op[4])&&(w_op[3:0]!=4'hf))
// STO's read A
||((w_dcdM)&&(w_op[0]))
// Test/compares
||(w_op[4:1]== 4'h8);
// 1 LUTs -- do we read a register for operand B? Specifically, do
// we need to stall if the register is not (yet) ready?
assign w_rB = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx)));
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
assign w_wR_n = ((w_dcdM)&&(w_op[0]))
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
||(w_cmptst);
assign w_wR = ~w_wR_n;
// 1-output bit (5 Opcode bits, 3 out-reg bits, 3 condition bits)
//
// This'd be 4 LUTs, save that we have the carve out for NOOPs
assign w_wF = (w_cmptst)
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
||((w_ALU)&&(~w_mov)&&(~w_ldixx))));
 
// Bottom 13 bits: no LUT's
// w_dcd[12: 0] -- no LUTs
// w_dcd[ 13] -- 2 LUTs
// w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
// w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
reg [22:0] r_I;
wire [22:0] w_I, w_fullI;
wire w_Iz;
 
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
: { {(23-14){iword[13]}}, iword[13:0] }
));
 
`ifdef OPT_VLIW
wire [5:0] w_halfI;
assign w_halfI = (w_ldi) ? iword[5:0]
:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
`else
assign w_I = w_fullI;
`endif
assign w_Iz = (w_I == 0);
 
 
`ifdef OPT_VLIW
//
// The o_phase parameter is special. It needs to let the software
// following know that it cannot break/interrupt on an o_phase asserted
// instruction, lest the break take place between the first and second
// half of a VLIW instruction. To do this, o_phase must be asserted
// when the first instruction half is valid, but not asserted on either
// a 32-bit instruction or the second half of a 2x16-bit instruction.
reg r_phase;
initial r_phase = 1'b0;
always @(posedge i_clk)
if (i_rst) // When no instruction is in the pipe, phase is zero
r_phase <= 1'b0;
else if (i_ce)
r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
// Phase is '1' on the first instruction of a two-part set
// But, due to the delay in processing, it's '1' when our output is
// valid for that first part, but that'll be the same time we
// are processing the second part ... so it may look to us like a '1'
// on the second half of processing.
 
assign o_phase = r_phase;
`else
assign o_phase = 1'b0;
`endif
 
 
always @(posedge i_clk)
if (i_ce)
begin
`ifdef OPT_VLIW
if (~o_phase)
begin
o_gie<= i_gie;
// i.e. dcd_pc+1
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
end
 
o_illegal <= (i_illegal);
`else
o_illegal <= ((i_illegal) || (i_instruction[31]));
o_gie<= i_gie;
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
`endif
 
if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
o_illegal <= 1'b1;
 
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
o_illegal <= 1'b1;
else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
o_illegal <= 1'b1;
 
 
if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
o_illegal <= 1'b1;
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
o_illegal <= 1'b1;
 
// Under what condition will we execute this
// instruction? Only the load immediate instruction
// is completely unconditional.
o_cond <= w_cond;
// Don't change the flags on conditional instructions,
// UNLESS: the conditional instruction was a CMP
// or TST instruction.
o_wF <= w_wF;
 
// Record what operation/op-code (4-bits) we are doing
// Note that LDI magically becomes a MOV
// instruction here. That way it's a pass through
// the ALU. Likewise, the two compare instructions
// CMP and TST becomes SUB and AND here as well.
// We keep only the bottom four bits, since we've
// already done the rest of the decode necessary to
// settle between the other instructions. For example,
// o_FP plus these four bits uniquely defines the FP
// instruction, o_DV plus the bottom of these defines
// the divide, etc.
o_op <= (w_ldi)? 4'hf:w_op[3:0];
 
// Default values
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
o_wR <= w_wR;
o_rA <= w_rA;
o_rB <= w_rB;
r_I <= w_I;
o_zI <= w_Iz;
 
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
o_M <= w_dcdM;
o_DV <= w_dcdDV;
o_FP <= w_dcdFP;
 
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
o_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
&&((w_op[2])||(w_op[1:0]==2'b11)))
o_illegal <= 1'b1;
 
`ifdef OPT_VLIW
r_nxt_half <= { iword[31], iword[13:5],
((iword[21])? iword[20:19] : 2'h0),
iword[4:0] };
`endif
end
 
 
generate
if (EARLY_BRANCHING!=0)
begin
reg r_early_branch;
reg [(AW-1):0] r_branch_pc;
always @(posedge i_clk)
if ((i_ce)&&(w_dcdR_pc)&&(w_cond[3]))
begin
if ((w_op == 5'hf)&&(w_dcdB_pc)&&(w_dcdA_pc))
begin // Move (X+PC) to PC
r_early_branch <= 1'b1;
end else if (w_op[4:1] == 4'hb) // LDI to PC
begin // LDI x,PC
r_early_branch <= 1'b1;
end else if ((w_op[4:0] == 5'h00)&&(~w_rB)&&(w_dcdA_pc))
begin // Add x,PC
r_early_branch <= 1'b1;
end else begin
r_early_branch <= 1'b0;
end
end else begin
if (i_ce)
r_early_branch <= 1'b0;
end
always @(posedge i_clk)
if (i_ce)
begin
if (w_op[4:1] == 4'hb)
r_branch_pc <= {{(AW-23){w_I[22]}},w_I};
else
r_branch_pc <= i_pc+{{(AW-23){w_I[22]}},w_I}
+{{(AW-1){1'b0}},1'b1};
end
 
assign o_early_branch = r_early_branch;
assign o_branch_pc = r_branch_pc;
end else begin
assign o_early_branch = 1'b0;
assign o_branch_pc = {(AW){1'b0}};
end endgenerate
 
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
 
endmodule
/memops.v
15,7 → 15,7
// error signal).
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
37,7 → 37,7
//
///////////////////////////////////////////////////////////////////////////
//
module memops(i_clk, i_rst, i_stb,
module memops(i_clk, i_rst, i_stb, i_lock,
i_op, i_addr, i_data, i_oreg,
o_busy, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
44,9 → 44,9
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
input i_clk, i_rst;
input i_stb;
input i_stb, i_lock;
// CPU interface
input i_op;
input [31:0] i_addr;
59,8 → 59,11
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output reg o_wb_cyc_gbl, o_wb_stb_gbl;
output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl;
output reg o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
// Wishbone inputs
67,26 → 70,29
input i_wb_ack, i_wb_stall, i_wb_err;
input [31:0] i_wb_data;
 
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
wire gbl_stb, lcl_stb;
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
 
initial r_wb_cyc_gbl = 1'b0;
initial r_wb_cyc_lcl = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
begin
if ((i_wb_ack)||(i_wb_err))
begin
o_wb_cyc_gbl <= 1'b0;
o_wb_cyc_lcl <= 1'b0;
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
end
end else if (i_stb) // New memory operation
begin // Grab the wishbone
o_wb_cyc_lcl <= lcl_stb;
o_wb_cyc_gbl <= gbl_stb;
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
end
always @(posedge i_clk)
if (o_wb_cyc_gbl)
120,4 → 126,25
always @(posedge i_clk)
if (i_wb_ack)
o_result <= i_wb_data;
 
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
 
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
 
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
end
 
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
endmodule
/prefetch.v
20,7 → 20,7
// can trap on it if necessary.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
47,18 → 47,18
// mode which this prefetch does not support. In non--pipelined mode, the
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
// or 72 clocks to fetch one instruction.
module prefetch(i_clk, i_rst, i_ce, i_pc, i_aux,
module prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux,
o_i, o_pc, o_aux, o_valid, o_illegal,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
input i_clk, i_rst, i_ce;
input i_clk, i_rst, i_ce, i_stalled_n;
input [(AW-1):0] i_pc;
input [(AUX_WIDTH-1):0] i_aux;
output reg [31:0] o_i;
output reg [(AW-1):0] o_pc;
output reg [(AUX_WIDTH-1):0] o_aux;
output wire o_valid, o_illegal;
output reg o_valid, o_illegal;
// Wishbone outputs
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
96,7 → 96,7
 
always @(posedge i_clk)
if (i_rst) // Set the address to guarantee the result is invalid
o_wb_addr <= 1'b0;
o_wb_addr <= {(AW){1'b1}};
else if ((i_ce)&&(~o_wb_cyc))
o_wb_addr <= i_pc;
always @(posedge i_clk)
108,8 → 108,17
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
o_pc <= o_wb_addr;
initial o_valid = 1'b0;
initial o_illegal = 1'b0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
begin
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err);
o_illegal <= i_wb_err;
end else if (i_stalled_n)
begin
o_valid <= 1'b0;
o_illegal <= 1'b0;
end
 
assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc);
assign o_illegal = (o_wb_cyc)&&(i_wb_err);
 
endmodule
/div.v
0,0 → 1,135
///////////////////////////////////////////////////////////////////////////////
//
// Filename: div.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Provide an Integer divide capability to the Zip CPU.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////////
//
// `include "cpudefs.v"
//
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator,
o_busy, o_valid, o_err, o_quotient, o_flags);
parameter BW=32, LGBW = 5;
input i_clk, i_rst;
// Input parameters
input i_wr, i_signed;
input [(BW-1):0] i_numerator, i_denominator;
// Output parameters
output reg o_busy, o_valid, o_err;
output reg [(BW-1):0] o_quotient;
output wire [3:0] o_flags;
 
reg [(2*BW-2):0] r_divisor;
reg [(BW-1):0] r_dividend;
wire [(BW):0] diff; // , xdiff[(BW-1):0];
assign diff = r_dividend - r_divisor[(BW-1):0];
// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
 
reg r_sign, pre_sign, r_z, r_c;
reg [(LGBW):0] r_bit;
 
always @(posedge i_clk)
if (i_rst)
begin
o_busy <= 1'b0;
o_valid <= 1'b0;
end else if (i_wr)
begin
o_busy <= 1'b1;
o_valid <= 1'b0;
end else if (o_busy)
begin
if ((r_bit == 6'h0)||(o_err))
begin
o_busy <= 1'b0;
o_valid <= (o_err)||(~r_sign);
end
end else if (r_sign)
begin
// if (o_err), o_valid is already one.
// if not, o_valid has not yet become one.
o_valid <= (~o_err); // 1'b1;
// r_sign <= 1'b0;
end else begin
o_busy <= 1'b0;
o_valid <= 1'b0;
end
 
always @(posedge i_clk)
if((i_rst)||(o_valid))
o_err <= 1'b0;
else if (o_busy)
o_err <= (r_divisor == 0);
 
always @(posedge i_clk)
if (i_wr)
begin
o_quotient <= 0;
// r_bit <= { 1'b1, {(LGBW){1'b0}} };
r_bit <= { 1'b0, {(LGBW){1'b1}} };
r_divisor <= { i_denominator, {(BW-1){1'b0}} };
r_dividend <= i_numerator;
r_sign <= 1'b0;
pre_sign <= i_signed;
r_z <= 1'b1;
end else if (pre_sign)
begin
// r_bit <= r_bit - 1;
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));;
if (r_dividend[BW-1])
r_dividend <= -r_dividend;
if (r_divisor[(2*BW-2)])
r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
pre_sign <= 1'b0;
end else if (o_busy)
begin
r_bit <= r_bit - 1;
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
if (|r_divisor[(2*BW-2):(BW)])
begin
end else if (diff[BW])
begin
end else begin
r_dividend <= diff[(BW-1):0];
o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
r_z <= 1'b0;
end
end else if (r_sign)
begin
r_sign <= 1'b0;
o_quotient <= -o_quotient;
end
 
// Set Carry on an exact divide
wire w_n;
always @(posedge i_clk)
r_c <= (o_busy)&&((diff == 0)||(r_dividend == 0));
assign w_n = o_quotient[(BW-1)];
 
assign o_flags = { 1'b0, w_n, r_c, r_z };
endmodule
/pipefetch.v
26,7 → 26,7
// these exceptions yet.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
/cpuops.v
4,10 → 4,13
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:
// Purpose: This supports the instruction set reordering of operations
// created by the second generation instruction set, as well as
// the new operations of POPC (population count) and BREV (bit reversal).
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
29,7 → 32,7
//
///////////////////////////////////////////////////////////////////////////
//
module cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
module cpuops(i_clk,i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
o_illegal);
parameter IMPLEMENT_MPY = 1;
input i_clk, i_rst, i_ce;
54,16 → 57,36
assign w_lsr_result = (|i_b[31:5])? 33'h00
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
 
// Bit reversal pre-logic
wire [31:0] w_brev_result;
genvar k;
generate
for(k=0; k<32; k=k+1)
assign w_brev_result[k] = i_b[31-k];
endgenerate
 
// Popcount pre-logic
wire [31:0] w_popc_result;
assign w_popc_result[5:0]=
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]})
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]})
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]})
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]})
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]})
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]})
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]})
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]});
assign w_popc_result[31:6] = 26'h00;
 
// Prelogic for our flags registers
wire z, n, v;
reg c, pre_sign, set_ovfl;
always @(posedge i_clk)
if (i_ce)
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
&&(i_a[31] != i_b[31]))
||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
||(i_op == 4'hd) // LSL
||(i_op == 4'hf)); // LSR
if (i_ce) // 1 LUT
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
||(i_op == 4'h6) // LSL
||(i_op == 4'h5)); // LSR
 
 
// A 4-way multiplexer can be done in one 6-LUT.
80,20 → 103,22
pre_sign <= (i_a[31]);
c <= 1'b0;
casez(i_op)
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
4'b?001: o_c <= i_a & i_b; // BTST/And
// 4'h3: There's a hole here for the unimplemented MPYU,
// 4'h4: and here for the unimplemented MPYS
4'h5: o_c <= w_rol_result; // ROL
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'ha: { c, o_c } <= i_a + i_b; // Add
4'hb: o_c <= i_a | i_b; // Or
4'hc: o_c <= i_a ^ i_b; // Xor
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR
default: o_c <= i_b; // MOV, LDI
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
4'b0001: o_c <= i_a & i_b; // BTST/And
4'b0010:{c,o_c } <= i_a + i_b; // Add
4'b0011: o_c <= i_a | i_b; // Or
4'b0100: o_c <= i_a ^ i_b; // Xor
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
// 4'h1010: The unimplemented MPYU,
// 4'h1011: and here for the unimplemented MPYS
4'b1100: o_c <= w_brev_result; // BREV
4'b1101: o_c <= w_popc_result; // POPC
4'b1110: o_c <= w_rol_result; // ROL
default: o_c <= i_b; // MOV, LDI
endcase
end
end else begin
100,10 → 125,12
//
// Multiply pre-logic
//
wire signed_mpy;
assign signed_mpy = i_op[0];
wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
wire signed [33:0] w_mpy_result;
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
assign w_mpy_a_input ={ ((i_a[15])&&(signed_mpy)), i_a[15:0] };
assign w_mpy_b_input ={ ((i_b[15])&&(signed_mpy)), i_b[15:0] };
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
 
 
116,20 → 143,22
pre_sign <= (i_a[31]);
c <= 1'b0;
casez(i_op)
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
4'b?001: o_c <= i_a & i_b; // BTST/And
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
4'h5: o_c <= w_rol_result; // ROL
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'ha: { c, o_c } <= i_a + i_b; // Add
4'hb: o_c <= i_a | i_b; // Or
4'hc: o_c <= i_a ^ i_b; // Xor
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR
default: o_c <= i_b; // MOV, LDI
4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
4'b0001: o_c <= i_a & i_b; // BTST/And
4'b0010:{c,o_c } <= i_a + i_b; // Add
4'b0011: o_c <= i_a | i_b; // Or
4'b0100: o_c <= i_a ^ i_b; // Xor
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR
4'b0110:{c,o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR
4'b1000: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'b1010:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
4'b1011:{c,o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
4'b1100: o_c <= w_brev_result; // BREV
4'b1101: o_c <= w_popc_result; // POPC
4'b1110: o_c <= w_rol_result; // ROL
default: o_c <= i_b; // MOV, LDI
endcase
end
end endgenerate
/pfcache.v
0,0 → 1,204
////////////////////////////////////////////////////////////////////////////////
//
// Filename: pfcache2.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Keeping our CPU fed with instructions, at one per clock and
// with no stalls. An unusual feature of this cache is the
// requirement that the entire cache may be cleared (if necessary).
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache,
// i_early_branch, i_from_addr,
i_stall_n, i_pc, o_i, o_pc, o_v,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
o_illegal);
parameter LGCACHELEN = 8, ADDRESS_WIDTH=24,
CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH,
CW=LGCACHELEN, PW=LGCACHELEN-5;
input i_clk, i_rst, i_new_pc;
input i_clear_cache;
input i_stall_n;
input [(AW-1):0] i_pc;
output reg [(BUSW-1):0] o_i;
output reg [(AW-1):0] o_pc;
output wire o_v;
//
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output wire [(BUSW-1):0] o_wb_data;
//
input i_wb_ack, i_wb_stall, i_wb_err;
input [(BUSW-1):0] i_wb_data;
//
output reg o_illegal;
 
// Fixed bus outputs: we read from the bus only, never write.
// Thus the output data is ... irrelevant and don't care. We set it
// to zero just to set it to something.
assign o_wb_we = 1'b0;
assign o_wb_data = 0;
 
reg r_v;
(* ram_style = "distributed" *)
reg [(BUSW-1):0] cache [0:((1<<CW)-1)];
reg [(AW-CW-1):0] tags [0:((1<<(CW-PW))-1)];
reg [((1<<(CW-PW))-1):0] vmask;
 
reg [(AW-1):0] lastpc;
reg [(CW-1):0] rdaddr;
reg [(AW-1):CW] tagval;
reg [(AW-1):PW] lasttag, illegal_cache;
 
initial o_i = 32'h76_00_00_00; // A NOOP instruction
initial o_pc = 0;
always @(posedge i_clk)
if (~r_v)
begin
o_i <= cache[lastpc[(CW-1):0]];
o_pc <= lastpc;
end else if ((i_stall_n)||(i_new_pc))
begin
o_i <= cache[i_pc[(CW-1):0]];
o_pc <= i_pc;
end
 
initial tagval = 0;
always @(posedge i_clk)
if (i_stall_n)
tagval <= tags[i_pc[(CW-1):PW]];
 
// i_pc will only increment when everything else isn't stalled, thus
// we can set it without worrying about that. Doing this enables
// us to work in spite of stalls. For example, if the next address
// isn't valid, but the decoder is stalled, get the next address
// anyway.
initial lastpc = 0;
always @(posedge i_clk)
if ((r_v)||(i_clear_cache)||(i_new_pc))
lastpc <= i_pc;
 
initial lasttag = 0;
always @(posedge i_clk)
lasttag <= i_pc[(AW-1):PW];
 
wire r_v_from_pc, r_v_from_last;
assign r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag)
&&(tagval == i_pc[(AW-1):CW])
&&(vmask[i_pc[(CW-1):PW]]));
assign r_v_from_last = ((lastpc[(AW-1):PW] == lasttag)
&&(tagval == lastpc[(AW-1):CW])
&&(vmask[lastpc[(CW-1):PW]]));
 
reg [1:0] delay;
 
initial delay = 2'h3;
initial r_v = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache)||(i_new_pc)||(r_v))
begin
r_v <= r_v_from_pc;
delay <= 2'h2;
end else begin
r_v <= r_v_from_last;
if (o_wb_cyc)
delay <= 2'h2;
else if (delay != 0)
delay <= delay - 1;
end
 
assign o_v = (r_v)&&(~i_new_pc);
 
 
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
initial o_wb_addr = {(AW){1'b0}};
initial rdaddr = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end else if (o_wb_cyc)
begin
if ((o_wb_stb)&&(~i_wb_stall))
begin
if (o_wb_addr[(PW-1):0] == {(PW){1'b1}})
o_wb_stb <= 1'b0;
else
o_wb_addr[(PW-1):0] <= o_wb_addr[(PW-1):0]+1;
end
 
if (i_wb_ack)
rdaddr <= rdaddr + 1;
if ((rdaddr[(PW-1):0] == {(PW){1'b1}})||(i_wb_err))
begin
o_wb_cyc <= 1'b0;
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW];
end
// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}})
// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW];
 
end else if ((~r_v)&&(delay==0)
&&((tagval != lastpc[(AW-1):CW])
||(~vmask[lastpc[(CW-1):PW]])))
begin
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
o_wb_addr <= { lastpc[(AW-1):PW], {(PW){1'b0}} };
rdaddr <= { lastpc[(CW-1):PW], {(PW){1'b0}} };
end
 
// Can't initialize an array, so leave cache uninitialized
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
cache[rdaddr] <= i_wb_data;
 
// VMask ... is a section loaded?
initial vmask = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
vmask <= 0;
else if ((~r_v)&&(tagval != lastpc[(AW-1):CW])&&(delay == 0))
vmask[lastpc[(CW-1):PW]] <= 1'b0;
else if ((o_wb_cyc)&&(i_wb_ack)&&(rdaddr[(PW-1):0] == {(PW){1'b1}}))
vmask[rdaddr[(CW-1):PW]] <= 1'b1;
 
initial illegal_cache = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache))
illegal_cache <= 0;
else if ((o_wb_cyc)&&(i_wb_err))
illegal_cache <= lastpc[(AW-1):PW];
 
initial o_illegal = 1'b0;
always @(posedge i_clk)
if (i_stall_n)
o_illegal <= (illegal_cache == lastpc[(AW-1):PW]);
 
endmodule
/cpuops_deprecated.v
0,0 → 1,164
///////////////////////////////////////////////////////////////////////////
//
// Filename: cpuops_deprecated.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This is the ALU within the Zip CPU. This particular version,
// however, has been deprecated in favor of the newer instruction
// set. The primary difference is that this instruction set doesn't
// offer the bit reversal or population count instructions, and the
// newer ALU reorders the opcodes.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
module cpuops_deprecated(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b,
o_c, o_f, o_valid, o_illegal);
parameter IMPLEMENT_MPY = 1;
input i_clk, i_rst, i_ce;
input [3:0] i_op;
input [31:0] i_a, i_b;
input i_valid;
output reg [31:0] o_c;
output wire [3:0] o_f;
output reg o_valid;
output wire o_illegal;
 
// Rotate-left pre-logic
wire [63:0] w_rol_tmp;
assign w_rol_tmp = { i_a, i_a } << i_b[4:0];
wire [31:0] w_rol_result;
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags
 
// Shift register pre-logic
wire [32:0] w_lsr_result, w_asr_result;
assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
: ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
assign w_lsr_result = (|i_b[31:5])? 33'h00
: ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
 
 
wire z, n, v;
reg c, pre_sign, set_ovfl;
always @(posedge i_clk)
if (i_ce)
set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
&&(i_a[31] != i_b[31]))
||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
||(i_op == 4'hd) // LSL
||(i_op == 4'hf)); // LSR
 
 
// A 4-way multiplexer can be done in one 6-LUT.
// A 16-way multiplexer can therefore be done in 4x 6-LUT's with
// the Xilinx multiplexer fabric that follows.
// Given that we wish to apply this multiplexer approach to 33-bits,
// this will cost a minimum of 132 6-LUTs.
generate
if (IMPLEMENT_MPY == 0)
begin
always @(posedge i_clk)
if (i_ce)
begin
pre_sign <= (i_a[31]);
c <= 1'b0;
casez(i_op)
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
4'b?001: o_c <= i_a & i_b; // BTST/And
// 4'h3: There's a hole here for the unimplemented MPYU,
// 4'h4: and here for the unimplemented MPYS
4'h5: o_c <= w_rol_result; // ROL
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'ha: { c, o_c } <= i_a + i_b; // Add
4'hb: o_c <= i_a | i_b; // Or
4'hc: o_c <= i_a ^ i_b; // Xor
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR
default: o_c <= i_b; // MOV, LDI
endcase
end
end else begin
//
// Multiply pre-logic
//
wire signed [16:0] w_mpy_a_input, w_mpy_b_input;
wire signed [33:0] w_mpy_result;
assign w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
assign w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
assign w_mpy_result = w_mpy_a_input * w_mpy_b_input;
 
 
//
// The master ALU case statement
//
always @(posedge i_clk)
if (i_ce)
begin
pre_sign <= (i_a[31]);
c <= 1'b0;
casez(i_op)
4'b?000:{c,o_c } <= {1'b0,i_a} - {1'b0,i_b};// CMP/SUB
4'b?001: o_c <= i_a & i_b; // BTST/And
4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU
4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYS
4'h5: o_c <= w_rol_result; // ROL
4'h6: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO
4'h7: o_c <= { i_b[15: 0], i_a[15:0] }; // LODIHI
4'ha: { c, o_c } <= i_a + i_b; // Add
4'hb: o_c <= i_a | i_b; // Or
4'hc: o_c <= i_a ^ i_b; // Xor
4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0]; // LSL
4'he: { o_c, c } <= w_asr_result[32:0]; // ASR
4'hf: { o_c, c } <= w_lsr_result[32:0]; // LSR
default: o_c <= i_b; // MOV, LDI
endcase
end
end endgenerate
 
generate
if (IMPLEMENT_MPY == 0)
begin
reg r_illegal;
always @(posedge i_clk)
r_illegal <= (i_ce)&&((i_op == 4'h3)||(i_op == 4'h4));
assign o_illegal = r_illegal;
end else
assign o_illegal = 1'b0;
endgenerate
 
assign z = (o_c == 32'h0000);
assign n = (o_c[31]);
assign v = (set_ovfl)&&(pre_sign != o_c[31]);
 
assign o_f = { v, n, c, z };
 
initial o_valid = 1'b0;
always @(posedge i_clk)
if (i_rst)
o_valid <= 1'b0;
else
o_valid <= (i_ce)&&(i_valid);
endmodule
/zipcpu.v
32,8 → 32,42
// to the spec.pdf for accurate and up to date information.)
//
//
// In general, the pipelining is controlled by three pieces of logic
// per stage: _ce, _stall, and _valid. _valid means that the stage
// holds a valid instruction. _ce means that the instruction from the
// previous stage is to move into this one, and _stall means that the
// instruction from the previous stage may not move into this one.
// The difference between these control signals allows individual stages
// to propagate instructions independently. In general, the logic works
// as:
//
//
// assign (n)_ce = (n-1)_valid && (~(n)_stall)
//
//
// always @(posedge i_clk)
// if ((i_rst)||(clear_pipeline))
// (n)_valid = 0
// else if (n)_ce
// (n)_valid = 1
// else if (n+1)_ce
// (n)_valid = 0
//
// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) )
// || ( (n)_valid && (n+1)_stall );
//
// and ...
//
// always @(posedge i_clk)
// if (n)_ce
// (n)_variable = ... whatever logic for this stage
//
// Note that a stage can stall even if no instruction is loaded into
// it.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Tecnology, LLC
// Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
69,11 → 103,13
//
`define CPU_CC_REG 4'he
`define CPU_PC_REG 4'hf
`define CPU_BUSERR_BIT 10
`define CPU_TRAP_BIT 9
`define CPU_ILL_BIT 8
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error
`define CPU_TRAP_BIT 9 // User TRAP has taken place
`define CPU_ILL_BIT 8 // Illegal instruction
`define CPU_BREAK_BIT 7
`define CPU_STEP_BIT 6
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions
`define CPU_GIE_BIT 5
`define CPU_SLEEP_BIT 4
// Compile time defines
81,11 → 117,6
`include "cpudefs.v"
//
//
//
// `define DEBUG_SCOPE
//
//
//
module zipcpu(i_clk, i_rst, i_interrupt,
// Debug interface
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
104,12 → 135,20
`endif
);
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
LGICACHE=6, AW=ADDRESS_WIDTH;
LGICACHE=6;
`ifdef OPT_MULTIPLY
parameter IMPLEMENT_MPY = 1;
`else
parameter IMPLEMENT_MPY = 0;
`endif
parameter IMPLEMENT_DIVIDE = 1, IMPLEMENT_FPU = 0,
IMPLEMENT_LOCK=1;
`ifdef OPT_EARLY_BRANCHING
parameter EARLY_BRANCHING = 1;
`else
parameter EARLY_BRANCHING = 0;
`endif
parameter AW=ADDRESS_WIDTH;
input i_clk, i_rst, i_interrupt;
// Debug interface -- inputs
input i_halt, i_clear_pf_cache;
155,7 → 194,7
// Condition codes
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
reg [3:0] flags, iflags;
wire [10:0] w_uflags, w_iflags;
wire [12:0] w_uflags, w_iflags;
reg trap, break_en, step, gie, sleep;
`ifdef OPT_ILLEGAL_INSTRUCTION
reg ill_err_u, ill_err_i;
163,6 → 202,9
wire ill_err_u, ill_err_i;
`endif
reg ibus_err_flag, ubus_err_flag;
wire idiv_err_flag, udiv_err_flag;
wire ifpu_err_flag, ufpu_err_flag;
wire ihalt_phase, uhalt_phase;
 
// The master chip enable
wire master_ce;
173,9 → 215,9
// Variable declarations
//
reg [(AW-1):0] pf_pc;
reg new_pc, op_break;
reg new_pc;
wire clear_pipeline;
assign clear_pipeline = new_pc || i_clear_pf_cache; // || op_break;
assign clear_pipeline = new_pc || i_clear_pf_cache;
 
wire dcd_stalled;
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
192,33 → 234,25
//
//
reg opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
wire op_stall, dcd_ce;
reg [3:0] dcdOp;
reg [4:0] dcdA, dcdB;
reg dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
reg [3:0] dcdF;
reg dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
dcdM, dcdF_wr, dcd_gie, dcd_break;
reg [(AW-1):0] dcd_pc;
reg [23:0] r_dcdI;
`ifdef OPT_SINGLE_CYCLE
reg dcd_zI; // true if dcdI == 0
`endif
reg opvalid_div, opvalid_fpu;
wire op_stall, dcd_ce, dcd_phase;
wire [3:0] dcdOp;
wire [4:0] dcdA, dcdB, dcdR;
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
wire [3:0] dcdF;
wire dcdR_wr, dcdA_rd, dcdB_rd,
dcdALU, dcdM, dcdDV, dcdFP,
dcdF_wr, dcd_gie, dcd_break, dcd_lock;
reg r_dcdvalid;
wire dcdvalid;
wire [(AW-1):0] dcd_pc;
wire [31:0] dcdI;
wire dcd_zI; // true if dcdI == 0
wire dcdA_stall, dcdB_stall, dcdF_stall;
 
`ifdef OPT_PRECLEAR_BUS
reg dcd_clear_bus;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
reg dcd_illegal;
`endif
`ifdef OPT_EARLY_BRANCHING
reg dcd_early_branch_stb, dcd_early_branch;
reg [(AW-1):0] dcd_branch_pc;
`else
wire dcd_early_branch_stb, dcd_early_branch;
wire dcd_illegal;
wire dcd_early_branch;
wire [(AW-1):0] dcd_branch_pc;
`endif
 
 
//
237,22 → 271,21
wire [31:0] w_opA, w_opB;
wire [31:0] opA_nowait, opB_nowait, opA, opB;
reg opR_wr, opR_cc, opF_wr, op_gie;
wire [10:0] opFl;
wire [12:0] opFl;
reg [5:0] r_opF;
wire [7:0] opF;
reg [2:0] opF_cp;
wire op_ce;
wire op_ce, op_phase;
// Some pipeline control wires
`ifdef OPT_SINGLE_CYCLE
`ifdef OPT_PIPELINED
reg opA_alu, opA_mem;
reg opB_alu, opB_mem;
`endif
`ifdef OPT_PRECLEAR_BUS
reg op_clear_bus;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
reg op_illegal;
`endif
reg op_break;
wire op_lock;
 
 
//
262,7 → 295,8
//
//
reg [(AW-1):0] alu_pc;
reg alu_pc_valid;;
reg alu_pc_valid;
wire alu_phase;
wire alu_ce, alu_stall;
wire [31:0] alu_result;
wire [3:0] alu_flags;
287,8 → 321,23
wire [31:0] mem_data, mem_result;
reg [4:0] mem_last_reg; // Last register result to go in
 
wire div_ce, div_error, div_busy, div_valid;
wire [31:0] div_result;
wire [3:0] div_flags;
 
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
&&(set_cond);
 
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
wire [31:0] fpu_result;
wire [3:0] fpu_flags;
 
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
&&(set_cond);
 
 
//
//
// PIPELINE STAGE #5 :: Write-back
318,37 → 367,68
//
// PIPELINE STAGE #2 :: Instruction Decode
// Calculate stall conditions
assign dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
assign dcd_stalled = (dcdvalid)&&(
(op_stall)
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
||((opvalid_mem)&&(op_wr_pc))
||((opvalid_mem)&&(opR_cc)));
`ifdef OPT_PIPELINED
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
`else
assign dcd_ce = 1'b1;
`endif
`ifdef OPT_PIPELINED
assign dcd_stalled = (dcdvalid)&&(op_stall);
`else
// If not pipelined, there will be no opvalid_ anything, and the
// op_stall will be false, dcdX_stall will be false, thus we can simply
// do a ...
assign dcd_stalled = 1'b0;
`endif
//
// PIPELINE STAGE #3 :: Read Operands
// Calculate stall conditions
assign op_stall = ((opvalid)&&(~master_ce))||(
wire op_lock_stall;
`ifdef OPT_PIPELINED
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
// Stall if we're stopped, and not allowed to execute
// an instruction
// (~master_ce) // Already captured in alu_stall
//
// Stall if going into the ALU and the ALU is stalled
// i.e. if the memory is busy, or we are single
// stepping
((opvalid_alu)&&(alu_stall))
// stepping. This also includes our stalls for
// op_break and op_lock, so we don't need to
// include those as well here.
((opvalid)&&(alu_stall))
// Stall if the divide is busy, since we can't have
// two parallel stages writing back at the same time
||(div_busy)
// Same for the floating point unit
||(fpu_busy)
//
// ||((opvalid_alu)&&(mem_rdbusy)) // part of alu_stall
// Stall if we are going into memory with an operation
// that cannot be pipelined, and the memory is
// already busy
`ifdef OPT_PIPELINED_BUS_ACCESS
||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
//
// Stall if we are going into memory with a pipeable
// operation, but the memory unit declares it is
// not going to accept any more pipeline operations
||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled))
||((opvalid_mem)&&(mem_stalled))
)
||(dcdvalid)&&(
// Stall if we've got a read going with an
// unknown output (known w/in the memory module)
(mem_rdbusy)
// Or if we need to wait for an operand A
// to be ready to read
||(dcdA_stall)
// Likewise for B, also includes logic
// regarding immediate offset (register must
// be in register file if we need to add to
// an immediate)
||(dcdB_stall)
// Or if we need to wait on flags to work on the
// CC register
||(dcdF_stall)
);
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall))&&(~clear_pipeline);
`else
||((opvalid_mem)&&(mem_busy))
assign op_stall = (opvalid)&&(~master_ce);
assign op_ce = (dcdvalid);
`endif
);
assign op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
 
//
// PIPELINE STAGE #4 :: ALU / Memory
363,12 → 443,22
// 4. Last case: Stall if we would otherwise move a break instruction
// through the ALU. Break instructions are not allowed through
// the ALU.
`ifdef OPT_PIPELINED
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
// Old case #3--this isn't an ALU stall though ...
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&(wr_write_cc)) // Case 3
||((opvalid_alu)&&(op_break)); // Case 3
assign alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
||((opvalid)&&(op_lock)&&(op_lock_stall))
||((opvalid)&&(op_break))
||(div_busy)||(fpu_busy);
assign alu_ce = (master_ce)&&(opvalid_alu)
&&(~alu_stall)
&&(~clear_pipeline);
`else
assign alu_stall = ((~master_ce)&&(opvalid_alu))
||((opvalid_alu)&&(op_break));
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall);
`endif
//
 
//
375,12 → 465,22
// Note: if you change the conditions for mem_ce, you must also change
// alu_pc_valid.
//
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
`ifdef OPT_PIPELINED
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
&&(~clear_pipeline)&&(set_cond);
`else
// If we aren't pipelined, then no one will be changing what's in the
// pipeline (i.e. clear_pipeline), while our only instruction goes
// through the ... pipeline.
assign mem_ce = (master_ce)&&(opvalid_mem)
&&(set_cond)&&(~mem_stalled);
`endif
`ifdef OPT_PIPELINED_BUS_ACCESS
assign mem_stalled = (~master_ce)||((opvalid_mem)&&(
(mem_pipe_stalled)
||((~op_pipe)&&(mem_busy))
||(div_busy)
||(fpu_busy)
// Stall waiting for flags to be valid
// Or waiting for a write to the PC register
// Or CC register, since that can change the
388,6 → 488,7
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&((wr_write_pc)||(wr_write_cc)))));
`else
`ifdef OPT_PIPELINED
assign mem_stalled = (mem_busy)||((opvalid_mem)&&(
(~master_ce)
// Stall waiting for flags to be valid
395,7 → 496,10
// Or CC register, since that can change the
// PC as well
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
`else
assign mem_stalled = (opvalid_mem)&&(~master_ce);
`endif
`endif
 
 
//
406,276 → 510,100
`ifdef OPT_SINGLE_FETCH
wire pf_ce;
 
assign pf_ce = (~dcd_stalled);
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
prefetch #(ADDRESS_WIDTH)
pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
instruction, instruction_pc, instruction_gie,
pf_valid, pf_illegal,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data);
 
initial r_dcdvalid = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_dcdvalid <= 1'b0;
else if (dcd_ce)
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
else if ((op_ce)||(clear_pipeline))
r_dcdvalid <= 1'b0;
assign dcdvalid = r_dcdvalid;
 
`else // Pipe fetch
 
`ifdef OPT_TRADITIONAL_PFCACHE
pfcache #(LGICACHE, ADDRESS_WIDTH)
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
i_clear_pf_cache,
// dcd_pc,
~dcd_stalled,
((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
? dcd_branch_pc:pf_pc,
instruction, instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
pf_illegal);
`else
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
i_clear_pf_cache, ~dcd_stalled,
(new_pc)?pf_pc:dcd_branch_pc,
instruction, instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
`ifdef OPT_PRECLEAR_BUS
((dcd_clear_bus)&&(dcdvalid))
||((op_clear_bus)&&(opvalid))
||
`endif
//`ifdef OPT_PRECLEAR_BUS
//((dcd_clear_bus)&&(dcdvalid))
//||((op_clear_bus)&&(opvalid))
//||
//`endif
(mem_cyc_lcl)||(mem_cyc_gbl),
pf_illegal);
`endif
assign instruction_gie = gie;
`endif
 
initial dcdvalid = 1'b0;
initial r_dcdvalid = 1'b0;
always @(posedge i_clk)
if (i_rst)
dcdvalid <= 1'b0;
if ((i_rst)||(clear_pipeline))
r_dcdvalid <= 1'b0;
else if (dcd_ce)
dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
dcdvalid <= 1'b0;
 
`ifdef OPT_EARLY_BRANCHING
always @(posedge i_clk)
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(master_ce))
begin
dcd_early_branch <= 1'b0;
// First case, a move to PC instruction
if ((instruction[31:28] == 4'h2)
// Offsets of the PC register *only*
&&(instruction[19:16] == `CPU_PC_REG)
&&((instruction_gie)
||((~instruction[20])&&(~instruction[15])))
&&(instruction[23:21]==3'h0)) // Unconditional
begin
dcd_early_branch_stb <= 1'b1;
dcd_early_branch <= 1'b1;
// r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
end else // Next case, an Add Imm -> PC instruction
if ((instruction[31:28] == 4'ha) // Add
&&(~instruction[20]) // Immediate
&&(instruction[23:21]==3'h0)) // Always
begin
dcd_early_branch_stb <= 1'b1;
dcd_early_branch <= 1'b1;
// r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
end else // Next case: load Immediate to PC
if (instruction[31:28] == 4'h3)
begin
dcd_early_branch_stb <= 1'b1;
dcd_early_branch <= 1'b1;
// r_dcdI <= { instruction[23:0] };
end
end else
begin
if (dcd_ce) dcd_early_branch <= 1'b0;
dcd_early_branch_stb <= 1'b0;
end
generate
if (AW == 24)
begin
always @(posedge i_clk)
if (dcd_ce)
begin
if (instruction[31]) // Add
begin
dcd_branch_pc <= instruction_pc
+ { {(AW-20){instruction[19]}}, instruction[19:0] }
+ {{(AW-1){1'b0}},1'b1};
end else if (~instruction[28]) // 4'h2 = MOV
dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
else // if (instruction[28]) // 4'h3 = LDI
dcd_branch_pc <= instruction_pc+{ instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
end
end else begin
always @(posedge i_clk)
if (dcd_ce)
begin
if (instruction[31]) // Add
begin
dcd_branch_pc <= instruction_pc
+ { {(AW-20){instruction[19]}}, instruction[19:0] }
+ {{(AW-1){1'b0}},1'b1};
end else if (~instruction[28]) // 4'h2 = MOV
begin
dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};
end else // if (instruction[28]) // 4'h3 = LDI
begin
dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};
end
end
end endgenerate
`else // OPT_EARLY_BRANCHING
assign dcd_early_branch_stb = 1'b0;
assign dcd_early_branch = 1'b0;
assign dcd_branch_pc = {(AW){1'b0}};
`endif // OPT_EARLY_BRANCHING
 
always @(posedge i_clk)
if (dcd_ce)
begin
dcd_pc <= instruction_pc
+{{(AW-1){1'b0}},1'b1}; // i.e. dcd_pc+1
 
// Record what operation we are doing
dcdOp <= instruction[31:28];
 
// Default values
dcdA[4:0] <= { instruction_gie, instruction[27:24] };
dcdB[4:0] <= { instruction_gie, instruction[19:16] };
dcdA_cc <= (instruction[27:24] == `CPU_CC_REG);
dcdB_cc <= (instruction[19:16] == `CPU_CC_REG);
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG);
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG);
dcdM <= 1'b0;
`ifdef OPT_CONDITIONAL_FLAGS
// Don't change the flags on conditional instructions,
// UNLESS: the conditional instruction was a CMP
// or TST instruction.
dcdF_wr <= ((instruction[23:21]==3'h0)
||(instruction[31:29] == 3'h0));
`else
dcdF_wr <= 1'b1;
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
else if (op_ce)
r_dcdvalid <= 1'b0;
assign dcdvalid = r_dcdvalid;
`endif
`ifdef OPT_PRECLEAR_BUS
dcd_clear_bus <= 1'b0;
`endif
`ifdef OPT_ILLEGAL_INSTRUCTION
dcd_illegal <= pf_illegal;
`endif
 
// Set the condition under which we do this operation
// The top four bits are a mask, the bottom four the
// value the flags must equal once anded with the mask
dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
casez(instruction[31:28])
4'h2: begin // Move instruction
if (~instruction_gie)
begin
dcdA[4] <= instruction[20];
dcdB[4] <= instruction[15];
end
dcdA_wr <= 1'b1;
dcdA_rd <= 1'b0;
dcdB_rd <= 1'b1;
r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[14:0] == 0);
`endif
dcdF_wr <= 1'b0; // Don't write flags
end
4'h3: begin // Load immediate
dcdA_wr <= 1'b1;
dcdA_rd <= 1'b0;
dcdB_rd <= 1'b0;
r_dcdI <= { instruction[23:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[23:0] == 0);
`endif
dcdF_wr <= 1'b0; // Don't write flags
dcdF <= 4'h8; // This is unconditional
dcdOp <= 4'h2;
end
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
`ifdef OPT_CONDITIONAL_FLAGS
// Don't write flags except for multiplies
// and then only if they are unconditional
dcdF_wr <= ((instruction[27:25] != 3'h7)
&&(instruction[23:21]==3'h0));
`ifdef OPT_NEW_INSTRUCTION_SET
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
IMPLEMENT_FPU)
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
dcd_ce, dcd_stalled, instruction, instruction_gie,
instruction_pc, pf_valid, pf_illegal, dcd_phase,
dcd_illegal, dcd_pc, dcd_gie,
{ dcdR_cc, dcdR_pc, dcdR },
{ dcdA_cc, dcdA_pc, dcdA },
{ dcdB_cc, dcdB_pc, dcdB },
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
dcdR_wr,dcdA_rd, dcdB_rd,
dcd_early_branch,
dcd_branch_pc);
`else
// Don't write flags except for multiplies
dcdF_wr <= (instruction[27:25] != 3'h7);
idecode_deprecated
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
IMPLEMENT_FPU)
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
dcd_ce, dcd_stalled, instruction, instruction_gie,
instruction_pc, pf_valid, pf_illegal, dcd_phase,
dcd_illegal, dcd_pc, dcd_gie,
{ dcdR_cc, dcdR_pc, dcdR },
{ dcdA_cc, dcdA_pc, dcdA },
{ dcdB_cc, dcdB_pc, dcdB },
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
dcdR_wr,dcdA_rd, dcdB_rd,
dcd_early_branch,
dcd_branch_pc);
`endif
r_dcdI <= { 8'h00, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
if (instruction[27:24] == 4'he)
begin
// NOOP instruction
dcdA_wr <= 1'b0;
dcdA_rd <= 1'b0;
dcdB_rd <= 1'b0;
dcdOp <= 4'h2;
// Might also be a break. Big
// instruction set hole here.
`ifdef OPT_ILLEGAL_INSTRUCTION
dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
`endif
end else if (instruction[27:24] == 4'hf)
begin // Load partial immediate(s)
dcdA_wr <= 1'b1;
dcdA_rd <= 1'b1;
dcdB_rd <= 1'b0;
dcdA[4:0] <= { instruction_gie, instruction[19:16] };
dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
dcdOp <= { 3'h3, instruction[20] };
end else begin
// Actual multiply instruction
r_dcdI <= { 8'h00, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
dcdA_rd <= 1'b1;
dcdB_rd <= (instruction[19:16] != 4'hf);
dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
end end
4'b011?: begin // LOD/STO or Load/Store
dcdF_wr <= 1'b0; // Don't write flags
dcdA_wr <= (~instruction[28]); // Write on loads
dcdA_rd <= (instruction[28]); // Read on stores
dcdB_rd <= instruction[20];
if (instruction[20])
begin
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
end else begin
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[19:0] == 0);
`endif
end
dcdM <= 1'b1; // Memory operation
`ifdef OPT_PRECLEAR_BUS
dcd_clear_bus <= (instruction[23:21]==3'h0);
`endif
end
default: begin
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
dcdA_rd <= 1'b1;
dcdB_rd <= instruction[20];
if (instruction[20])
begin
r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[15:0] == 0);
`endif
end else begin
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
`ifdef OPT_SINGLE_CYCLE
dcd_zI <= (instruction[19:0] == 0);
`endif
end end
endcase
 
 
dcd_gie <= instruction_gie;
end
always @(posedge i_clk)
if (dcd_ce)
dcd_break <= (instruction[31:0] == 32'h4e000001);
else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
dcd_break <= 1'b0;
 
`ifdef OPT_PIPELINED_BUS_ACCESS
reg [23:0] r_opI;
reg [4:0] op_B;
695,10 → 623,10
&&(dcdB == op_B) // Same address register
&&((dcdF[2:0] == opF_cp) // Same condition
||(opF_cp == 3'h0)) // or no prev condition
&&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
&&((dcdI[23:0] == r_opI)||(dcdI[23:0]==r_opI+24'h1));
always @(posedge i_clk)
if (op_ce) // &&(dcdvalid))
r_opI <= r_dcdI;
r_opI <= dcdI[23:0];
always @(posedge i_clk)
if (op_ce) // &&(dcdvalid))
op_B <= dcdB;
727,10 → 655,10
else if (dcdA_pc)
r_opA <= w_pcA_v;
else if (dcdA_cc)
r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
r_opA <= { w_opA[31:13], (dcdA[4])?w_uflags:w_iflags };
else
r_opA <= w_opA;
`ifdef OPT_SINGLE_CYCLE
`ifdef OPT_PIPELINED
end else if (opvalid)
begin // We were going to pick these up when they became valid,
// but for some reason we're stuck here as they became
740,8 → 668,7
`endif
end
 
wire [31:0] dcdI, w_opBnI, w_pcB_v;
assign dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
wire [31:0] w_opBnI, w_pcB_v;
generate
if (AW < 32)
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
752,13 → 679,13
assign w_opBnI = (~dcdB_rd) ? 32'h00
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
: ((dcdB_pc) ? w_pcB_v
: ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
: ((dcdB_cc) ? { w_opB[31:13], (dcdB[4])?w_uflags:w_iflags}
: w_opB)));
 
always @(posedge i_clk)
if (op_ce) // &&(dcdvalid))
r_opB <= w_opBnI + dcdI;
`ifdef OPT_SINGLE_CYCLE
`ifdef OPT_PIPELINED
else if ((opvalid)&&(
((opB_alu)&&(alu_wr))
||((opB_mem)&&(mem_valid))))
779,11 → 706,23
begin // Set the flag condition codes, bit order is [3:0]=VNCZ
case(dcdF[2:0])
3'h0: r_opF <= 6'h00; // Always
`ifdef OPT_NEW_INSTRUCTION_SET
// These were remapped as part of the new instruction
// set in order to make certain that the low order
// two bits contained the most commonly used
// conditions: Always, LT, Z, and NZ.
3'h1: r_opF <= 6'h24; // LT
3'h2: r_opF <= 6'h11; // Z
3'h3: r_opF <= 6'h10; // NE
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
3'h5: r_opF <= 6'h20; // GE (!N)
`else
3'h1: r_opF <= 6'h11; // Z
3'h2: r_opF <= 6'h10; // NE
3'h3: r_opF <= 6'h20; // GE (!N)
3'h4: r_opF <= 6'h30; // GT (!N&!Z)
3'h5: r_opF <= 6'h24; // LT
`endif
3'h6: r_opF <= 6'h02; // C
3'h7: r_opF <= 6'h08; // V
endcase
793,6 → 732,8
if (op_ce)
opF_cp[2:0] <= dcdF[2:0];
 
wire w_opvalid;
assign w_opvalid = (~clear_pipeline)&&(dcdvalid);
initial opvalid = 1'b0;
initial opvalid_alu = 1'b0;
initial opvalid_mem = 1'b0;
812,19 → 753,25
// Hence, the test on dcd_stalled here. If we must
// wait until our operands are valid, then we aren't
// valid yet until then.
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid<= w_opvalid;
`ifdef OPT_ILLEGAL_INSTRUCTION
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
`else
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
opvalid_alu <= (dcdALU)&&(w_opvalid);
opvalid_mem <= (dcdM)&&(w_opvalid);
opvalid_div <= (dcdDV)&&(w_opvalid);
opvalid_fpu <= (dcdFP)&&(w_opvalid);
`endif
end else if ((~op_stall)||(clear_pipeline))
end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
begin
opvalid <= 1'b0;
opvalid_alu <= 1'b0;
opvalid_mem <= 1'b0;
opvalid_div <= 1'b0;
opvalid_fpu <= 1'b0;
end
 
// Here's part of our debug interface. When we recognize a break
843,47 → 790,109
else if ((clear_pipeline)||(~opvalid))
op_break <= 1'b0;
 
`ifdef OPT_PIPELINED
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_op_lock, r_op_lock_stall;
 
initial r_op_lock_stall = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_op_lock_stall <= 1'b0;
else
r_op_lock_stall <= (~opvalid)||(~op_lock)
||(~dcdvalid)||(~pf_valid);
 
assign op_lock_stall = r_op_lock_stall;
 
initial r_op_lock = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_op_lock <= 1'b0;
else if ((op_ce)&&(dcd_lock))
r_op_lock <= 1'b1;
else if ((op_ce)||(clear_pipeline))
r_op_lock <= 1'b0;
assign op_lock = r_op_lock;
 
end else begin
assign op_lock_stall = 1'b0;
assign op_lock = 1'b0;
end endgenerate
 
`else
assign op_lock_stall = 1'b0;
assign op_lock = 1'b0;
`endif
 
`ifdef OPT_ILLEGAL_INSTRUCTION
always @(posedge i_clk)
if(op_ce)
op_illegal <= dcd_illegal;
`ifdef OPT_PIPELINED
op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
`else
op_illegal <= (dcd_illegal)||(dcd_lock);
`endif
`endif
 
generate
if (EARLY_BRANCHING > 0)
begin
always @(posedge i_clk)
if (op_ce)
begin
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))&&(~dcd_early_branch);
opR_wr <= (dcdR_wr)&&(~dcd_early_branch);
op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
&&(dcdR[4] == dcd_gie))
&&(~dcd_early_branch);
end
end else begin
always @(posedge i_clk)
if (op_ce)
begin
// Will we write the flags/CC Register with
// our result?
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr));
// Will we be writing our results into a
// register?
opR_wr <= dcdR_wr;
op_wr_pc <= ((dcdR_wr)&&(dcdR_pc)
&&(dcdR[4] == dcd_gie));
end
end endgenerate
 
always @(posedge i_clk)
if (op_ce)
begin
opn <= dcdOp; // Which ALU operation?
// opM <= dcdM; // Is this a memory operation?
`ifdef OPT_EARLY_BRANCHING
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
`else
// Will we write the flags/CC Register with our result?
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
// Will we be writing our results into a register?
opR_wr <= dcdA_wr;
`endif
// What register will these results be written into?
opR <= dcdA;
opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
opR <= dcdR;
opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
// User level (1), vs supervisor (0)/interrupts disabled
op_gie <= dcd_gie;
 
 
//
`ifdef OPT_EARLY_BRANCHING
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
`else
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
`endif
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
// op_pc <= dcd_pc;
 
`ifdef OPT_PRECLEAR_BUS
op_clear_bus <= dcd_clear_bus;
`endif
end
assign opFl = (op_gie)?(w_uflags):(w_iflags);
 
`ifdef OPT_VLIW
reg r_op_phase;
initial r_op_phase = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(clear_pipeline))
r_op_phase <= 1'b0;
else if (op_ce)
r_op_phase <= dcd_phase;
assign op_phase = r_op_phase;
`else
assign op_phase = 1'b0;
`endif
 
// This is tricky. First, the PC and Flags registers aren't kept in
// register set but in special registers of their own. So step one
// is to select the right register. Step to is to replace that
896,7 → 905,7
// We'll create a flag here to start our coordination. Once we
// define this flag to something other than just plain zero, then
// the stalls will already be in place.
`ifdef OPT_SINGLE_CYCLE
`ifdef OPT_PIPELINED
initial opA_alu = 1'b0;
always @(posedge i_clk)
if (op_ce)
916,7 → 925,7
always @(posedge i_clk)
if (mem_ce)
mem_last_reg <= opR;
`ifdef OPT_SINGLE_CYCLE
`ifdef OPT_PIPELINED
assign opA = ((opA_alu)&&(alu_wr)) ? alu_result
: ( ((opA_mem)&&(mem_valid))?mem_result
: r_opA );
924,20 → 933,15
assign opA = r_opA;
`endif
 
`ifdef OPT_PIPELINED
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
`ifdef OPT_SINGLE_CYCLE
// Skip the requirement on writing back opA
// Stall on memory, since we'll always need to stall for a
// memory access anyway
((opvalid_alu)&&(opF_wr)&&(dcdA_cc)));
`else
((opvalid)&&(opR_wr)&&(opR == dcdA))
||((opvalid_alu)&&(opF_wr)&&(dcdA_cc))
||((mem_rdbusy)&&(mem_last_reg == dcdA))
);
// There are no pipeline hazards, if we aren't pipelined
assign dcdA_stall = 1'b0;
`endif
 
`ifdef OPT_SINGLE_CYCLE
`ifdef OPT_PIPELINED
always @(posedge i_clk)
if (op_ce)
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(opR_wr)&&(dcdB_rd)&&(dcd_zI);
956,8 → 960,8
assign opB = r_opB;
`endif
 
`ifdef OPT_PIPELINED
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
`ifdef OPT_SINGLE_CYCLE
// Stall on memory ops writing to my register
// (i.e. loads), or on any write to my
// register if I have an immediate offset
978,12 → 982,13
// will write to opB
||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)));
`else
((opvalid)&&(opR_wr)&&(opR == dcdB))
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
||((mem_rdbusy)&&(mem_last_reg == dcdB))
);
// No stalls without pipelining, 'cause how can you have a pipeline
// hazard without the pipeline?
assign dcdB_stall = 1'b0;
`endif
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])
||((dcdA_rd)&&(dcdA_cc))
||((dcdB_rd)&&(dcdB_cc)))
&&(opvalid)&&(opR_cc);
//
//
990,10 → 995,52
// PIPELINE STAGE #4 :: Apply Instruction
//
//
`ifdef OPT_NEW_INSTRUCTION_SET
cpuops #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
(opvalid_alu), opn, opA, opB,
alu_result, alu_flags, alu_valid, alu_illegal_op);
`else
cpuops_deprecated #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
(opvalid_alu), opn, opA, opB,
alu_result, alu_flags, alu_valid, alu_illegal_op);
`endif
 
generate
if (IMPLEMENT_DIVIDE != 0)
begin
div thedivide(i_clk, i_rst, div_ce, opn[0],
opA, opB, div_busy, div_valid, div_error, div_result,
div_flags);
end else begin
assign div_error = 1'b1;
assign div_busy = 1'b0;
assign div_valid = 1'b0;
assign div_result= 32'h00;
assign div_flags = 4'h0;
end endgenerate
 
generate
if (IMPLEMENT_FPU != 0)
begin
//
// sfpu thefpu(i_clk, i_rst, fpu_ce,
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
// fpu_flags);
//
assign fpu_error = 1'b1;
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end else begin
assign fpu_error = 1'b1;
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end endgenerate
 
 
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
initial alF_wr = 1'b0;
initial alu_wr = 1'b0;
1013,11 → 1060,26
alu_wr <= (i_halt)&&(i_dbg_we);
alF_wr <= 1'b0;
end
 
`ifdef OPT_VLIW
reg r_alu_phase;
initial r_alu_phase = 1'b0;
always @(posedge i_clk)
if (alu_ce)
if (i_rst)
r_alu_phase <= 1'b0;
else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
r_alu_phase <= op_phase;
assign alu_phase = r_alu_phase;
`else
assign alu_phase = 1'b0;
`endif
 
always @(posedge i_clk)
if ((alu_ce)||(div_ce)||(fpu_ce))
alu_reg <= opR;
else if ((i_halt)&&(i_dbg_we))
alu_reg <= i_dbg_reg;
 
reg [31:0] dbg_val;
reg dbgv;
always @(posedge i_clk)
1051,8 → 1113,30
alu_pc_valid <= ((alu_ce)
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
 
wire bus_lock;
`ifdef OPT_PIPELINED
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_bus_lock;
initial r_bus_lock = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_bus_lock <= 1'b0;
else if ((op_ce)&&(op_lock))
r_bus_lock <= 1'b1;
else if (~opvalid_mem)
r_bus_lock <= 1'b0;
assign bus_lock = r_bus_lock;
end else begin
assign bus_lock = 1'b0;
end endgenerate
`else
assign bus_lock = 1'b0;
`endif
 
`ifdef OPT_PIPELINED_BUS_ACCESS
pipemem #(AW) domem(i_clk, i_rst, mem_ce,
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
(opn[0]), opB, opA, opR,
mem_busy, mem_pipe_stalled,
mem_valid, bus_err, mem_wreg, mem_result,
1062,7 → 1146,7
mem_ack, mem_stall, mem_err, i_wb_data);
`else // PIPELINED_BUS_ACCESS
memops #(AW) domem(i_clk, i_rst, mem_ce,
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst, mem_ce, bus_lock,
(opn[0]), opB, opA, opR,
mem_busy,
mem_valid, bus_err, mem_wreg, mem_result,
1106,13 → 1190,15
// Further, alu_wr includes (set_cond), so we don't need to
// check for that here either.
`ifdef OPT_ILLEGAL_INSTRUCTION
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid);
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
`else
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid);
assign wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
`endif
// Which register shall be written?
// COULD SIMPLIFY THIS: by adding three bits to these registers,
// One or PC, one for CC, and one for GIE match
// Note that the alu_reg is the register to write on a divide or
// FPU operation.
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
// Are we writing to the CC register?
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1119,7 → 1205,10
// Are we writing to the PC?
assign wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
// What value to write?
assign wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result) :mem_result;
assign wr_reg_vl = (alu_wr)?((dbgv)?dbg_val: alu_result)
:((mem_valid) ? mem_result
:((div_valid) ? div_result
:fpu_result));
always @(posedge i_clk)
if (wr_reg_ce)
regset[wr_reg_id] <= wr_reg_vl;
1128,14 → 1217,11
// Write back to the condition codes/flags register ...
// When shall we write to our flags register? alF_wr already
// includes the set condition ...
assign wr_flags_ce = (alF_wr)&&(~clear_pipeline)&&(~alu_illegal);
`ifdef OPT_ILLEGAL_INSTRUCTION
assign w_uflags = { ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
`else
assign w_uflags = { ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { ibus_err_flag, trap, ill_err_i, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
`endif
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
assign w_uflags = { ufpu_err_flag, udiv_err_flag, ubus_err_flag, trap, ill_err_u, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
assign w_iflags = { ifpu_err_flag, idiv_err_flag, ibus_err_flag, trap, ill_err_i,break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
 
 
// What value to write?
always @(posedge i_clk)
// If explicitly writing the register itself
1143,13 → 1229,15
flags <= wr_reg_vl[3:0];
// Otherwise if we're setting the flags from an ALU operation
else if ((wr_flags_ce)&&(alu_gie))
flags <= alu_flags;
flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
: alu_flags);
 
always @(posedge i_clk)
if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
iflags <= wr_reg_vl[3:0];
else if ((wr_flags_ce)&&(~alu_gie))
iflags <= alu_flags;
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
: alu_flags);
 
// The 'break' enable bit. This bit can only be set from supervisor
// mode. It control what the CPU does upon encountering a break
1175,8 → 1263,11
`ifdef OPT_ILLEGAL_INSTRUCTION
assign o_break = ((break_en)||(~op_gie))&&(op_break)
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
&&(~div_busy)&&(~fpu_busy)
&&(~clear_pipeline)
||((~alu_gie)&&(bus_err))
||((~alu_gie)&&(div_valid)&&(div_error))
||((~alu_gie)&&(fpu_valid)&&(fpu_error))
||((~alu_gie)&&(alu_valid)&&(alu_illegal));
`else
assign o_break = (((break_en)||(~op_gie))&&(op_break)
1193,12 → 1284,19
// set the sleep bit and switch to supervisor mode in the same
// instruction: users are not allowed to halt the CPU.
always @(posedge i_clk)
if ((i_rst)||((i_interrupt)&&(gie)))
if ((i_rst)||(w_switch_to_interrupt))
sleep <= 1'b0;
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
// In supervisor mode, we have no protections. The
// supervisor can set the sleep bit however he wants.
sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
// Well ... not quite. Switching to user mode and
// sleep mode shouold only be possible if the interrupt
// flag isn't set.
// Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
// don't set the sleep bit
// otherwise however it would o.w. be set
sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
&&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
// In user mode, however, you can only set the sleep
// mode while remaining in user mode. You can't switch
1217,16 → 1315,20
// The GIE register. Only interrupts can disable the interrupt register
assign w_switch_to_interrupt = (gie)&&(
// On interrupt (obviously)
(i_interrupt)
((i_interrupt)&&(~alu_phase)&&(~bus_lock))
// If we are stepping the CPU
||((alu_pc_valid)&&(step))
||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
// If we encounter a break instruction, if the break
// enable isn't set.
||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
&&(op_break)&&(~break_en))
`ifdef OPT_ILLEGAL_INSTRUCTION
// On an illegal instruction
||((alu_valid)&&(alu_illegal))
`endif
||((div_valid)&&(div_error))
||((fpu_valid)&&(fpu_error))
||(bus_err)
// If we write to the CC register
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
1248,12 → 1350,9
always @(posedge i_clk)
if (i_rst)
trap <= 1'b0;
else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
&&(wr_write_cc)) // &&(wr_reg_id[4]) implied
trap <= 1'b1;
// else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
// &&(~i_dbg_data[`CPU_GIE_BIT]))
// trap <= i_dbg_data[`CPU_TRAP_BIT];
else if (w_release_from_interrupt)
trap <= 1'b0;
 
1317,6 → 1416,103
else if ((bus_err)&&(alu_gie))
ubus_err_flag <= 1'b1;
 
generate
if (IMPLEMENT_DIVIDE != 0)
begin
reg r_idiv_err_flag, r_udiv_err_flag;
 
// Supervisor/interrupt divide (by zero) error flag -- this will
// crash the CPU if ever set. This bit is thus available for us
// to be able to tell if/why the CPU crashed.
initial r_idiv_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_idiv_err_flag <= 1'b0;
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
&&(~wr_reg_vl[`CPU_DIVERR_BIT]))
r_idiv_err_flag <= 1'b0;
else if ((div_error)&&(div_valid)&&(~alu_gie))
r_idiv_err_flag <= 1'b1;
// User divide (by zero) error flag -- if ever set, it will
// cause a sudden switch interrupt to supervisor mode.
initial r_udiv_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_udiv_err_flag <= 1'b0;
else if (w_release_from_interrupt)
r_udiv_err_flag <= 1'b0;
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
&&(~wr_reg_vl[`CPU_DIVERR_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
r_udiv_err_flag <= 1'b0;
else if ((div_error)&&(alu_gie)&&(div_valid))
r_udiv_err_flag <= 1'b1;
 
assign idiv_err_flag = r_idiv_err_flag;
assign udiv_err_flag = r_udiv_err_flag;
end else begin
assign idiv_err_flag = 1'b0;
assign udiv_err_flag = 1'b0;
end endgenerate
 
generate
if (IMPLEMENT_FPU !=0)
begin
// Supervisor/interrupt floating point error flag -- this will
// crash the CPU if ever set.
reg r_ifpu_err_flag, r_ufpu_err_flag;
initial r_ifpu_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_ifpu_err_flag <= 1'b0;
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
&&(~wr_reg_vl[`CPU_FPUERR_BIT]))
r_ifpu_err_flag <= 1'b0;
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
r_ifpu_err_flag <= 1'b1;
// User floating point error flag -- if ever set, it will cause
// a sudden switch interrupt to supervisor mode.
initial r_ufpu_err_flag = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_ufpu_err_flag <= 1'b0;
else if (w_release_from_interrupt)
r_ufpu_err_flag <= 1'b0;
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
&&(~wr_reg_vl[`CPU_FPUERR_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
r_ufpu_err_flag <= 1'b0;
else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
r_ufpu_err_flag <= 1'b1;
 
assign ifpu_err_flag = r_ifpu_err_flag;
assign ufpu_err_flag = r_ufpu_err_flag;
end else begin
assign ifpu_err_flag = 1'b0;
assign ufpu_err_flag = 1'b0;
end endgenerate
 
`ifdef OPT_VLIW
reg r_ihalt_phase, r_uhalt_phase;
 
initial r_ihalt_phase = 0;
initial r_uhalt_phase = 0;
always @(posedge i_clk)
if (~alu_gie)
r_ihalt_phase <= alu_phase;
always @(posedge i_clk)
if (alu_gie)
r_uhalt_phase <= alu_phase;
else if (w_release_from_interrupt)
r_uhalt_phase <= 1'b0;
 
assign ihalt_phase = r_ihalt_phase;
assign uhalt_phase = r_uhalt_phase;
`else
assign ihalt_phase = 1'b0;
assign uhalt_phase = 1'b0;
`endif
 
//
// Write backs to the PC register, and general increments of it
// We support two: upc and ipc. If the instruction is normal,
1350,8 → 1546,15
pf_pc <= upc;
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
pf_pc <= wr_reg_vl[(AW-1):0];
else if (dcd_ce)
`ifdef OPT_PIPELINED
else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
pf_pc <= dcd_branch_pc + 1;
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
`else
else if ((alu_pc_valid)&&(~clear_pipeline))
pf_pc <= alu_pc;
`endif
 
initial new_pc = 1'b1;
always @(posedge i_clk)
1378,7 → 1581,7
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
begin
o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[`CPU_GIE_BIT] <= gie;
end
end
1390,7 → 1593,7
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
else if (i_dbg_reg[3:0] == `CPU_CC_REG)
begin
o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[12:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
o_dbg_reg[`CPU_GIE_BIT] <= gie;
end
end
1418,7 → 1621,8
`ifdef DEBUG_SCOPE
always @(posedge i_clk)
o_debug <= {
pf_pc[7:0],
/*
pf_pc[3:0], flags,
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
op_ce, alu_ce, mem_ce,
//
1432,6 → 1636,13
// opA[23:20], opA[3:0],
gie, sleep,
wr_reg_vl[5:0]
*/
i_rst, master_ce, (new_pc),
((dcd_early_branch)&&(dcdvalid)),
pf_valid, pf_illegal,
op_ce, dcd_ce, dcdvalid, dcd_stalled,
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
pf_pc[7:0], pf_addr[7:0]
};
`endif

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