URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl/core
- from Rev 81 to Rev 82
- ↔ Reverse comparison
Rev 81 → Rev 82
/pfcache.v
1,6 → 1,6
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pfcache2.v |
// Filename: pfcache.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
73,7 → 73,8
reg [(AW-1):0] lastpc; |
reg [(CW-1):0] rdaddr; |
reg [(AW-1):CW] tagval; |
reg [(AW-1):PW] lasttag, illegal_cache; |
wire [(AW-1):PW] lasttag; |
reg [(AW-1):PW] illegal_cache; |
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initial o_i = 32'h76_00_00_00; // A NOOP instruction |
initial o_pc = 0; |
90,7 → 91,17
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initial tagval = 0; |
always @(posedge i_clk) |
if (i_stall_n) |
if((o_wb_cyc)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}) |
&&(i_wb_ack)&&(~i_wb_err)) |
// Our tag value changes any time we finish reading a |
// new cache line |
tagval <= o_wb_addr[(AW-1):CW]; |
else if ((i_stall_n)&&(~o_wb_cyc)) |
// Otherwise, as long as we're not reading new stuff, |
// the tag line changes any time the pipeline steps |
// forwards. Our purpose here is primarily just to |
// catch sudden changes. The result is that walking |
// from one cache line to the next will cost a clock. |
tagval <= tags[i_pc[(CW-1):PW]]; |
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// i_pc will only increment when everything else isn't stalled, thus |
103,16 → 114,19
if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc)) |
lastpc <= i_pc; |
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initial lasttag = 0; |
always @(posedge i_clk) |
lasttag <= i_pc[(AW-1):PW]; |
assign lasttag = lastpc[(AW-1):PW]; |
// initial lasttag = 0; |
// always @(posedge i_clk) |
// if (((r_v)&&(i_stall_n))||(i_clear_cache)||(i_new_pc)) |
// lasttag <= i_pc[(AW-1):PW]; |
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wire r_v_from_pc, r_v_from_last; |
assign r_v_from_pc = ((i_pc[(AW-1):PW] == lasttag) |
&&(tagval == i_pc[(AW-1):CW]) |
&&(vmask[i_pc[(CW-1):PW]])); |
assign r_v_from_last = ((lastpc[(AW-1):PW] == lasttag) |
&&(tagval == lastpc[(AW-1):CW]) |
assign r_v_from_last = ( |
//(lastpc[(AW-1):PW] == lasttag)&& |
(tagval == lastpc[(AW-1):CW]) |
&&(vmask[lastpc[(CW-1):PW]])); |
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reg [1:0] delay; |
155,12 → 169,15
end |
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if (i_wb_ack) |
begin |
rdaddr <= rdaddr + 1; |
if ((rdaddr[(PW-1):0] == {(PW){1'b1}})||(i_wb_err)) |
begin |
if (rdaddr[(PW-1):0] == {(PW){1'b1}}) |
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW]; |
end |
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if (((i_wb_ack)&&(rdaddr[(PW-1):0]=={(PW){1'b1}}))||(i_wb_err)) |
o_wb_cyc <= 1'b0; |
tags[o_wb_addr[(CW-1):PW]] <= o_wb_addr[(AW-1):CW]; |
end |
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// else if (rdaddr[(PW-1):1] == {(PW-1){1'b1}}) |
// tags[lastpc[(CW-1):PW]] <= lastpc[(AW-1):CW]; |
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