URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu/trunk/rtl/core
- from Rev 91 to Rev 105
- ↔ Reverse comparison
Rev 91 → Rev 105
/idecode.v
55,7 → 55,7
o_cond, o_wF, |
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, |
o_early_branch, o_branch_pc, o_ljmp, |
o_pipe |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
79,6 → 79,7
output reg o_wR, o_rA, o_rB; |
output wire o_early_branch; |
output wire [(AW-1):0] o_branch_pc; |
output wire o_ljmp; |
output reg o_pipe; |
|
wire dcdA_stall, dcdB_stall, dcdF_stall; |
96,8 → 97,16
wire [3:0] w_cond; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP; |
wire w_wR, w_rA, w_rB, w_wR_n; |
wire w_ljmp; |
|
generate |
if (EARLY_BRANCHING != 0) |
assign w_ljmp = (iword == 32'h7c87c000); |
else |
assign w_ljmp = 1'b0; |
endgenerate |
|
|
wire [31:0] iword; |
`ifdef OPT_VLIW |
reg [16:0] r_nxt_half; |
127,7 → 136,7
// 0 LUTs |
assign w_dcdA = w_dcdR; |
// 2 LUTs, 1 delay each |
// assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
// 0 LUTs |
assign w_dcdA_pc = w_dcdR_pc; |
330,37 → 339,54
`endif |
end |
|
|
generate |
if (EARLY_BRANCHING!=0) |
begin |
reg r_early_branch; |
reg r_early_branch, r_ljmp; |
reg [(AW-1):0] r_branch_pc; |
|
initial r_ljmp = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
if (i_rst) |
r_ljmp <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_ljmp <= (w_ljmp); |
assign o_ljmp = r_ljmp; |
|
always @(posedge i_clk) |
if (i_rst) |
r_early_branch <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
begin |
if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
if (r_ljmp) |
// LOD (PC),PC |
r_early_branch <= 1'b1; |
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
begin |
if (w_op[4:1] == 4'hb) // LDI to PC |
begin // LDI x,PC |
// LDI x,PC |
r_early_branch <= 1'b1; |
end else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
begin // Add x,PC |
else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
// Add x,PC |
r_early_branch <= 1'b1; |
end else begin |
else begin |
r_early_branch <= 1'b0; |
end |
end else |
r_early_branch <= 1'b0; |
end |
end else if (i_ce) |
r_early_branch <= 1'b0; |
|
always @(posedge i_clk) |
if (i_ce) |
begin |
if (w_op[4:1] == 4'hb) // LDI |
if (r_ljmp) |
r_branch_pc <= iword[(AW-1):0]; |
else if (w_op[4:1] == 4'hb) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
else // Add x,PC |
r_branch_pc <= i_pc |
+ {{(AW-18){iword[17]}},iword[16:0]} |
+ {{(AW-17){iword[17]}},iword[16:0]} |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
369,6 → 395,7
end else begin |
assign o_early_branch = 1'b0; |
assign o_branch_pc = {(AW){1'b0}}; |
assign o_ljmp = 1'b0; |
end endgenerate |
|
|
396,6 → 423,8
always @(posedge i_clk) |
if (i_rst) |
r_valid <= 1'b0; |
else if ((i_ce)&&(o_ljmp)) |
r_valid <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_valid <= 1'b1; |
else if (~i_stalled) |
/idecode_deprecated.v
101,7 → 101,7
assign o_branch_pc = r_branch_pc; |
|
always @(posedge i_clk) |
if ((i_ce)&&(i_instruction[27:24]==`CPU_PC_REG)) |
if ((i_ce)&&(i_pf_valid)&&(i_instruction[27:24]==`CPU_PC_REG)) |
begin |
r_early_branch <= 1'b0; |
// First case, a move to PC instruction |
/zipcpu.v
252,7 → 252,7
wire dcdR_wr, dcdA_rd, dcdB_rd, |
dcdALU, dcdM, dcdDV, dcdFP, |
dcdF_wr, dcd_gie, dcd_break, dcd_lock, |
dcd_pipe; |
dcd_pipe, dcd_ljmp; |
reg r_dcdvalid; |
wire dcdvalid; |
wire [(AW-1):0] dcd_pc; |
523,8 → 523,8
if (i_rst) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch)); |
else if ((op_ce)||(clear_pipeline)) |
r_dcdvalid <= (pf_valid); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
|
532,11 → 532,11
|
`ifdef OPT_TRADITIONAL_PFCACHE |
pfcache #(LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)), |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
i_clear_pf_cache, |
// dcd_pc, |
~dcd_stalled, |
((dcd_early_branch)&&(dcdvalid)&&(~new_pc)) |
((dcd_early_branch)&&(~clear_pipeline)) |
? dcd_branch_pc:pf_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
544,7 → 544,7
pf_illegal); |
`else |
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)), |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
i_clear_pf_cache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
565,7 → 565,7
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch)); |
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch)); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
585,7 → 585,7
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_branch_pc, dcd_ljmp, |
dcd_pipe); |
`else |
idecode_deprecated |
604,6 → 604,7
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
assign dcd_ljmp = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
736,7 → 737,7
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
|
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid); |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
1557,7 → 1558,7
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_reg_vl[(AW-1):0]; |
`ifdef OPT_PIPELINED |
else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid))) |
else if ((dcd_early_branch)&&(~clear_pipeline)) |
pf_pc <= dcd_branch_pc + 1; |
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |