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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/sim/verilator
    from Rev 204 to Rev 207
    Reverse comparison

Rev 204 → Rev 207

/div_tb.cpp
45,6 → 45,8
#include "testb.h"
// #include "twoc.h"
 
#define DIVASSERT(A) do { if (!(A)) { closetrace(); } assert(A); } while(0)
 
class DIV_TB : public TESTB<Vdiv> {
public:
DIV_TB(void) {
57,11 → 59,6
TESTB<Vdiv>::reset();
}
 
bool on_tick(void) {
tick();
return true;
}
 
void bprint(char *str, int nbits, unsigned long v) {
while(*str)
str++;
118,7 → 115,7
 
// The test bench is supposed to assert that we are idle when
// we come in here.
assert(m_core->o_busy == 0);
DIVASSERT(m_core->o_busy == 0);
 
// Request a divide
m_core->i_rst = 0;
141,10 → 138,10
// listed as a valid result.
if (!m_core->o_busy) {
closetrace();
assert(m_core->o_busy);
DIVASSERT(m_core->o_busy);
} if (m_core->o_valid != 0) {
closetrace();
assert(m_core->o_valid == 0);
DIVASSERT(m_core->o_valid == 0);
}
 
// while((!m_core->o_valid)&&(!m_core->o_err))
156,7 → 153,7
// is a test failure.
dbgdump();
closetrace();
assert(m_core->o_busy);
DIVASSERT(m_core->o_busy);
}
 
// Let the algorithm work for another clock tick.
167,7 → 164,7
// result has been produced.
if (m_core->o_busy) {
closetrace();
assert(!m_core->o_busy);
DIVASSERT(!m_core->o_busy);
}
 
if (dbg) {
191,7 → 188,7
// assert, lest the file not get the final
// values into it.
closetrace();
assert(m_core->o_err);
DIVASSERT(m_core->o_err);
}
} else if (m_core->o_err) {
// Otherwise, there should not have been any divide
199,7 → 196,7
// divide by zero. So, this is an error. Let's
// stop and report it.
closetrace();
assert(!m_core->o_err);
DIVASSERT(!m_core->o_err);
} else if (ans != (uint32_t)m_core->o_quotient) {
// The other problem we might encounter would be if the
// result doesn't match the one we are expecting.
207,8 → 204,14
// Stop on this bug as well.
//
closetrace();
assert(ans == (uint32_t)m_core->o_quotient);
DIVASSERT(ans == (uint32_t)m_core->o_quotient);
}
 
if(((m_core->o_quotient == 0)&&((m_core->o_flags&1)==0))
||((m_core->o_quotient!= 0)&&((m_core->o_flags&1)!=0))){
fprintf(stderr, "Z-FLAG DOES NOT MATCH: FLAGS = %d, QUOTIENT = %08x\n", m_core->o_flags, m_core->o_quotient);
DIVASSERT((m_core->o_quotient!= 0)^(m_core->o_flags&1));
}
}
 
// Test a signed divide
254,8 → 257,6
Verilated::commandArgs(argc, argv);
DIV_TB *tb = new DIV_TB();
 
// tb->opentrace("divtrace.vcd");
 
tb->reset();
// tb->opentrace("div_tb.vcd");
 

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