OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/sw
    from Rev 206 to Rev 209
    Reverse comparison

Rev 206 → Rev 209

/.gitignore
10,3 → 10,6
newlib-2.5.0/
newlib-2.5.0-zip/
2017*.patch
lib/
zipos/
zlibc/
/Makefile
1,69 → 1,75
################################################################################
#
# Filename: Makefile
#
# Project: Zip CPU -- a small, lightweight, RISC CPU soft core
#
# Purpose: This makefile attempts to build the ZipCPU toolchain. This
# includes binutils and GCC. (Eventually, it will include the
# standard library as well ...) Configuration options for binutils, GCC,
# and newlib can be found (and set) in the gas-script.sh, gcc-script.sh,
# and nlib-script.sh files respectively.
#
# Targets:
#
# make all:
# Includes the install target, but also the pdf documentation
# files that come with binutils and gcc. Building this target
# will require a LaTeX distribution in addition to the needs of
# the other targets. Since the PDFs can be found on line,
# building them is not really necessary, but may be quite useful.
#
# make install
# Attempts to build binutils, gcc, and newlib, and to install
# them into the local install directory.
#
# This is the default target
#
# make binutils
# make gcc
# make newlib
# Builds the respective packages
#
# make binutils-install
# make gcc-install
# make newlib-install
# Installs the respective packages into the install directory,
# building them first if necessary.
#
# make clean
# Removes all build products--to include the source directories
# that are built from patched tarballs.
#
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Technology, LLC
#
##
## Filename: Makefile
##
## Project: Zip CPU -- a small, lightweight, RISC CPU soft core
##
## Purpose: This makefile attempts to build the ZipCPU toolchain. This
## includes binutils and GCC. (Eventually, it will include the
## standard library as well ...) Configuration options for binutils, GCC,
## and newlib can be found (and set) in the gas-script.sh, gcc-script.sh,
## and nlib-script.sh files respectively.
##
## Targets:
##
## make all:
## Includes the install target, but also the pdf documentation
## files that come with binutils and gcc. Building this target
## will require a LaTeX distribution in addition to the needs of
## the other targets. Since the PDFs can be found on line,
## building them is not really necessary, but may be quite useful.
##
## make install
## Attempts to build binutils, gcc, and newlib, and to install
## them into the local install directory.
##
## This is the default target
##
## make binutils
## make gcc
## make newlib
## Builds the respective packages
##
## make binutils-install
## make gcc-install
## make newlib-install
## Installs the respective packages into the install directory,
## building them first if necessary.
##
## make clean
## Removes all build products--to include the source directories
## that are built from patched tarballs.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
#
# Copyright (C) 2015-2017, Gisselquist Technology, LLC
#
# This program is free software (firmware): you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
# by the Free Software Foundation, either version 3 of the License, or (at
# your option) any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# License: GPL, v3, as defined and found on www.gnu.org,
# http://www.gnu.org/licenses/gpl.html
#
#
##
## Copyright (C) 2015-2017, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
#
##
##
.PHONY: all basic-install install build
install: basic-install
all: basic-install binutils-pdf-install gcc-pdf-install
71,17 → 77,19
build: gas gcc-all nlib
CC: gcc
 
BINUTILSD=binutils-2.27
GCCD=gcc-6.2.0
NLIBD=newlib-2.5.0
INSTALL=`pwd`/install
PDFD=$(INSTALL)/usr/doc
BINUTILSD:=binutils-2.27
GCCD:=gcc-6.2.0
NLIBD:=newlib-2.5.0
export INSTALLD:=$(shell pwd)/install
export PATH:=$(PATH):$(INSTALLD)/cross-tools/bin
PDFD=$(INSTALLD)/usr/doc
ZASMD=zasm
BUILDGASD=build-gas
BUILDGCCD=build-gcc
BUILDNLIB=build-nlib
SUBMAKE=$(MAKE) --no-print-directory
ZIPINCD=$(INSTALL)/cross-tools/zip/include
BUILDGASD:=build-gas
BUILDGCCD:=build-gcc
BUILDNLIB:=build-nlib
TARGETGCC:=$(INSTALL)/cross-tools/bin/zip-gcc
SUBMAKE:=$(MAKE) --no-print-directory
ZIPINCD=$(INSTALLD)/cross-tools/zip/include
 
$(BINUTILSD)-zip/nonce.txt: $(BINUTILSD).tar.bz2 gas-zippatch.patch
rm -rf $(BINUTILSD)-zip/
97,25 → 105,32
.PHONY: binutils
binutils: $(BUILDGASD)/nonce.txt
$(SUBMAKE) --directory=$(BUILDGASD)
@echo "Binutils package build complete"
 
.PHONY: binutils-install
binutils-install: binutils
$(SUBMAKE) --directory=$(BUILDGASD) install
cp ../bench/zipsim.ld install/cross-tools/zip/lib/ldscripts
bash -c "if [[ ! -f $(BUILDGASD)/install-nonce.txt ]]; then touch $(BUILDGASD)/install-nonce.txt; fi"
@echo "Binutils installed"
 
.PHONY: binutils-pdf
binutils-pdf: binutils
$(SUBMAKE) --directory=$(BUILDGASD) pdf
@echo "Binutils pdfs made"
 
$(PDFD)/:
bash -c "if [[ ! -d $(PDFD) ]]; then mkdir -p $(PDFD); fi"
.PHONY: pdfd
pdfd:
$(mk-pdfd)
 
.PHONY:
pdfd: $(PDFD)/
define mk-pdfd
@bash -c "if [[ ! -d $(PDFD) ]]; then mkdir -p $(PDFD); fi"
endef
 
.PHONY: binutils-pdf-install
binutils-pdf-install: binutils-pdf $(PDFD)/
binutils-pdf-install: binutils-pdf pdfd
find $(BUILDGASD) -name "*.pdf" -exec cp \{\} $(PDFD)/ \;
@echo "Binutils pdfs installed"
 
.PHONY: gas
gas: binutils
123,6 → 138,9
.PHONY: gas-install
gas-install: binutils-install
 
$(BUILDGASD)/install-nonce.txt: binutils-install
 
 
# We can also set the environment variable DEJAGNU to point to our site .exp
# file.
gas-check: binutils-install
132,6 → 150,7
# Now let's try the same thing for GCC
#
#
$(GCCD)-zip/nonce.txt: $(BUILDGASD)/install-nonce.txt
$(GCCD)-zip/nonce.txt: $(GCCD).tar.bz2 gcc-zippatch.patch
rm -rf $(GCCD)-zip/
tar -xjf ./$(GCCD).tar.bz2 --transform s,$(GCCD),$(GCCD)-zip,
145,7 → 164,8
$(GCCD)-zip/gcc/config/zip/zip-ops.md: genzipops
./genzipops $@
 
$(BUILDGCCD)/nonce.txt: $(GCCD)-zip/nonce.txt $(GCCD)-zip/gcc/config/zip/zip-ops.md gas-install
$(BUILDGCCD)/nonce.txt: $(BUILDGASD)/install-nonce.txt
$(BUILDGCCD)/nonce.txt: $(GCCD)-zip/nonce.txt $(GCCD)-zip/gcc/config/zip/zip-ops.md
bash -c "if [[ ! -e $(BUILDGCCD) ]]; then bash gcc-script.sh; fi"
touch $(BUILDGCCD)/nonce.txt
 
158,19 → 178,23
#
gcc-host: $(BUILDGCCD)/nonce.txt
+$(SUBMAKE) --directory=$(BUILDGCCD) all-host
@echo "GCC package build complete"
.PHONY: zip-gcc
zip-gcc: gcc-host
 
gcc-install-host: $(BUILDGCCD)/nonce.txt gcc-host
+$(SUBMAKE) --directory=$(BUILDGCCD) install-host
@bash -c "if [[ ! -f $(BUILDGCCD)/install-nonce.txt ]]; then touch $(BUILDGCCD)/install-nonce.txt; fi"
@echo "GCC package installed"
 
.PHONY: zip-gcc-install
zip-gcc-install: gcc-install-host
 
$(INSTALL)/cross-tools/bin/zip-gcc: zip-gcc-install
$(INSTALLD)/cross-tools/bin/zip-gcc: zip-gcc-install
$(BUILDGCCD)/install-nonce.txt: zip-gcc-install
 
$(INSTALL)/cross-tools/bin/zip-cc: zip-gcc-install
bash -c "cd $(INSTALL)/cross-tools/bin; if [[ ! -e zip-cc ]]; then ln -s zip-gcc zip-cc; fi"
$(INSTALLD)/cross-tools/bin/zip-cc: zip-gcc-install
bash -c "cd $(INSTALLD)/cross-tools/bin; if [[ ! -e zip-cc ]]; then ln -s zip-gcc zip-cc; fi"
 
.PHONY: gcc-pdf-install
#
180,19 → 204,24
#
#
.PHONY: gcc
gcc: $(BUILDGCCD)/nonce.txt gas-install newlib-install
gcc: $(BUILDGASD)/install-nonce.txt
gcc: $(BUILDNLIB)/install-nonce.txt
gcc: $(BUILDGCCD)/nonce.txt
+$(SUBMAKE) --directory=$(BUILDGCCD)
 
.PHONY: gcc-install
gcc-install: gcc
+$(SUBMAKE) --directory=$(BUILDGCCD) install
@echo "GCC installed"
 
.PHONY: gcc-pdf
gcc-pdf: $(BUILDGCCD)/nonce.txt
+$(SUBMAKE) --directory=$(BUILDGCCD) pdf
@echo "GCC documentation built"
 
gcc-pdf-install: gcc-pdf $(PDFD)/
find $(BUILDGCCD) -name "*.pdf" -exec cp \{\} $(PDFD)/ \;
@echo "GCC documentation/pdfs installed"
 
#
#
199,6 → 228,7
# And repeat for newlib
#
#
$(NLIBD)-zip/nonce.txt: $(BUILDGCCD)/install-nonce.txt
$(NLIBD)-zip/nonce.txt: $(NLIBD).tar.gz nlib-zippatch.patch
rm -rf $(NLIBD)-zip/
tar -xzf ./$(NLIBD).tar.gz --transform s,$(NLIBD),$(NLIBD)-zip,
211,13 → 241,17
touch $(BUILDNLIB)/nonce.txt
 
.PHONY: newlib
newlib: $(BUILDNLIB)/nonce.txt zip-gcc-install
newlib: $(INSTALL)/cross-tools/bin/zip-cc
newlib: $(BUILDGCCD)/install-nonce.txt
newlib: $(BUILDNLIB)/nonce.txt
newlib: $(INSTALLD)/cross-tools/bin/zip-cc
+$(SUBMAKE) --directory=$(BUILDNLIB)
@echo "Newlib build complete"
 
.PHONY: newlib-install
newlib-install: newlib
+$(SUBMAKE) --directory=$(BUILDNLIB) install
@bash -c "if [[ ! -f $(BUILDNLIB)/install-nonce.txt ]]; then touch $(BUILDNLIB)/install-nonce.txt; fi"
@echo "Newlib installed"
 
 
# Some abbreviations for targets
224,6 → 258,7
.PHONY: nlib nlib-install
nlib: newlib
nlib-install: newlib-install
$(BUILDNLIB)/install-nonce.txt: newlib-install
 
#
#
243,7 → 278,7
#
.PHONY: clean
clean:
rm -rf $(INSTALL)
rm -rf $(INSTALLD)/cros-tools/bin/zip-*
rm -rf $(BINUTILSD)-zip/ $(GCCD)-zip/ $(NLIBD)-zip/
rm -rf $(BUILDGASD) $(BUILDGCCD) $(BUILDNLIB)
# $(SUBMAKE) --no-print-directory --directory=$(ZASMD) clean
/README.md
0,0 → 1,49
This directory contains the source code for the ZipCPU tool-chain--the
GCC back end, assembler, and linker. The directory also has the patches
necessary to build the C-library, newlib. This tool-chain is kept in a series
of patch files--primarily because I found the patch files for the eco32
CPU *very* helpful to me when I needed to know where to start when building
the back end for the ZipCPU.
 
You'll also find within this directory the [Makefile](Makefile) used to
direct the build of this tool-chain, together with basic scripts for building
[GCC](gcc-script.sh), [binutils](gas-script.sh), and [newlib](nlib-script.sh).
 
If you run into trouble building these components, know this: the
[Makefile](Makefile) works off of the existence of nonce.txt files to know
how to proceed from one step to the next. Hence, as an example, when building
the binutils components, it will start by applying patches to the binutils
repository found within here. Once completed, it will place a nonce.txt
file into the resulting (patched) directory. It will then attempt to
configure binutils. Once done, there will be a `build-gas` directory with
a `nonce.txt` file within it. This will be `make`s indication to move forward
and build the compiler. If you have any problems with building, or if you want
to start the build over, feel free to either remove the patched directories,
or even to just remove the (empty) `nonce.txt` files and have `make`
start over.
 
## Common problems building the toolchain
 
The most common problem people have had is the result of not having the
pre-requisites properly installed on your computer. Sadly, in this case,
the makefile will exit with some confusing error. You'll need to find the
`config.log` file of the component that didn't build to find out what is
missing.
 
Another common error is that GCC needs the cross-built GCC to build it's
libraries. Hence, you may need to make certain that the install'ed binary
directory is in your path. I've tried to clean this up so that the
tool-chain Makefile doesn't require this, but certainly the builds of any
assembly or C related files will require it.
 
## Installed location
 
Currently, the tool-chain as configured does not install into your system
directories, but rather into an `install` directory that will be built as a
subset of this one. This behavior is controlled by the `prefix` flags within
the various build scripts, which in turn is set by a Makefile variable.
Should you wish to change this behavior, just remember that the install
to the system directory will require sys-admin privileges, and it may also
require you to build the various components manually rather than via the
make script. (It's not something I've tested.)
 
/gas-script.sh
50,7 → 50,11
set -e
CLFS_HOST=$MACHTYPE
CLFS_TARGET="zip"
INSTALL_BASE=`pwd`/install
if [[ -z "$INSTALLD" ]]
then
INSTALLD=`pwd`/install
fi
INSTALL_BASE=${INSTALLD}
mkdir -p ${INSTALL_BASE}/cross-tools
mkdir -p build-gas
echo ../$VERSION-zip/configure
/gas-zippatch.patch
1,5 → 1,5
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/archures.c binutils-2.27-zip/bfd/archures.c
--- binutils-2.27/bfd/archures.c 2016-08-03 03:36:50.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/archures.c binutils-2.27-zip/bfd/archures.c
--- binutils-2.27-original/bfd/archures.c 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27-zip/bfd/archures.c 2017-01-04 14:22:45.000000000 -0500
@@ -525,6 +525,8 @@
.#define bfd_mach_nios2r2 2
26,8 → 26,8
#endif
0
};
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/bfd-in2.h binutils-2.27-zip/bfd/bfd-in2.h
--- binutils-2.27/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/bfd-in2.h binutils-2.27-zip/bfd/bfd-in2.h
--- binutils-2.27-original/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27-zip/bfd/bfd-in2.h 2017-01-04 22:04:11.000000000 -0500
@@ -2336,6 +2336,8 @@
#define bfd_mach_nios2r2 2
61,8 → 61,8
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/config.bfd binutils-2.27-zip/bfd/config.bfd
--- binutils-2.27/bfd/config.bfd 2016-08-03 03:36:50.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/config.bfd binutils-2.27-zip/bfd/config.bfd
--- binutils-2.27-original/bfd/config.bfd 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27-zip/bfd/config.bfd 2016-12-31 17:11:00.961307172 -0500
@@ -1742,6 +1742,10 @@
targ_underscore=yes
75,8 → 75,8
*-*-ieee*)
targ_defvec=ieee_vec
;;
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/configure binutils-2.27-zip/bfd/configure
--- binutils-2.27/bfd/configure 2016-08-03 04:33:36.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/configure binutils-2.27-zip/bfd/configure
--- binutils-2.27-original/bfd/configure 2016-08-03 04:33:36.000000000 -0400
+++ binutils-2.27-zip/bfd/configure 2016-12-31 17:12:22.360697343 -0500
@@ -14542,6 +14542,7 @@
xtensa_elf32_le_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
96,8 → 96,8
esac
case "$COREFILE" in
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/configure.ac binutils-2.27-zip/bfd/configure.ac
--- binutils-2.27/bfd/configure.ac 2016-08-03 03:36:50.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/configure.ac binutils-2.27-zip/bfd/configure.ac
--- binutils-2.27-original/bfd/configure.ac 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27-zip/bfd/configure.ac 2016-12-31 17:13:38.600136486 -0500
@@ -717,6 +717,7 @@
xtensa_elf32_le_vec) tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
117,8 → 117,8
esac
case "$COREFILE" in
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/cpu-zip.c binutils-2.27-zip/bfd/cpu-zip.c
--- binutils-2.27/bfd/cpu-zip.c 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/cpu-zip.c binutils-2.27-zip/bfd/cpu-zip.c
--- binutils-2.27-original/bfd/cpu-zip.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/bfd/cpu-zip.c 2017-01-04 14:26:27.000000000 -0500
@@ -0,0 +1,65 @@
+////////////////////////////////////////////////////////////////////////////////
186,8 → 186,8
+ // the same family.
+};
+
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/archures.texi binutils-2.27-zip/bfd/doc/archures.texi
--- binutils-2.27/bfd/doc/archures.texi 2016-08-03 04:36:22.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/doc/archures.texi binutils-2.27-zip/bfd/doc/archures.texi
--- binutils-2.27-original/bfd/doc/archures.texi 2016-08-03 04:36:22.000000000 -0400
+++ binutils-2.27-zip/bfd/doc/archures.texi 2016-12-31 17:14:43.103668704 -0500
@@ -492,6 +492,8 @@
#define bfd_mach_nios2r2 2
198,8 → 198,8
bfd_arch_last
@};
@end example
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/bfd.info binutils-2.27-zip/bfd/doc/bfd.info
--- binutils-2.27/bfd/doc/bfd.info 2016-08-03 04:36:22.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/doc/bfd.info binutils-2.27-zip/bfd/doc/bfd.info
--- binutils-2.27-original/bfd/doc/bfd.info 2016-08-03 04:36:22.000000000 -0400
+++ binutils-2.27-zip/bfd/doc/bfd.info 2017-01-04 14:40:21.000000000 -0500
@@ -8466,6 +8466,8 @@
#define bfd_mach_nios2r2 2
210,8 → 210,8
bfd_arch_last
};
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/doc/reloc.texi binutils-2.27-zip/bfd/doc/reloc.texi
--- binutils-2.27/bfd/doc/reloc.texi 2016-08-03 04:36:22.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/doc/reloc.texi binutils-2.27-zip/bfd/doc/reloc.texi
--- binutils-2.27-original/bfd/doc/reloc.texi 2016-08-03 04:36:22.000000000 -0400
+++ binutils-2.27-zip/bfd/doc/reloc.texi 2016-12-31 17:17:15.950640091 -0500
@@ -4214,6 +4214,19 @@
@deffnx {} BFD_RELOC_VISIUM_IM16_PCREL
233,8 → 233,8
@example
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/elf32-zip.c binutils-2.27-zip/bfd/elf32-zip.c
--- binutils-2.27/bfd/elf32-zip.c 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/elf32-zip.c binutils-2.27-zip/bfd/elf32-zip.c
--- binutils-2.27-original/bfd/elf32-zip.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/bfd/elf32-zip.c 2017-01-24 13:54:25.214097101 -0500
@@ -0,0 +1,1134 @@
+////////////////////////////////////////////////////////////////////////////////
1371,8 → 1371,8
+};
+#endif
+
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/libbfd.h binutils-2.27-zip/bfd/libbfd.h
--- binutils-2.27/bfd/libbfd.h 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/libbfd.h binutils-2.27-zip/bfd/libbfd.h
--- binutils-2.27-original/bfd/libbfd.h 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/bfd/libbfd.h 2017-01-04 22:04:11.000000000 -0500
@@ -3125,6 +3125,16 @@
"BFD_RELOC_VISIUM_HI16_PCREL",
1391,8 → 1391,8
"@@overflow: BFD_RELOC_UNUSED@@",
};
#endif
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/Makefile.am binutils-2.27-zip/bfd/Makefile.am
--- binutils-2.27/bfd/Makefile.am 2016-08-03 03:36:50.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/Makefile.am binutils-2.27-zip/bfd/Makefile.am
--- binutils-2.27-original/bfd/Makefile.am 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27-zip/bfd/Makefile.am 2016-12-31 17:26:07.151146300 -0500
@@ -173,7 +173,8 @@
cpu-xstormy16.lo \
1430,8 → 1430,8
elf32.c \
elflink.c \
elfxx-sparc.c \
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/Makefile.in binutils-2.27-zip/bfd/Makefile.in
--- binutils-2.27/bfd/Makefile.in 2016-08-03 04:06:27.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/Makefile.in binutils-2.27-zip/bfd/Makefile.in
--- binutils-2.27-original/bfd/Makefile.in 2016-08-03 04:06:27.000000000 -0400
+++ binutils-2.27-zip/bfd/Makefile.in 2017-01-04 14:29:55.000000000 -0500
@@ -505,7 +505,8 @@
cpu-xstormy16.lo \
1477,8 → 1477,8
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/demo64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf1.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dwarf2.Plo@am__quote@
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/merge.c binutils-2.27-zip/bfd/merge.c
--- binutils-2.27/bfd/merge.c 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/merge.c binutils-2.27-zip/bfd/merge.c
--- binutils-2.27-original/bfd/merge.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/bfd/merge.c 2017-01-02 14:48:54.000000000 -0500
@@ -826,7 +826,7 @@
else
1489,8 → 1489,8
if (bfd_seek (output_bfd, pos, SEEK_SET) != 0)
return FALSE;
}
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/reloc.c binutils-2.27-zip/bfd/reloc.c
--- binutils-2.27/bfd/reloc.c 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/reloc.c binutils-2.27-zip/bfd/reloc.c
--- binutils-2.27-original/bfd/reloc.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/bfd/reloc.c 2017-01-04 22:03:52.000000000 -0500
@@ -7697,7 +7697,32 @@
BFD_RELOC_VISIUM_IM16_PCREL
1526,8 → 1526,8
ENDSENUM
BFD_RELOC_UNUSED
CODE_FRAGMENT
diff -Naur '--exclude=*.swp' binutils-2.27/bfd/targets.c binutils-2.27-zip/bfd/targets.c
--- binutils-2.27/bfd/targets.c 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/bfd/targets.c binutils-2.27-zip/bfd/targets.c
--- binutils-2.27-original/bfd/targets.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/bfd/targets.c 2016-12-31 17:37:14.021847080 -0500
@@ -910,6 +910,7 @@
extern const bfd_target xtensa_elf32_le_vec;
1546,8 → 1546,8
#endif /* not SELECT_VECS */
/* Always support S-records, for convenience. */
diff -Naur '--exclude=*.swp' binutils-2.27/binutils/readelf.c binutils-2.27-zip/binutils/readelf.c
--- binutils-2.27/binutils/readelf.c 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/binutils/readelf.c binutils-2.27-zip/binutils/readelf.c
--- binutils-2.27-original/binutils/readelf.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/binutils/readelf.c 2016-12-31 17:40:19.908241961 -0500
@@ -154,6 +154,7 @@
#include "elf/xgate.h"
1610,8 → 1610,8
return reloc_type == 0;
case EM_AARCH64:
diff -Naur '--exclude=*.swp' binutils-2.27/config.sub binutils-2.27-zip/config.sub
--- binutils-2.27/config.sub 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/config.sub binutils-2.27-zip/config.sub
--- binutils-2.27-original/config.sub 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/config.sub 2017-01-11 14:20:34.804049801 -0500
@@ -316,7 +316,7 @@
| visium \
1637,8 → 1637,8
# We use `pc' rather than `unknown'
# because (1) that's what they normally are, and
diff -Naur '--exclude=*.swp' binutils-2.27/configure binutils-2.27-zip/configure
--- binutils-2.27/configure 2016-08-03 03:54:55.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/configure binutils-2.27-zip/configure
--- binutils-2.27-original/configure 2016-08-03 03:54:55.000000000 -0400
+++ binutils-2.27-zip/configure 2017-01-08 20:37:33.566336786 -0500
@@ -3548,6 +3548,9 @@
ft32-*-*)
1670,8 → 1670,8
esac
# If we aren't building newlib, then don't build libgloss, since libgloss
diff -Naur '--exclude=*.swp' binutils-2.27/configure.ac binutils-2.27-zip/configure.ac
--- binutils-2.27/configure.ac 2016-08-03 04:37:38.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/configure.ac binutils-2.27-zip/configure.ac
--- binutils-2.27-original/configure.ac 2016-08-03 04:37:38.000000000 -0400
+++ binutils-2.27-zip/configure.ac 2017-01-08 20:41:54.836485336 -0500
@@ -884,6 +884,9 @@
ft32-*-*)
1703,10 → 1703,10
esac
# If we aren't building newlib, then don't build libgloss, since libgloss
diff -Naur '--exclude=*.swp' binutils-2.27/gas/config/tc-zip.c binutils-2.27-zip/gas/config/tc-zip.c
--- binutils-2.27/gas/config/tc-zip.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/config/tc-zip.c 2017-03-15 23:03:15.801504568 -0400
@@ -0,0 +1,3340 @@
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/config/tc-zip.c binutils-2.27-zip/gas/config/tc-zip.c
--- binutils-2.27-original/gas/config/tc-zip.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/config/tc-zip.c 2019-02-14 20:54:05.341671631 -0500
@@ -0,0 +1,3403 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: tc-zip.c
1728,7 → 1728,7
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
+// Copyright (C) 2016-2018, Gisselquist Technology, LLC
+//
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
1877,6 → 1877,18
+ return nw;
+}
+
+static int fits_within(int nbits, int value) {
+ // -2 fits_within two bits
+ // -1 fits_within two bits
+ // 1 fits_within two bits
+ // 2 does not
+ //
+ if (value > 0)
+ return (value < (1l<<(nbits-1))) ? 1:0;
+ else
+ return (value >= -(1l<<(nbits-1))) ? 1:0;
+}
+
+static uint32_t
+zip_brev(uint32_t v) {
+ unsigned r=0, b;
1947,9 → 1959,9
+ pzipm->r[insn->i_areg].m_subsy = NULL;
+ return;
+ }
+ } else if (insn->i_rp) {
+ } else if (insn->i_rp)
+ bknown = MACH_VUNKNOWN;
+ } else if (ZIP_RNONE == insn->i_breg)
+ else if (ZIP_RNONE == insn->i_breg)
+ // B-Op is an immediate only
+ bknown = MACH_VKNOWN;
+ else if (insn->i_breg >= ZIP_CC)
2005,16 → 2017,22
+
+ if (ZIPC_ALWAYS != insn->i_cnd) {
+#ifdef ZIP_DEBUG
+ fprintf(stderr, "MACHINE, CONDITIONAL\n");
+ fprintf(stderr, "\tMACHINE, CONDITIONAL operation\n");
+#endif
+ if ((ZIPO_LDILO == insn->i_op)
+ &&((av->m_known == MACH_VKNOWN)
+ ||(av->m_known == MACH_VUPPERKNOWN)))
+ ||(av->m_known == MACH_VUPPERKNOWN))) {
+ av->m_known = MACH_VUPPERKNOWN;
+ else if ((ZIPO_LDI == insn->i_op)||(ZIPO_LDIn == insn->i_op))
+ ; // We'll catch this in a moment
+ else
+ } else if ((ZIPO_LDI == insn->i_op)||(ZIPO_LDIn == insn->i_op)){
+ if (((av->m_known == MACH_VKNOWN)
+ ||(av->m_known == MACH_VUPPERKNOWN))
+ &&(((insn->i_imm ^ av->m_value)&& ~0x0ffff)==0)) {
+ av->m_known = MACH_VUPPERKNOWN;
+ } else
+ av->m_known = MACH_VUNKNOWN;
+ } else {
+ av->m_known = MACH_VUNKNOWN;
+}
+ } switch(insn->i_op) {
+ case ZIPO_SUB:
+ av->m_known = (av->m_known==MACH_VKNOWN)
2162,6 → 2180,39
+ pzipm->r[ZIP_PC].m_known = MACH_VUNKNOWN;
+}
+
+static int zip_findnearreg_machine(MACHINEREGS *pzipm, unsigned value) {
+ int bestrg = ZIP_RNONE, bestd, d;
+ int rg;
+
+ bestd = 0x7fffffff;
+ bestrg= ZIP_RNONE;
+
+ for(rg=0; rg<ZIP_CC; rg++) {
+ if (pzipm->r[rg].m_known == MACH_VUNKNOWN)
+ continue;
+ if (pzipm->r[rg].m_known == MACH_VSYMKNOWN)
+ continue;
+ if (pzipm->r[rg].m_known == MACH_VUPPERKNOWN)
+ continue;
+ gas_assert(pzipm->r[rg].m_known == MACH_VKNOWN);
+
+ if (pzipm->r[rg].m_addsy)
+ continue;
+ if (pzipm->r[rg].m_subsy)
+ continue;
+
+ d = abs(pzipm->r[rg].m_value - value);
+ if (d < bestd) {
+ bestd = d;
+ bestrg = rg;
+ }
+ }
+
+ if (fits_within(18,bestd))
+ return bestrg;
+ return ZIP_RNONE;
+}
+
+#ifdef ZIP_DEBUG
+static void
+zip_debug_machine(MACHINEREGS *pzipm) {
2245,8 → 2296,8
+ return 1;
+ switch(c) {
+ case 0: return 1;
+ case OPTION_CIS: zip_param_cis = 1; return 1; break;
+ case OPTION_NOCIS: zip_param_cis = 0; return 1; break;
+ case OPTION_CIS: zip_param_cis = 1; return 1; break;
+ case OPTION_NOCIS: zip_param_cis = 0; return 1; break;
+ case OPTION_ZIPM: zip_param_use_machine = 1; return 1; break;
+ case OPTION_NOZIPM: zip_param_use_machine = 0; return 1; break;
+ // case OPTION_GOT : zip_param_got = 1; return 1; break;
2362,7 → 2413,7
+ case ZIPO_SOUT: fprintf(stderr, "%7s", "SOUT"); break;
+ case ZIPO_NDUMP: fprintf(stderr, "%7s", "NDUMP"); break;
+ case ZIPO_NEXIT: fprintf(stderr, "%7s", "NEXIT"); break;
+ case ZIPO_NOUT: fprintf(stderr, "%7s", "OUT"); break;
+ case ZIPO_NOUT: fprintf(stderr, "%7s", "NOUT"); break;
+ //
+ case ZIPO_LJMP: fprintf(stderr, "%7s", "LJMP"); break;
+ case ZIPO_LJSR: fprintf(stderr, "%7s", "LJSR"); break;
2846,18 → 2897,6
+ return err;
+}
+
+static int fits_within(int nbits, int value) {
+ // -2 fits_within two bits
+ // -1 fits_within two bits
+ // 1 fits_within two bits
+ // 2 does not
+ //
+ if (value > 0)
+ return (value < (1l<<(nbits-1))) ? 1:0;
+ else
+ return (value >= -(1l<<(nbits-1))) ? 1:0;
+}
+
+static const char *zip_parse(const char *line, ZIPIS *insn) {
+ const char *err = NULL, *opstr = NULL;
+ char *alt;
2888,7 → 2927,7
+
+
+#ifdef ZIP_DEBUG
+ fprintf(stderr, "**** Parsing %s\n", line);
+ fprintf(stderr, "\n**** Parsing %s\n", line);
+#endif
+
+ insn->i_naux = 0;
3398,6 → 3437,8
+ case ZIPO_TRAP:
+ insn->i_areg = ZIP_CC;
+ if (insn->i_breg == ZIP_RNONE) {
+ // TRAP instructions *ALWAYS* clear the GIE bit
+ insn->i_imm &= (~0x0020);
+ if (insn->i_cnd == ZIPC_ALWAYS)
+ insn->i_op = ZIPO_LDI;
+ else if (fits_within(16, insn->i_imm))
3405,7 → 3446,7
+ else if (fits_within(18, zip_brev(insn->i_imm)))
+ insn->i_op = ZIPO_BREV;
+ else
+ err = "TRAP immediate not supported";
+ err = "TRAP 18+ bit immediate not supported";
+ } else
+ insn->i_op = ZIPO_MOV;
+ break;
3606,6 → 3647,7
+ // 1. Can't merge anything that's already merged
+ if ((a|b) & 0x80000000)
+ return 0;
+
+ ZIP_OPCODE opa, opb;
+ ZIP_CONDITION ac, bc;
+ int imma, immb;
3640,9 → 3682,9
+ }
+
+ // Prohibit moves to/from user regs to merge
+ if ((opa == ZIPO_MOV)&&(a & 0x44000))
+ if ((opa == ZIPO_MOV)&&(a & 0x42000))
+ return 0;
+ if ((opb == ZIPO_MOV)&&(b & 0x44000))
+ if ((opb == ZIPO_MOV)&&(b & 0x42000))
+ return 0;
+
+ imma = zip_non_cis_immediate(a);
3649,10 → 3691,8
+ immb = zip_non_cis_immediate(b);
+
+ if (!fits_within(8,imma)) {
+ // fprintf(stderr, "As immediate is out of range\n");
+ return 0;
+ } if (!fits_within(8,immb)) {
+ // fprintf(stderr, "Bs immediate is out of range\n");
+ return 0;
+ }
+
3979,6 → 4019,8
+ (insn->i_rp)&&(symbol_get_frag(insn->i_rp->r_sym)==fragP)?1:0,
+ this_segment, insn->i_imm);
+#endif
+ int rg;
+
+ switch(insn->i_op) {
+ case ZIPO_LDI: // May or may not be conditional
+ if ((sym_known)&&(this_segment)
4002,8 → 4044,37
+ // 0.111.x111.11
+ insn->i_aux[0] = 0x7fc00000; // NOOP -- if never used.
+ immv += symv;
+ if ((insn->i_cnd == ZIPC_ALWAYS)
+ &&(zip_param_cis)
+ &&(zip_param_use_machine)&&(pzipm)
+ &&(!fits_within(8,immv))) {
+ // Convert an LDI instruction to a MOV instruction if
+ // it would make that instruction CIS-able.
+
+ if ((rg=zip_findnearreg_machine(pzipm, immv))
+ != ZIP_RNONE) {
+ int d;
+ d = immv - pzipm->r[rg].m_value;
+ if (fits_within(3,d)) {
+ insn->i_op = ZIPO_MOV;
+ insn->i_breg = rg;
+ insn->i_naux = 0;
+ insn->i_imm = d;
+ zip_assemble_insn_words(fragP,
+ seg, insn, relax_state,
+ stretch, pzipm);
+ return;
+ }
+ }
+ }
+
+ if ((!insn->i_rp)&&(insn->i_cnd == ZIPC_ALWAYS)
+ &&(fits_within(23, immv))) {
+ // Can we do this with an ordinary load immediate
+ // instruction?
+ //
+ // If we do this, we'll avoid any opportunity to use
+ // the ZipMachine and move something into this address
+ insn->i_naux = 0;
+ insn->i_code = LDIOP(immv,insn->i_areg);
+ } else if (((!insn->i_rp)||(sym_known))
4019,7 → 4090,8
+ if (insn->i_rp)
+ insn->i_rp->r_type = BFD_RELOC_NONE;
+// 0000 1110 0000 0000 0000 0000 0100 0000
+ } else if ((zip_param_use_machine)&&(pzipm)&&((!insn->i_rp)||(sym_known))
+ } else if ((zip_param_use_machine)&&(pzipm)
+ &&((!insn->i_rp)||(sym_known))
+ &&(pzipm->r[insn->i_areg].m_known)
+ &&(0==((immv^pzipm->r[insn->i_areg].m_value)
+ & 0x0ffff0000))) {
4035,57 → 4107,48
+ pzipm->r[insn->i_areg].m_known = MACH_VUPPERKNOWN;
+ } else
+ pzipm->r[insn->i_areg].m_known = MACH_VKNOWN;
+ } else if ((zip_param_use_machine)&&(pzipm)
+ &&((!insn->i_rp)||(sym_known))
+ &&(pzipm->r[insn->i_areg].m_known)
+ &&((rg=zip_findnearreg_machine(pzipm, immv))!= ZIP_RNONE)
+ &&(fits_within(13,pzipm->r[rg].m_value - immv))) {
+ // Replace LDI with a MOV instruction
+ insn->i_op = ZIPO_MOV;
+ insn->i_breg = rg;
+ insn->i_naux = 0;
+ insn->i_imm = pzipm->r[rg].m_value - immv;
+ zip_assemble_insn_words(fragP, seg, insn,
+ relax_state, stretch, pzipm);
+ return;
+ } else if ((zip_param_use_machine)&&(pzipm)
+ &&((!insn->i_rp)||(sym_known))
+ &&(pzipm->r[insn->i_areg].m_known)
+ &&((rg=zip_findnearreg_machine(pzipm, zip_brev(immv)))!= ZIP_RNONE)
+ &&(fits_within(14,zip_brev(pzipm->r[rg].m_value - immv)))) {
+ // Replace LDI with a MOV instruction
+ insn->i_op = ZIPO_BREV;
+ insn->i_breg = rg;
+ insn->i_naux = 0;
+ insn->i_imm = zip_brev(pzipm->r[rg].m_value - immv);
+ zip_assemble_insn_words(fragP, seg, insn,
+ relax_state, stretch, pzipm);
+ return;
+ } else {
+ //
+ // If the symbol isn't defined, then any immv value
+ // will work--we have to come back anyway.
+ //
+ int known_bypass = 0, i;
+
+ if ((zip_param_use_machine)&&(pzipm)&&(
+ ((!insn->i_rp)
+ &&(!fits_within(4,immv)))
+ ||((insn->i_rp)&&(sym_known)))) {
+ for(i=0; i<14; i++) {
+ int offset = immv-pzipm->r[i].m_value;
+ if ((pzipm->r[i].m_known==MACH_VKNOWN)
+ &&(fits_within(13, offset))
+ &&((insn->i_rp)
+ ||(!fits_within(4, immv)))
+ ) {
+ // Pick the closest value ... if
+ // there's a choice
+ if ((!known_bypass)
+ ||(abs(offset)<known_bypass))
+ continue;
+ insn->i_naux = 0;
+ insn->i_op = ZIPO_MOV;
+ insn->i_breg = i;
+ insn->i_imm = offset;
+
+ insn->i_code = SMPLMOV(
+ insn->i_cnd, offset,
+ i, insn->i_areg);
+ known_bypass = abs(offset);
+ if (known_bypass==0)
+ known_bypass = 1;
+ }
+ } known_bypass = (known_bypass)?1:0;
+ } if (!known_bypass) {
+ // BREV Extension would modify this statement
+ insn->i_naux = 1;
+ insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd,
+ zip_brev(immv)&0x01ffff, insn->i_areg);
+ insn->i_aux[0]=IMMOP(ZIPO_LDILO, insn->i_cnd,
+ (immv&0x0ffff), insn->i_areg);
+ if (insn->i_rp)
+ insn->i_rp->r_type = BFD_RELOC_ZIP_LDI;
+ else if ((zip_param_cis)&&(zip_can_merge(insn->i_code, insn->i_aux[0]))) {
+ insn->i_code = zip_insn_merge(insn->i_code, insn->i_aux[0]);
+ insn->i_naux = 0;
+ }
+ } else {
+fprintf(stderr, "known-bypass\n");
+ // BREV Extension would modify this statement
+ insn->i_naux = 1;
+ insn->i_code = IMMOP(ZIPO_BREV, insn->i_cnd,
+ zip_brev(immv)&0x01ffff, insn->i_areg);
+ insn->i_aux[0]=IMMOP(ZIPO_LDILO, insn->i_cnd,
+ (immv&0x0ffff), insn->i_areg);
+ if (insn->i_rp)
+ insn->i_rp->r_type = BFD_RELOC_ZIP_LDI;
+ else if ((zip_param_cis)&&(zip_can_merge(insn->i_code, insn->i_aux[0]))) {
+ insn->i_code = zip_insn_merge(insn->i_code, insn->i_aux[0]);
+ insn->i_naux = 0;
+ }
+ }
+#ifdef ZIP_DEBUG
5047,8 → 5110,8
+ }
+ }
+}
diff -Naur '--exclude=*.swp' binutils-2.27/gas/config/tc-zip.h binutils-2.27-zip/gas/config/tc-zip.h
--- binutils-2.27/gas/config/tc-zip.h 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/config/tc-zip.h binutils-2.27-zip/gas/config/tc-zip.h
--- binutils-2.27-original/gas/config/tc-zip.h 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/config/tc-zip.h 2017-03-03 09:35:34.527310651 -0500
@@ -0,0 +1,191 @@
+////////////////////////////////////////////////////////////////////////////////
5242,8 → 5305,8
+
+#endif
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/configure.tgt binutils-2.27-zip/gas/configure.tgt
--- binutils-2.27/gas/configure.tgt 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/configure.tgt binutils-2.27-zip/gas/configure.tgt
--- binutils-2.27-original/gas/configure.tgt 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/gas/configure.tgt 2016-12-31 17:44:37.270167826 -0500
@@ -112,6 +112,7 @@
x86_64*) cpu_type=i386 arch=x86_64;;
5262,8 → 5325,8
*-*-aout | *-*-scout) fmt=aout ;;
*-*-cloudabi*) fmt=elf ;;
*-*-dragonfly*) fmt=elf em=dragonfly ;;
diff -Naur '--exclude=*.swp' binutils-2.27/gas/Makefile.am binutils-2.27-zip/gas/Makefile.am
--- binutils-2.27/gas/Makefile.am 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/Makefile.am binutils-2.27-zip/gas/Makefile.am
--- binutils-2.27-original/gas/Makefile.am 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/gas/Makefile.am 2016-12-31 17:45:17.941851449 -0500
@@ -200,6 +200,7 @@
config/tc-xtensa.c \
5281,8 → 5344,8
config/xtensa-relax.h
# OBJ files in config
diff -Naur '--exclude=*.swp' binutils-2.27/gas/Makefile.in binutils-2.27-zip/gas/Makefile.in
--- binutils-2.27/gas/Makefile.in 2016-08-03 04:16:28.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/Makefile.in binutils-2.27-zip/gas/Makefile.in
--- binutils-2.27-original/gas/Makefile.in 2016-08-03 04:16:28.000000000 -0400
+++ binutils-2.27-zip/gas/Makefile.in 2016-12-31 17:49:43.603837948 -0500
@@ -494,6 +494,7 @@
config/tc-xtensa.c \
5329,8 → 5392,8
xtensa-relax.o: config/xtensa-relax.c
@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa-relax.o -MD -MP -MF $(DEPDIR)/xtensa-relax.Tpo -c -o xtensa-relax.o `test -f 'config/xtensa-relax.c' || echo '$(srcdir)/'`config/xtensa-relax.c
@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/xtensa-relax.Tpo $(DEPDIR)/xtensa-relax.Po
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip.exp binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp
--- binutils-2.27/gas/testsuite/gas/zip/zip.exp 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip.exp binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp
--- binutils-2.27-original/gas/testsuite/gas/zip/zip.exp 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip.exp 2017-01-12 22:12:40.839206088 -0500
@@ -0,0 +1,17 @@
+# ZipCPU assembler testsuite
5350,8 → 5413,8
+ # run_dump_test "zip_insn_jsr"
+ # run_dump_test "zip_insn_jsrv"
+}
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.d 2017-01-12 22:01:30.790982203 -0500
@@ -0,0 +1,41 @@
+#as: -novliw
5395,8 → 5458,8
+ 70: 78 89 ff ff BZ +@0x00020073.*$
+ 74: 78 aa 00 00 BNZ +@0xfffe0078.*$
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_add.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_add.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_add.s 2017-01-10 12:00:50.870044337 -0500
@@ -0,0 +1,33 @@
+ .text
5432,8 → 5495,8
+ add 4,pc
+ add.z 131071,pc
+ add.nz -131072,pc
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.d 2017-01-10 10:46:16.957469423 -0500
@@ -0,0 +1,22 @@
+#as:
5458,8 → 5521,8
+
+00000024 <bra_target>:
+ 24: 7f c0 00 00 NOOP
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_bratest.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_bratest.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_bratest.s 2017-01-09 10:28:54.983992877 -0500
@@ -0,0 +1,14 @@
+ .text
5476,8 → 5539,8
+ ldi -1,r0
+bra_target:
+ noop
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.d 2017-01-16 11:02:02.344009430 -0500
@@ -0,0 +1,39 @@
+#as:
5519,8 → 5582,8
+ 68: 00 98 00 01 ADD.C +\$1,R0
+ 6c: 00 b8 00 01 ADD.NC +\$1,R0
+ 70: 00 b8 00 01 ADD.NC +\$1,R0
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_ctest.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_ctest.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_ctest.s 2017-01-16 10:55:53.054697861 -0500
@@ -0,0 +1,34 @@
+ .text
5557,8 → 5620,8
+ [nc] add 1,R0
+ [geu] add 1,R0
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.d 2017-01-10 11:31:45.633275455 -0500
@@ -0,0 +1,24 @@
+#as: -nozipm
5585,8 → 5648,8
+ 2c: 42 03 fe ff BREV +\$-257,R8
+ 30: 4a 01 fe ff LDI +0xff7ffffe,R9.*
+ 34: 4a 40 ff fe
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_lditest.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_lditest.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_lditest.s 2017-01-09 10:28:37.472119620 -0500
@@ -0,0 +1,13 @@
+ .text
5602,8 → 5665,8
+ ldi -8388608,r7
+ ldi -8388609,r8
+ ldi -8388610,r9
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.d 2017-01-12 22:09:54.925246052 -0500
@@ -0,0 +1,86 @@
+#as: -novliw -nozipm
5692,8 → 5755,8
+ c4: 73 40 90 01 MOV +\$-4095\+R2,CC
+ c8: 73 41 0f ff MOV +\$4095\+R4,CC
+ cc: 73 41 80 00 MOV +R6,CC
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_mov.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_mov.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_mov.s 2017-01-12 16:45:17.027962005 -0500
@@ -0,0 +1,93 @@
+ .text
5789,8 → 5852,8
+ mov 4095+r4,cc
+ mov r6,cc
+ ;
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.d 2017-01-12 22:12:11.497444662 -0500
@@ -0,0 +1,98 @@
+#as: -novliw -nozipm
5891,8 → 5954,8
+ 154: 2c 82 00 00 LW +\(\$-131072\),R5
+ 158: 34 c2 00 00 SW +R6,\(\$-131072\)
+ 15c: 17 82 00 00 FPI2F +\$-131072,R2
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_optest.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_optest.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_optest.s 2017-01-12 16:28:47.212542071 -0500
@@ -0,0 +1,119 @@
+ .text
6014,8 → 6077,8
+ ; ldi
+ fpi2f -0x20000,r2
+ ;
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.d 2017-01-10 11:09:36.301473902 -0500
@@ -0,0 +1,32 @@
+#as: -novliw
6050,8 → 6113,8
+ 4c: 04 87 40 20 LW +32\(SP\),R0
+ 50: 68 80 00 30 ADD +\$48,SP
+ 54: 7b 40 00 00 RTN +
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologue.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologue.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologue.s 2017-01-09 07:25:40.495644200 -0500
@@ -0,0 +1,24 @@
+some_function:
6078,8 → 6141,8
+ ADD 48,SP
+ RETN
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.d 2017-01-12 21:58:59.513900839 -0500
@@ -0,0 +1,21 @@
+#as: -nozipm -vliw
6103,8 → 6166,8
+ 20: 84 14 84 18 LW +20\(SP\),R0 +| LW +24\(SP\),R0
+ 24: 84 1c 84 20 LW +28\(SP\),R0 +| LW +32\(SP\),R0
+ 28: ea 30 ff 80 ADD +\$48,SP +| MOV +R0,PC
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_prologuev.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_prologuev.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_prologuev.s 2017-01-10 11:29:18.612449601 -0500
@@ -0,0 +1,24 @@
+some_function:
6131,8 → 6194,8
+ ADD 48,SP
+ RETN
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.d 2017-01-24 08:03:32.892847657 -0500
@@ -0,0 +1,41 @@
+#as:
6176,8 → 6239,8
+ 70: 7f c0 02 27 NOUT R7
+ 74: 7f 80 02 33 SOUT uR3
+ 78: 7f c0 02 38 NOUT uR8
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_specials.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_specials.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_specials.s 2017-01-19 07:18:13.405003668 -0500
@@ -0,0 +1,35 @@
+ .text
6215,8 → 6278,8
+ sout uR3
+ nout uR8
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.d 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.d binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.d 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.d 2017-01-12 21:50:28.719237156 -0500
@@ -0,0 +1,77 @@
+#as: -vliw
6296,8 → 6359,8
+ f0: bb 3f c4 18 CMP +\$63\+R7,R7 +| LW 24\(SP\),R8 *$
+ f4: cd 1c de 7c SW +R9,\$28\(SP\) +| LDI +\$124,R11 *$
+ f8: 1b 40 40 01 MOV +\$1\+R1,R3
diff -Naur '--exclude=*.swp' binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s
--- binutils-2.27/gas/testsuite/gas/zip/zip_insn_vliw.s 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.s binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s
--- binutils-2.27-original/gas/testsuite/gas/zip/zip_insn_vliw.s 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/gas/testsuite/gas/zip/zip_insn_vliw.s 2017-01-12 16:55:54.690241718 -0500
@@ -0,0 +1,110 @@
+ .text
6410,8 → 6473,8
+ mov 1+r1,r3
+
+
diff -Naur '--exclude=*.swp' binutils-2.27/gas/write.c binutils-2.27-zip/gas/write.c
--- binutils-2.27/gas/write.c 2016-08-03 03:36:51.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/gas/write.c binutils-2.27-zip/gas/write.c
--- binutils-2.27-original/gas/write.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27-zip/gas/write.c 2016-12-31 17:51:52.470985149 -0500
@@ -2676,7 +2676,7 @@
6422,8 → 6485,8
addressT after;
if (symbolP)
diff -Naur '--exclude=*.swp' binutils-2.27/include/dis-asm.h binutils-2.27-zip/include/dis-asm.h
--- binutils-2.27/include/dis-asm.h 2016-08-03 03:36:53.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/include/dis-asm.h binutils-2.27-zip/include/dis-asm.h
--- binutils-2.27-original/include/dis-asm.h 2016-08-03 03:36:53.000000000 -0400
+++ binutils-2.27-zip/include/dis-asm.h 2016-12-31 17:52:29.022758231 -0500
@@ -318,10 +318,12 @@
extern int print_insn_rl78_g10 (bfd_vma, disassemble_info *);
6438,8 → 6501,8
extern void print_aarch64_disassembler_options (FILE *);
extern void print_i386_disassembler_options (FILE *);
diff -Naur '--exclude=*.swp' binutils-2.27/include/elf/common.h binutils-2.27-zip/include/elf/common.h
--- binutils-2.27/include/elf/common.h 2016-08-03 03:36:53.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/include/elf/common.h binutils-2.27-zip/include/elf/common.h
--- binutils-2.27-original/include/elf/common.h 2016-08-03 03:36:53.000000000 -0400
+++ binutils-2.27-zip/include/elf/common.h 2016-12-31 17:53:58.942198950 -0500
@@ -411,6 +411,9 @@
/* Old constant that might be in use by some software. */
6451,8 → 6514,8
/* See the above comment before you add a new EM_* value here. */
/* Values for e_version. */
diff -Naur '--exclude=*.swp' binutils-2.27/include/elf/zip.h binutils-2.27-zip/include/elf/zip.h
--- binutils-2.27/include/elf/zip.h 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/include/elf/zip.h binutils-2.27-zip/include/elf/zip.h
--- binutils-2.27-original/include/elf/zip.h 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/include/elf/zip.h 2017-01-18 18:19:33.764898333 -0500
@@ -0,0 +1,58 @@
+////////////////////////////////////////////////////////////////////////////////
6513,8 → 6576,8
+END_RELOC_NUMBERS(R_ZIP_max)
+
+#endif /* _ELF_ZIP_H */
diff -Naur '--exclude=*.swp' binutils-2.27/ld/configure.tgt binutils-2.27-zip/ld/configure.tgt
--- binutils-2.27/ld/configure.tgt 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/configure.tgt binutils-2.27-zip/ld/configure.tgt
--- binutils-2.27-original/ld/configure.tgt 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/ld/configure.tgt 2016-12-31 17:55:04.013793303 -0500
@@ -816,6 +816,8 @@
;;
6525,8 → 6588,8
*-*-ieee*) targ_emul=vanilla
;;
*-tandem-none) targ_emul=st2000
diff -Naur '--exclude=*.swp' binutils-2.27/ld/emulparams/elf32zip.sh binutils-2.27-zip/ld/emulparams/elf32zip.sh
--- binutils-2.27/ld/emulparams/elf32zip.sh 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/emulparams/elf32zip.sh binutils-2.27-zip/ld/emulparams/elf32zip.sh
--- binutils-2.27-original/ld/emulparams/elf32zip.sh 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/ld/emulparams/elf32zip.sh 2017-01-05 08:22:45.000000000 -0500
@@ -0,0 +1,50 @@
+################################################################################
6579,8 → 6642,8
+COMMONPAGESIZE=0x1000
+EMBEDDED=yes
+
diff -Naur '--exclude=*.swp' binutils-2.27/ld/Makefile.am binutils-2.27-zip/ld/Makefile.am
--- binutils-2.27/ld/Makefile.am 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/Makefile.am binutils-2.27-zip/ld/Makefile.am
--- binutils-2.27-original/ld/Makefile.am 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/ld/Makefile.am 2016-12-31 17:57:39.684819835 -0500
@@ -286,6 +286,7 @@
eelf32xc16xs.c \
6600,8 → 6663,8
eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
$(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
diff -Naur '--exclude=*.swp' binutils-2.27/ld/Makefile.in binutils-2.27-zip/ld/Makefile.in
--- binutils-2.27/ld/Makefile.in 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/ld/Makefile.in binutils-2.27-zip/ld/Makefile.in
--- binutils-2.27-original/ld/Makefile.in 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/ld/Makefile.in 2016-12-31 17:59:30.788122513 -0500
@@ -654,6 +654,7 @@
eelf32xc16xs.c \
6629,8 → 6692,8
eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \
$(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/configure binutils-2.27-zip/opcodes/configure
--- binutils-2.27/opcodes/configure 2016-08-03 04:33:39.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/configure binutils-2.27-zip/opcodes/configure
--- binutils-2.27-original/opcodes/configure 2016-08-03 04:33:39.000000000 -0400
+++ binutils-2.27-zip/opcodes/configure 2017-01-05 08:50:32.000000000 -0500
@@ -12685,7 +12685,7 @@
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
6641,8 → 6704,8
"") ;;
*) as_fn_error "*** unknown target architecture $arch" "$LINENO" 5 ;;
esac
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/configure.ac binutils-2.27-zip/opcodes/configure.ac
--- binutils-2.27/opcodes/configure.ac 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/configure.ac binutils-2.27-zip/opcodes/configure.ac
--- binutils-2.27-original/opcodes/configure.ac 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/opcodes/configure.ac 2017-01-05 08:49:53.000000000 -0500
@@ -353,7 +353,7 @@
bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;;
6653,8 → 6716,8
"") ;;
*) AC_MSG_ERROR(*** unknown target architecture $arch) ;;
esac
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/disassemble.c binutils-2.27-zip/opcodes/disassemble.c
--- binutils-2.27/opcodes/disassemble.c 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/disassemble.c binutils-2.27-zip/opcodes/disassemble.c
--- binutils-2.27-original/opcodes/disassemble.c 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/opcodes/disassemble.c 2016-12-31 18:02:03.139162969 -0500
@@ -98,6 +98,7 @@
#define ARCH_xtensa
6676,8 → 6739,8
#ifdef ARCH_vax
case bfd_arch_vax:
disassemble = print_insn_vax;
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/Makefile.am binutils-2.27-zip/opcodes/Makefile.am
--- binutils-2.27/opcodes/Makefile.am 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/Makefile.am binutils-2.27-zip/opcodes/Makefile.am
--- binutils-2.27-original/opcodes/Makefile.am 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/opcodes/Makefile.am 2017-01-05 08:28:32.000000000 -0500
@@ -86,7 +86,9 @@
w65-opc.h \
6709,8 → 6772,8
POTFILES = $(HFILES) $(CFILES)
po/POTFILES.in: @MAINT@ Makefile
for f in $(POTFILES); do echo $$f; done | LC_ALL=C sort > tmp \
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/Makefile.in binutils-2.27-zip/opcodes/Makefile.in
--- binutils-2.27/opcodes/Makefile.in 2016-08-03 03:36:54.000000000 -0400
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/Makefile.in binutils-2.27-zip/opcodes/Makefile.in
--- binutils-2.27-original/opcodes/Makefile.in 2016-08-03 03:36:54.000000000 -0400
+++ binutils-2.27-zip/opcodes/Makefile.in 2017-01-05 08:28:04.000000000 -0500
@@ -386,7 +386,9 @@
w65-opc.h \
6743,10 → 6806,10
.c.o:
@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-dis.c binutils-2.27-zip/opcodes/zip-dis.c
--- binutils-2.27/opcodes/zip-dis.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/opcodes/zip-dis.c 2017-03-03 09:34:03.983308793 -0500
@@ -0,0 +1,474 @@
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-dis.c binutils-2.27-zip/opcodes/zip-dis.c
--- binutils-2.27-original/opcodes/zip-dis.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/opcodes/zip-dis.c 2018-03-22 17:57:34.688834861 -0400
@@ -0,0 +1,527 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: zip-dis.c
6836,6 → 6899,25
+ // 0111.1000.10cc.c0ii.iiii.iiii.iiii.iiii
+ if ((nxtword&0xffc40000) == 0x78800000)
+ return 1;
+ // OR ... the second word could be a
+ // load into the PC
+ // 0.1111.10010.ccc.0.iiiiiiiiiiiiiiiiii LW.X #imm,PC
+ // 0.1111.10010.ccc.1.rrrr.iiiiiiiiiiiiii LW.X #(R),PC
+ //
+ // These must be unconditional, since the MOV above is
+ // also unconditional
+ // 0111.1100.10cc.cxxxxx.... LW.X #(R),PC
+ if ((nxtword&0xfff80000) == 0x7c800000)
+ return 1;
+ //
+ // OR ... the second word could be a
+ // Register move into the PC from the current
+ // register set
+ // 0.1111.01101.ccc.0.rrrr.0.iiiiiiiiiiiii MOV #(R),PC
+ // 0111.1011.01cc.c0rr.rr0i.iiiiiiiiiiii MOV #(R),PC
+ if ((nxtword&0xfffc2000) == 0x7b400000)
+ return 1;
+ //
+ return 0;
+}
+
6851,7 → 6933,7
+}
+
+static inline int
+TWOWORD_CIS_JSR(uint32_t iword) {
+TWOWORD_CIS_LJSR(uint32_t iword) {
+ // MOV 2(PC) | LOD (PC),PC
+ //
+ // 1.0000.111.1.1111.010
6863,7 → 6945,7
+
+static inline int
+CIS_JSR(uint32_t iword __attribute__((unused)) ) {
+ if (TWOWORD_CIS_JSR(iword))
+ if (TWOWORD_CIS_LJSR(iword))
+ return 1;
+ // MOV 1(PC) | MOV Rx,PC
+ //
6885,7 → 6967,7
+ // MOV 2(PC),PC
+ if (iword == 0x0343c002)
+ return 1;
+ if (TWOWORD_CIS_JSR(iword))
+ if (TWOWORD_CIS_LJSR(iword))
+ return 1;
+ // The conditional LJMP is three words, which we don't handle ...
+ // Any BREV command could be the beginning of a twoword instruction
6959,18 → 7041,52
+
+ return;
+ } else if (TWOWORD_JSR(ins, nxtword)) {
+ int cv = zip_getbits(nxtword, ZIP_BITFIELD(3,19));
+ int iv = zip_sbits(nxtword, 18);
+ if ((nxtword&0xffc40000) == 0x78800000) {
+ int cv = zip_getbits(nxtword, ZIP_BITFIELD(3,19));
+ int iv = zip_sbits(nxtword, 18);
+
+ *refaddr = iv + addr + 8;
+ sprintf(line, "%s%s", "JSR", zip_ccstr[cv]);
+ sprintf(line, "%-11s", line);
+ sprintf(line, "%s0x%08x", line, *refaddr);
+ *refaddr = iv + addr + 8;
+ sprintf(line, "%s%s", "JSR", zip_ccstr[cv]);
+ sprintf(line, "%-11s", line);
+ sprintf(line, "%s0x%08x", line, *refaddr);
+
+ return;
+ } else if (TWOWORD_CIS_JSR(ins)) {
+ return;
+ } else if ((nxtword&0xfff80000) == 0x7c800000) {
+ // OR ... the second word could be a load into the PC
+ if ((nxtword>>18)&1) {
+ // LW #(Rw),PC
+ int iv = zip_sbits(nxtword, 14);
+ int rb = zip_ubits(nxtword>>14, 4);
+
+ sprintf(line,"%-11s#%d(%s)", "IJSR", iv,
+ zip_regstr[rb]);
+ *refaddr = 0;
+ } else {
+ // LW (#),PC
+ int iv = zip_sbits(nxtword, 18);
+ sprintf(line,"%-11s(#%d)", "IJSR", iv);
+ *refaddr = iv;
+ }
+ return;
+ } else { // if ((nxtword&0xfffc2000) == 0x7b400000)
+ // OR ... the second word could be a register move into
+ // the PC from the current register set
+ int rb = zip_ubits(nxtword>>14, 4);
+ int iv = zip_sbits(nxtword, 13);
+
+ *refaddr = 0;
+ if (iv == 0)
+ sprintf(line, "%-11s %s", "JSR",
+ zip_regstr[rb]);
+ else
+ sprintf(line, "%-11s#%d+%s", "JSR",iv,
+ zip_regstr[rb]);
+
+ return;
+ }
+ } else if (TWOWORD_CIS_LJSR(ins)) {
+ *refaddr = nxtword;
+ sprintf(line, "%-11s", "JSR");
+ sprintf(line, "%-11s", "LJSR");
+ sprintf(line, "%s0x%08x", line, *refaddr);
+ return;
+ } else if (CIS_JSR(ins)) {
7168,7 → 7284,7
+ if ((*info->read_memory_func)(vma, ibytes, 12, info) ==0)
+ refaddr = (ibytes[8]<<24)|(ibytes[9]<<16)|(ibytes[10]<<8)|(ibytes[11]);
+ sprintf(&astr[strlen(astr)], "@0x%08x", refaddr);
+ } else if (TWOWORD_CIS_JSR(iword)) {
+ } else if (TWOWORD_CIS_LJSR(iword)) {
+ refaddr = nxtword;
+ sprintf(astr, "%-11s0x%08x", "JSR", refaddr);
+ } else
7209,7 → 7325,7
+ return 8;
+ if (TWOWORD_JSR(iword,nxtword))
+ return 8;
+ if (TWOWORD_CIS_JSR(iword))
+ if (TWOWORD_CIS_LJSR(iword))
+ return 8;
+ return 4;
+}
7221,8 → 7337,8
+ return print_zip_insn;
+}
+
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-dis.h binutils-2.27-zip/opcodes/zip-dis.h
--- binutils-2.27/opcodes/zip-dis.h 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-dis.h binutils-2.27-zip/opcodes/zip-dis.h
--- binutils-2.27-original/opcodes/zip-dis.h 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/opcodes/zip-dis.h 2016-12-31 18:10:03.512012534 -0500
@@ -0,0 +1,45 @@
+////////////////////////////////////////////////////////////////////////////////
7270,9 → 7386,9
+zip_get_disassembler(bfd *abfd);
+
+#endif
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-opc.c binutils-2.27-zip/opcodes/zip-opc.c
--- binutils-2.27/opcodes/zip-opc.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/opcodes/zip-opc.c 2017-03-06 14:00:55.404955681 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-opc.c binutils-2.27-zip/opcodes/zip-opc.c
--- binutils-2.27-original/opcodes/zip-opc.c 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/opcodes/zip-opc.c 2018-06-07 10:35:06.439245343 -0400
@@ -0,0 +1,362 @@
+////////////////////////////////////////////////////////////////////////////////
+//
7524,54 → 7640,54
+ // 1111.1000.10xc.c0ii.iixx.xxxx.xxxx.xxxx
+ // Mask, val, result, Ra, Rb, I, condition (no conditions for OP_UNDER_TEST)
+ // BRA: 1.1111.011.0.sssssss
+ { "BRA", 0xff800000, 0xf9000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "BRA", 0xff800000, 0xf9000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ // CLR: 1.rrrr.110.00000000
+ { "CLR", 0x87ff0000, 0x86000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
+ { "CLR", 0x87ff0000, 0x86000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
+ // RTN: 1.1111.111.0.0000.000, MOV R0,Pc
+ { "RTN", 0xffff0000, 0xff800000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
+ { "RTN", 0xffff0000, 0xff800000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED },
+ // JMP: 1.1111.111.0.rrrrsss
+ { "JMP", 0xff800000, 0xff000000, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ { "JMP", 0xff800000, 0xff000000, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ // LJSR: 1.000_0.011_.0.111_1.001 ?.1111.110.1.1111.000
+ // { "LJSR",0xffffffff, 0x83797ef8, ZIP_REGFIELD(27),ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ //
+ // 1.rrrr.000.0.sssssss
+ // 1rrr.r000.0sss.ssss
+ { "SUB", 0x87800000, 0x80000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "SUB", 0x87800000, 0x80000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ // 1.rrrr.000.1.rrrrsss
+ { "SUB", 0x87800000, 0x80800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ //
+ // 1.rrrr.001.0.sssssss
+ // 1.rrrr.001.1.rrrrsss
+ { "AND", 0x87800000, 0x81000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "AND", 0x87800000, 0x81000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "AND", 0x87800000, 0x81800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ //
+ // 1.rrrr.010.0.sssssss
+ // 1.rrrr.010.1.rrrrsss
+ { "ADD", 0x87800000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "ADD", 0x87800000, 0x82000000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "ADD", 0x87800000, 0x82800000, ZIP_REGFIELD(27), ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ //
+ // 1.rrrr.011.a.rrrrsss
+ { "CMP", 0x87800000, 0x83000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "CMP", 0x87800000, 0x83800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ { "CMP", 0x87800000, 0x83000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "CMP", 0x87800000, 0x83800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ //
+ // 1.rrrr.100.0.sssssss
+ // 1.rrrr.100.1.rrrrsss
+ { "LW", 0x87800000, 0x84000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "LW", 0x87800000, 0x84800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ { "LW", 0x87800000, 0x84000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "LW", 0x87800000, 0x84800000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ // 1.rrrr.101.ssssssss
+ { "SW", 0x87800000, 0x85000000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ { "SW", 0x87800000, 0x85000000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_SP, ZIP_IMMFIELD(7,16), ZIP_OPUNUSED },
+ // 1.rrrr.110.0.sssssss
+ { "SW", 0x87800000, 0x85800000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ { "SW", 0x87800000, 0x85800000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ // 1.rrrr.110.iiiiiiii
+ { "LDI", 0x87000000, 0x86000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(8,16), ZIP_OPUNUSED },
+ { "LDI", 0x87000000, 0x86000000, ZIP_REGFIELD(27), ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(8,16), ZIP_OPUNUSED },
+ // 1.rrrr.111.1.sssssss
+ { "MOV", 0x87800000, 0x87800000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ { "MOV", 0x87800000, 0x87800000, ZIP_OPUNUSED, ZIP_REGFIELD(27), ZIP_REGFIELD(19), ZIP_IMMFIELD(3,16), ZIP_OPUNUSED },
+ //
+ // 1.rrrr.111.1.rrrrsss
+ // Illegal instruction !!
+ { "ILLV", 0x80000000, 0x80000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(32,16), ZIP_OPUNUSED },
+ // Global illegal instruction
+ { "ILL", 0x00000000, 0x00000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(32,0), ZIP_OPUNUSED }
+ { "ILL", 0x00000000, 0x00000000, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_OPUNUSED, ZIP_IMMFIELD(32,0), ZIP_OPUNUSED }
+};
+
+static const ZOPCODE zip_opbottomlist_raw[] = {
7636,8 → 7752,8
+const int nzip_oplist = (sizeof(zip_oplist_raw)/sizeof(ZOPCODE));
+const int nzip_opbottom = (sizeof(zip_opbottomlist_raw)/sizeof(ZOPCODE));
+
diff -Naur '--exclude=*.swp' binutils-2.27/opcodes/zip-opc.h binutils-2.27-zip/opcodes/zip-opc.h
--- binutils-2.27/opcodes/zip-opc.h 1969-12-31 19:00:00.000000000 -0500
diff -Naur '--exclude=*.swp' binutils-2.27-original/opcodes/zip-opc.h binutils-2.27-zip/opcodes/zip-opc.h
--- binutils-2.27-original/opcodes/zip-opc.h 1969-12-31 19:00:00.000000000 -0500
+++ binutils-2.27-zip/opcodes/zip-opc.h 2017-02-10 17:48:01.761470841 -0500
@@ -0,0 +1,77 @@
+////////////////////////////////////////////////////////////////////////////////
/gcc-script.sh
6,8 → 6,8
## Project: Zip CPU -- a small, lightweight, RISC CPU soft core
##
## Purpose: To handle all of the GCC configuration options properly. This
## both runs the GCC configure script, as well as initially running
## make on the resulting configured directory.
## runs the GCC configure script, using options known to work
## with the ZipCPU.
##
##
## Creator: Dan Gisselquist, Ph.D.
60,7 → 60,16
set -e
CLFS_HOST=$MACHTYPE
CLFS_TARGET="zip"
INSTALL_BASE=`pwd`/install
if [[ -z "$INSTALLD" ]]
then
INSTALLD=`pwd`/install
fi
if [[ ! $(which zip-as) ]]
then
echo "GCC-script ERROR: Unable to find zip-as, the ZipCPU assembler, in your path"
exit -1
fi
INSTALL_BASE=${INSTALLD}
mkdir -p ${INSTALL_BASE}/cross-tools
mkdir -p ${INSTALL_BASE}/tools/lib
mkdir -p ${INSTALL_BASE}/usr/include
79,7 → 88,7
--disable-multilib \
--disable-threads --disable-tls \
--enable-checking --disable-nls \
--without-fp --with-newlib
--with-newlib
 
echo $PATH | grep ${INSTALL_BASE}/cross-tools/bin \
|| export PATH=$PATH:${INSTALL_BASE}/cross-tools/bin
/gcc-zippatch.patch
162,12 → 162,13
# If we aren't building newlib, then don't build libgloss, since libgloss
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c
--- gcc-6.2.0/gcc/cfgexpand.c 2016-04-27 08:23:50.000000000 -0400
+++ gcc-6.2.0-zip/gcc/cfgexpand.c 2016-12-31 16:38:36.195534819 -0500
@@ -74,6 +74,15 @@
+++ gcc-6.2.0-zip/gcc/cfgexpand.c 2018-06-05 21:18:19.438798488 -0400
@@ -74,6 +74,16 @@
#include "tree-chkp.h"
#include "rtl-chkp.h"
+
+// #define DO_ZIP_DEBUGS
+#ifdef DO_ZIP_DEBUGS
+#include <stdio.h>
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
179,7 → 180,7
/* Some systems use __main in a way incompatible with its use in gcc, in these
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
give the same symbol without quotes for an alternative entry point. You
@@ -1172,7 +1181,7 @@
@@ -1172,7 +1182,7 @@
base_align = crtl->max_used_stack_slot_alignment;
else
base_align = MAX (crtl->max_used_stack_slot_alignment,
188,7 → 189,7
<< ASAN_SHADOW_SHIFT);
}
else
@@ -2225,7 +2234,7 @@
@@ -2225,7 +2235,7 @@
data.asan_vec.safe_push (offset);
/* Leave space for alignment if STRICT_ALIGNMENT. */
if (STRICT_ALIGNMENT)
197,7 → 198,7
<< ASAN_SHADOW_SHIFT)
/ BITS_PER_UNIT, 1);
@@ -5745,7 +5754,7 @@
@@ -5745,7 +5755,7 @@
&& (last = get_last_insn ())
&& JUMP_P (last))
{
300,6 → 301,232
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops gcc-6.2.0-zip/gcc/config/zip/genzipops
--- gcc-6.2.0/gcc/config/zip/genzipops 1969-12-31 19:00:00.000000000 -0500
+++ gcc-6.2.0-zip/gcc/config/zip/genzipops 2018-03-22 18:33:09.823726748 -0400
@@ -0,0 +1,201 @@
+•ui Ÿø?` À@`@` @`(@`0@`8@`@@`H@`P@`X@` +x@`€@`HƒìH‹9 H…ÀtèHƒÄÃÿ59 ÿ%9 @ÿ%9 héàÿÿÿÿ%ú8 héÐÿÿÿÿ%ò8 héÀÿÿÿÿ%ê8 hé°ÿÿÿÿ%â8 hé ÿÿÿÿ%Ú8 héÿÿÿÿ%Ò8 hé€ÿÿÿÿ%Ê8 hépÿÿÿÿ%Â8 hé`ÿÿÿÿ%º8 h éPÿÿÿÿ%²8 h +éÿÿÿÿ%8 f1íI‰Ñ^H‰âHƒäðPTIÇÀð@HÇÁ€@HÇÇ>@è7ÿÿÿôfD¸¯@`UH-¨@`HƒøH‰åv¸H…Àt]¿¨@`ÿàf„]Ã@f.„¾¨@`UHî¨@`HÁþH‰åH‰ðHÁè?HÆHÑþt¸H…Àt ]¿¨@`ÿà]ÃfD€=8 uUH‰åènÿÿÿ]Æþ7 óÃ@¿ >`Hƒ?u듸H…ÀtñUH‰åÿÐ]ézÿÿÿUH‰åHƒìH‰}øH‹EøH‰Áº¸¾¿@èÃþÿÿÉÃUH‰åHƒìH‰}øH‰uðH‹UðH‹Eø¾Á @H‰Ç¸è6þÿÿÉÃUH‰åHƒì0H‰}øH‰uðH‰UèH‰MàL‰EØL‰MÐH‹}èH‹uÐH‹MÐH‹UðH‹EøHƒìÿuÿuØÿuàI‰ùI‰ð¾Ð @H‰Ç¸èÚýÿÿHƒÄ ÉÃUH‰åHìÐH‰½hÿÿÿH‰µ`ÿÿÿH‰•XÿÿÿH‰PÿÿÿL‰…HÿÿÿL‰@ÿÿÿH‹EH‰…8ÿÿÿdH‹%(H‰Eø1ÀH‹•8ÿÿÿH…pÿÿÿ¾³!@H‰Ç¸è¤ýÿÿH‹•8ÿÿÿH‹…hÿÿÿ¾È!@H‰Ç¸èDýÿÿH‹½8ÿÿÿH‹µPÿÿÿH‹XÿÿÿH‹•`ÿÿÿH‹…hÿÿÿHƒìÿµ`ÿÿÿI‰ùI‰ð¾ð!@H‰Ç¸èÿüÿÿHƒÄH‹½8ÿÿÿH‹µPÿÿÿH‹@ÿÿÿH‹•`ÿÿÿH‹…hÿÿÿHƒìÿµ`ÿÿÿI‰ùI‰ð¾€"@H‰Ç¸è¶üÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìh?#@A¹<#@I‰øH‰ÇèBþÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhD#@A¹A#@I‰øH‰ÇèþÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhJ#@A¹G#@I‰øH‰ÇèÀýÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhP#@A¹M#@I‰øH‰ÇèýÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhW#@A¹S#@I‰øH‰Çè>ýÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìh]#@A¹Y#@I‰øH‰ÇèýüÿÿHƒÄH‹EødH3%(tèçúÿÿÉÃUH‰åHì€H‰½¨ùÿÿH‰µ ùÿÿH‰•˜ùÿÿH‰ùÿÿL‰…ˆùÿÿdH‹%(H‰Eø1ÀH‹•˜ùÿÿH…ðùÿÿ¾`#@H‰Ç¸èøúÿÿH‹•˜ùÿÿH…ðûÿÿ¾$@H‰Ç¸èØúÿÿH‹•˜ùÿÿH…ðýÿÿ¾8$@H‰Ç¸è¸úÿÿL…ðýÿÿH½ðûÿÿH‹ùÿÿH•ðùÿÿH‹µ ùÿÿH‹…¨ùÿÿHƒìÿµˆùÿÿM‰ÁI‰øH‰ÇècüÿÿHƒÄH‹•˜ùÿÿH…ðùÿÿ¾¸$@H‰Ç¸èRúÿÿH‹•˜ùÿÿH…ðûÿÿ¾ˆ%@H‰Ç¸è2úÿÿH‹•˜ùÿÿH…ðýÿÿ¾Ø%@H‰Ç¸èúÿÿH‹• ùÿÿH…°ùÿÿ¾Š&@H‰Ç¸èòùÿÿL…ðýÿÿH½ðûÿÿH‹ùÿÿH•ðùÿÿHµ°ùÿÿH‹…¨ùÿÿHƒìÿµˆùÿÿM‰ÁI‰øH‰ÇèûÿÿHƒÄH‹EødH3%(tè'ùÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøHƒìÿuàÿuàÿuàI‰ùI‰ð¾˜&@H‰Ç¸èùÿÿHƒÄ ÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾(@H‰Ç¸è¹øÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾`)@H‰Ç¸èrøÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾ˆ*@H‰Ç¸è+øÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾˜+@H‰Ç¸èä÷ÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾à,@H‰Ç¸è÷ÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾(.@H‰Ç¸èV÷ÿÿÉÃUH‰å¿p/@èåöÿÿ]ÃUH‰åAUATSHƒì(‰}ÌH‰uÀH‹?0 ¾²/@H‰Çè:÷ÿÿH‰EØH‹/0 H‰EЃ}Ì~!H‹EÀHƒÀH‹¶<-uè›ÿÿÿ¿è4÷ÿÿƒ}ÌŽ´H‹EÀHƒÀH‹H‰Çè‡öÿÿH‰ÃH‹Ý/ H‰ÇèuöÿÿH9Ãr~H‹É/ H‹EÀHƒÀL‹ H‹EÀHƒÀH‹H‰ÇèKöÿÿI‰ÅH‹¡/ H‰Çè9öÿÿI)ÅL‰èLàH‰ÞH‰ÇèUöÿÿ…Àu/H‹EÀHƒÀH‹¾H‰ÇèYöÿÿ…ÀuH‹EÀHƒÀH‹H‰ÇèÂõÿÿH‹EÀH‹@H‰EÐH‹EØH‰Çè÷ÿÿH‹EØA¸´/@¹¸/@º¹/@¾Á/@H‰ÇèäúÿÿH‹EØA¸È/@¹¸/@ºÌ/@¾Õ/@H‰ÇèÃúÿÿH‹EØA¸Ü/@¹¸/@ºà/@¾è/@H‰Çè¢úÿÿH‹EØA¸ï/@¹ô/@º0@¾0@H‰ÇèúÿÿH‹EØA¸0@¹ô/@º0@¾0@H‰Çè`úÿÿH‹EØA¸$0@¹¸/@º(0@¾/0@H‰Çè?úÿÿH‹EØA¸60@¹¸/@º90@¾@0@H‰ÇèúÿÿH‹EØA¸G0@¹¸/@ºK0@¾R0@H‰ÇèýùÿÿH‹EØA¸Y0@¹¸/@º]0@¾i0@H‰ÇèÜùÿÿH‹EØA¸q0@¹¸/@ºu0@¾0@H‰Çè»ùÿÿH‹EØA¸‡0@¹¸/@º‹0@¾—0@H‰ÇèšùÿÿH‹EØHƒìh3@A¹ 0@A¸x1@¹ ++2@º2@¾3@H‰Çè¬öÿÿHƒÄH‹EØHƒìh5@A¹ 3@A¸ø3@¹ ++2@º4@¾5@H‰ÇèxöÿÿHƒÄH‹Eؾ–5@H‰ÇèÖõÿÿH‹Eع?#@º<#@¾´5@H‰ÇèÆúÿÿH‹EعD#@ºA#@¾´5@H‰Çè«úÿÿH‹EعJ#@ºG#@¾´5@H‰ÇèúÿÿH‹EعP#@ºM#@¾´5@H‰ÇèuúÿÿH‹EعW#@ºS#@¾´5@H‰ÇèZúÿÿH‹Eع]#@ºY#@¾´5@H‰Çè?úÿÿH‹Eؾ¹5@H‰Çè#õÿÿH‹Eع?#@º<#@¾Ö5@H‰ÇèkúÿÿH‹EعD#@ºA#@¾Ö5@H‰ÇèPúÿÿH‹EعJ#@ºG#@¾Ö5@H‰Çè5úÿÿH‹EعP#@ºM#@¾Ö5@H‰ÇèúÿÿH‹EعW#@ºS#@¾Ö5@H‰ÇèÿùÿÿH‹Eع]#@ºY#@¾Ö5@H‰ÇèäùÿÿH‹Eؾà5@H‰ÇèpôÿÿH‹Eع?#@º<#@¾6@H‰ÇèFúÿÿH‹EعD#@ºA#@¾6@H‰Çè+úÿÿH‹EعJ#@ºG#@¾6@H‰ÇèúÿÿH‹EعP#@ºM#@¾6@H‰ÇèõùÿÿH‹EعW#@ºS#@¾6@H‰ÇèÚùÿÿH‹Eع]#@ºY#@¾6@H‰Çè¿ùÿÿH‹Eؾ6@H‰Çè½óÿÿH‹Eع?#@º<#@¾"6@H‰ÇèLùÿÿH‹EعD#@ºA#@¾"6@H‰Çè1ùÿÿH‹EعJ#@ºG#@¾"6@H‰ÇèùÿÿH‹EعP#@ºM#@¾"6@H‰ÇèûøÿÿH‹EعW#@ºS#@¾"6@H‰ÇèàøÿÿH‹Eع]#@ºY#@¾"6@H‰ÇèÅøÿÿH‹Eؾ'6@H‰Çè +M( H‹n( H‹Uо6@H‰Ç¸èïÿÿ¿è^ïÿÿ¿èTïÿÿ@AWAVA‰ÿAUATL%~% UH-~% SI‰öI‰ÕL)åHƒìHÁýè'îÿÿH…ít 1Û„L‰êL‰öD‰ÿAÿÜHƒÃH9ëuêHƒÄ[]A\A]A^A_Ãf.„óÃHƒìHƒÄÃ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ++;; Filename: zip-ops.md ++;; ++;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core ++;; ++;; Purpose: This is a computer generated machine description of the ++;; ZipCPU's operations. It is computer generated simply for ++;; two reasons. First, I can't seem to find a way to generate this ++;; information within GCC's current constructs. Specifically, the ++;; CPU's instructions normally set the condition codes, unless they ++;; are conditional instructions when they don't. Second, the ZipCPU is ++;; actually quite regular. Almost all of the instructions have the same ++;; form. This form turns into many, many RTL instructions. Because the ++;; CPU doesn't match any of the others within GCC, that means either ++;; I have a *lot* of cut, copy, paste, and edit to do to create the file ++;; and upon any and every edit, or I need to build a program to generate ++;; the remaining .md constructs. Hence, I chose the latter to minimize ++;; the amount of work I needed to do. ++;; ++;; ++;; Creator: Dan Gisselquist, Ph.D. ++;; Gisselquist Technology, LLC ++;; ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ++;; Copyright (C) 2017, Gisselquist Technology, LLC ++;; ++;; This program is free software (firmware): you can redistribute it and/or ++;; modify it under the terms of the GNU General Public License as published ++;; by the Free Software Foundation, either version 3 of the License, or (at ++;; your option) any later version. ++;; ++;; This program is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or ++;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++;; for more details. ++;; ++;; License: GPL, v3, as defined and found on www.gnu.org, ++;; http://www.gnu.org/licenses/gpl.html ++;; ++;; ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ++;; ++; ++; ++; %s ++; ++; ++(define_insn "%s_%s" ++ [(cond_exec (%s (reg:CC CC_REG) (const_int 0)) ++ %s)] ++ "%s" ; Condition ++ "%s.%s\t%%1,%%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++%s (genzipop_long); ++; ++; ++; %s (genzipop_long) ++; ++; ++; ++(define_insn "%s" ++ [%s ++ (clobber (reg:CC CC_REG))] ++ "%s" ++ "%s\t%%2,%%0 ; %s" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "%s_raw" ++ [%s ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "%s" ++ "%s\t%%1,%%0 ; %s_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++eqZneNZltLTgeGEltuCgeuNC(set (match_operand:SI 0 "register_operand" "=r") ++ (%s (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))(set (match_operand:SI 0 "register_operand" "=r") ++ (%s (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))(set (match_operand:SI 0 "register_operand" "=r") ++ (%s (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N"))))(set (match_dup 0) (%s (match_dup 0) ++ (plus:SI (match_dup 2) (match_dup 3))))(set (match_operand:SI 0 "register_operand" "=r") ++ (%s (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N"))))%s_off; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.%s %%1,%%0 ; cmov ++ LW.%s %%1,%%0 ; cmov ++ LDI.%s %%1,%%0 ; cmov ++ SW.%s %%1,%%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.%s %%1,%%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.%s %%0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.%s %%0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.%s %%1,%%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.%s %%1,%%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "%s_%s" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.%s %%1,%%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++USAGE: genzipops .zip-ops.mdzip-ops.mdwADDplus:SIaddsi3SUBminus:SIsubsi3MPYmult:SImulsi3DIVS(ZIP_DIVIDE)div:SIdivsi3DIVUudiv:SIudivsi3ANDand:SIandsi3ORior:SIiorsi3XORxor:SIxorsi3ASRashiftrt:SIashrsi3LSLashift:SIashlsi3LSRlshiftrt:SIlshrsi3(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32))))(set (match_dup 0) ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 1)) ++ (sign_extend:DI (match_dup 2))) ++ (const_int 32))))(ZIP_HAS_DI)(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" "0")) ++ (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO"))) ++ (const_int 32))))smulsi_highpartMPYSHI(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32))))(set (match_dup 0) ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 1)) ++ (zero_extend:DI (match_dup 2))) ++ (const_int 32))))(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) ++ (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO"))) ++ (const_int 32))))umulsi_highpartMPYUHIConditional move instructionscmovConditional add instructionscaddConditional negate instructionscnegConditional not instructionscnotConditional and instructionscandConditional ior instructionsciorConditional xor instructionscxorERR: Could not create %s, leaving results in %s +ô@>`>`õþÿo˜@X@À@ ++« @`Pˆ@X@0 þÿÿo(@ÿÿÿoðÿÿo@(>`@&@6@F@V@f@v@†@–@¦@¶@Æ@Ö@æ@›/@§/@GCC: (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 201606098@T@t@˜@À@X@@(@ X@ +ð@@ô@@Ä6@`7@>`>` >`(>`ø?`@`ˆ@`À@`ñÿ  >`0@p@.°@DÈ@`S>`zÐ@†>`¥ñÿñÿ±ð9@¿ >`ñÿË>`Ü(>`å>`øÄ6@ @`!ð@1Ÿ@G9M - ˆ@`i+@Xqƒ @`Œk @À•M @`£˜@`«¨@`²+ô@ÆÚö­ @¾Ê@G +ˆ@`8LX@GTi x@`…@”€@e×Ð@`¤ @-1@*°æ@G¸ƒ@GÀ¨@`Ì>@>Ñ-@×ëþ &ö@*,ASg¨@`s @Gž Ø@•À@`crtstuff.c__JCR_LIST__deregister_tm_clones__do_global_dtors_auxcompleted.7594__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entrygenzipops.c__FRAME_END____JCR_END____init_array_end_DYNAMIC__init_array_start__GNU_EH_FRAME_HDR_GLOBAL_OFFSET_TABLE___libc_csu_finigenciorunlink@@GLIBC_2.2.5_ITM_deregisterTMCloneTablegencmovputs@@GLIBC_2.2.5TAILPATHgenzipopgenzip_condopTMPPATH_edatafclose@@GLIBC_2.2.5strlen@@GLIBC_2.2.5__stack_chk_fail@@GLIBC_2.4genzipop_longgencnot__libc_start_main@@GLIBC_2.2.5__data_startstrcmp@@GLIBC_2.2.5gencandfprintf@@GLIBC_2.2.5__gmon_start____dso_handle_IO_stdin_used__libc_csu_initgen_headinggencxorgencadd__bss_startmainusageaccess@@GLIBC_2.2.5fopen@@GLIBC_2.2.5_Jv_RegisterClassesrename@@GLIBC_2.2.5legalsprintf@@GLIBC_2.2.5exit@@GLIBC_2.2.5fwrite@@GLIBC_2.2.5__TMC_END___ITM_registerTMCloneTablegencnegstderr@@GLIBC_2.2.5.symtab.strtab.shstrtab.interp.note.ABI-tag.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.plt.got.text.fini.rodata.eh_frame_hdr.eh_frame.init_array.fini_array.jcr.dynamic.got.plt.data.bss.comment8@8#T@T 1t@t$Döÿÿo˜@˜$N À@À˜VX@X«^ÿÿÿo@"kþÿÿo(@(0zX@X0„Bˆ@ˆPŽØ@؉@ð”ð@ð@ò£ô@ô ©@Á±Ä6@Ä6œ¿`7@`7”É>`>Õ>`>á >` >æ(>`(>Иø?`ø?ï@`@ˆøˆ@`ˆ@ þÀ@`¨@ 0¨@4qM à@è/ ÈI© +\ No newline at end of file diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c --- gcc-6.2.0/gcc/config/zip/genzipops.c 1969-12-31 19:00:00.000000000 -0500 +++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c 2017-03-07 12:03:59.062584503 -0500 @@ -750,8 +977,8 @@ +} diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c --- gcc-6.2.0/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/config/zip/zip.c 2017-03-07 12:03:18.566583672 -0500 -@@ -0,0 +1,2679 @@ ++++ gcc-6.2.0-zip/gcc/config/zip/zip.c 2018-06-05 21:17:24.151098201 -0400 +@@ -0,0 +1,2711 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: zip.c @@ -2502,6 +2729,12 @@ + strcpy(mstr, ":HI"); + else if (GET_MODE(x) == SImode) + strcpy(mstr, ":SI"); ++ else if (GET_MODE(x) == DImode) ++ strcpy(mstr, ":DI"); ++ else if (GET_MODE(x) == SFmode) ++ strcpy(mstr, ":SF"); ++ else if (GET_MODE(x) == DFmode) ++ strcpy(mstr, ":DF"); + else if (GET_MODE(x) == VOIDmode) + strcpy(mstr, ":V"); + else @@ -2509,8 +2742,14 @@ + if (REG_P(XEXP(x,0))) { + int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)), + sb = SUBREG_BYTE(x); -+ if (mod==QImode) -+ sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb); ++ if (mod==SFmode) ++ sprintf(buf,"(SUBREG%s (REG:SF %d)/%d)",mstr,hreg, sb); ++ else if (mod==DFmode) ++ sprintf(buf,"(SUBREG%s (REG:DF %d)/%d)",mstr,hreg, sb); ++ else if (mod==DImode) ++ sprintf(buf,"(SUBREG%s (REG:DI %d)/%d)",mstr,hreg, sb); ++ else if (mod==SImode) ++ sprintf(buf,"(SUBREG%s (REG:SI %d)/%d)",mstr,hreg, sb); + else if (mod==HImode) + sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb); + else if (mod==QImode) @@ -2922,8 +3161,8 @@ + ZIPDEBUGFLAG(dbg, false); + + if (dbg) fprintf(stderr, "\nZIP::MOVDI\n"); -+ if (dbg) zip_debug_rtx_pfx("DST", dst); -+ if (dbg) zip_debug_rtx_pfx("SRC", src); ++ if (dbg) zip_debug_rtx_pfx(" DST", dst); ++ if (dbg) zip_debug_rtx_pfx(" SRC", src); + + // MOV !REG->!REG + if ((!REG_P(dst))&&(!REG_P(src))&&(can_create_pseudo_p())) { @@ -2946,6 +3185,26 @@ + return 1; + } + ++ // MOV SUBREG->REG ++ if ((REG_P(dst))&&(SUBREG_P(src))) { ++ if (dbg) fprintf(stderr, "ZIP::MOVDI -- SUBREG->REG\n"); ++ ++ if (GET_MODE(src)==DImode) { ++ emit_insn(gen_movdi_raw(dst, src)); ++ return 1; ++ } ++ } ++ ++ // MOV REG->SUBREG ++ if ((SUBREG_P(dst))&&(REG_P(src))) { ++ if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->SUBREG\n"); ++ ++ if (GET_MODE(dst)==DImode) { ++ emit_insn(gen_movdi_raw(dst, src)); ++ return 1; ++ } ++ } ++ + // MOV REG->MEM (a store instruction) + if ((MEM_P(dst))&&(REG_P(src))) { + rtx addr = XEXP(dst,0); @@ -3445,8 +3704,8 @@ +#endif diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md --- gcc-6.2.0/gcc/config/zip/zip-di.md 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md 2017-02-22 15:56:17.195319460 -0500 -@@ -0,0 +1,528 @@ ++++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md 2018-06-05 18:57:29.386399718 -0400 +@@ -0,0 +1,548 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Filename: zip-di.md @@ -3464,7 +3723,7 @@ +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; -+;; Copyright (C) 2015, Gisselquist Technology, LLC ++;; Copyright (C) 2015-2018, Gisselquist Technology, LLC +;; +;; This program is free software (firmware): you can redistribute it and/or +;; modify it under the terms of the GNU General Public License as published @@ -3508,9 +3767,29 @@ + return "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0"; + else if (MEM_P(operands[0])) //; StoreDI + return "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0"; -+ else if (MEM_P(operands[1])) //; LoadDI -+ return "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0"; -+ else if (CONST_INT_P(operands[1])) { ++ else if (MEM_P(operands[1])) { //; LoadDI ++ //; Deal with the case of ++ //; LOD (R0),R0 ++ //; LOD 4(R0),R1 ++ //; By reversing the order of the operands, to ++ //; LOD 4(R0),R1 ++ //; LOD (R0),R0 ++ //; This isn't efficient, so let's do whatever we can to ++ //; avoid this, still ... if we do it, we can make it ++ //; work ++ rtx address = XEXP(operands[1],0); ++ int hazard = 0; ++ if ( (REG_P(address)) ++ &&((REGNO(address))==(REGNO(operands[0]))) ) ++ hazard = 1; ++ else if ( (PLUS == (GET_CODE(address))) ++ &&(REGNO(XEXP(address,0))==(REGNO(operands[0]))) ) ++ hazard = 1; ++ if (hazard) ++ return "LW 4+%1,%L0\t; Load:DI\n\tLW %1,%H0"; ++ else ++ return "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0"; ++ } else if (CONST_INT_P(operands[1])) { + char tmp[128]; + HOST_WIDE_INT v = INTVAL(operands[1]); + sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0", @@ -4119,7 +4398,7 @@ +; diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h --- gcc-6.2.0/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/config/zip/zip.h 2017-03-03 09:30:57.671304970 -0500 ++++ gcc-6.2.0-zip/gcc/config/zip/zip.h 2018-06-05 22:22:38.581639662 -0400 @@ -0,0 +1,4114 @@ +//////////////////////////////////////////////////////////////////////////////// +// @@ -4316,8 +4595,8 @@ + * If this macro is not defined, the GCC driver provides a default that passes + * the string '-lgcc' to the linker. + */ -+#undef LIBGCC_SPEC -+#define LIBGCC_SPEC "" ++// #undef LIBGCC_SPEC ++// #define LIBGCC_SPEC "" + +/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the + * LIBGCC_SPEC is not directly used by the driver program but is instead @@ -4390,6 +4669,7 @@ + */ +#define TARGET_CPU_CPP_BUILTINS() \ + { builtin_define("__ZIPCPU__"); \ ++ builtin_define("__BIG_ENDIAN__"); \ + builtin_define("__IEEE_BIG_ENDIAN"); \ + builtin_define("_LDBL_EQ_DBL"); \ + if (ZIP_FPU) builtin_define("__ZIPFPU__"); \ @@ -4442,7 +4722,6 @@ + * achieved. Therefore, we won't support these modes. However, we can't just + * set this to zero, so let's come back to this. + */ -+// #warning "Wrong answer encoded to date" +// #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P +// #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0 + @@ -7160,7 +7439,7 @@ + +/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive + * to specify the size of a symbol, without any arguments. ON systems that -+ * use ELF, the dfault is "\t.size\t"; on other systems, the default is not to ++ * use ELF, the default is "\t.size\t"; on other systems, the default is not to + * define this macro. + * + * Define this amcro only if it is correct to use the default definitions of @@ -7216,7 +7495,7 @@ + * (sans semicolon) to output to the stdio stream STREAM any text necessary for + * claiming a register REGNO for a global variable DECL with name NAME. + * -+ * If you don't defin this macro, that is equivalent to dfining it to do ++ * If you don't defin this macro, that is equivalent to defining it to do + * nothing. + */ + @@ -8237,8 +8516,8 @@ + diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md --- gcc-6.2.0/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2017-03-07 12:02:29.862582673 -0500 -@@ -0,0 +1,1968 @@ ++++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2018-06-07 12:51:05.802342817 -0400 +@@ -0,0 +1,1897 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Filename: zip.md @@ -8254,7 +8533,7 @@ +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; -+;; Copyright (C) 2015-2017, Gisselquist Technology, LLC ++;; Copyright (C) 2015-2018, Gisselquist Technology, LLC +;; +;; This program is free software (firmware): you can redistribute it and/or +;; modify it under the terms of the GNU General Public License as published @@ -8337,10 +8616,10 @@ + (RTNV_REG 1) ; Subroutine return value register + (AP_REG 10) ; Hopefully never used + (GBL_REG 11) ; Hopefully never used, but just in case ... -+ (FP_REG 12) -+ (SP_REG 13) -+ (CC_REG 14) -+ (PC_REG 15) ++ (FP_REG 12) ; Frame pointer register ++ (SP_REG 13) ; Stack pointer register ++ (CC_REG 14) ; Condition codes register ++ (PC_REG 15) ; Program counter + ]) +; +; @@ -8420,42 +8699,8 @@ +}) + +; -+; zip_movdst_operand_p and zip_movsrc_operand_p are no longer necessary, and -+; are being deprecated. +; -+;(define_predicate "zip_movdst_operand_p" -+; (match_code "mem,reg,subreg") -+;{ -+; if (MEM_P(op)) // Check for valid store address -+; return zip_pd_opb_operand(XEXP(op,0)); -+; else if ((SUBREG_P(op))&&(REG_P(XEXP(op,0)))) -+; return 1; -+; else if (REG_P(op)) -+; return register_operand(op, GET_MODE(op)); -+; return 1; -+;}) -+ -+;(define_predicate "zip_movsrc_operand_p" -+; (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label") -+;{ -+; if (MEM_P(op)) -+; return zip_pd_opb_operand(XEXP(op,0)); -+; else if (GET_CODE(op)==PLUS) -+; return zip_pd_opb_operand(op); -+; else if ((SUBREG_P(op))&&(REG_P(XEXP(op,0)))) { -+; //; As far as predicates are concerned, subregs must be valid. -+; //; The details of them are settled within the constraints. -+; return 1; -+; } else if ((REG_P(op))||(SUBREG_P(op))) -+; return register_operand(op,SImode); -+; else if (CONST_INT_P(op)) -+; return 1; -+; return 1; -+;}) -+ +; -+; -+; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Constraints @@ -8631,26 +8876,6 @@ +; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; -+;; Load and store multiple values -+;; -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; -+; So far, from the code I've seen from GCC's output, -+; these instructions do not appear to be necessary. -+; -+;(define_insn "load_multiple" -+; for(a=0; a<%2; a++) -+; LW a(%1),%0+a -+;(define_insn "store_multiple" -+; for(a=0; a<%2; a++) -+; SW %0+a,a(%1) -+; pushsi -- Do not define, compiler will work around it nicely w/o our help -+; -+; -+; -+; -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; +;; Substitution Pattern +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -8840,14 +9065,10 @@ +;; +; +; -+; ASR -+; LSL -+; LSR +; +; +; +; -+; +; Others: NEG, TEST, POPC, NOT +; +; @@ -8883,18 +9104,6 @@ +; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; -+;; Conditional arithmetic instructions -+;; -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+; -+; -+; -+; -+; -+; -+; -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;; +;; Comparison instructions, both compare and test +;; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; @@ -9073,10 +9282,10 @@ + (if_then_else:SI (match_operand 1 "comparison_operator") + (xor:SI (match_operand:SI 2 "register_operand" "0") + (const_int -1)) -+ (match_dup 2)))] ++ (match_operand:SI 3 "register_operand" "0")))] + "" + { -+ extern void zip_debug_rtx_pfx(const char *, const_rtx); ++ //; extern void zip_debug_rtx_pfx(const char *, const_rtx); + //; fprintf(stderr, "NOTSICC\n"); + //; zip_debug_rtx_pfx("- DST: ", operands[0]); + //; zip_debug_rtx_pfx("- CMP: ", operands[1]); @@ -9083,10 +9292,6 @@ + //; zip_debug_rtx_pfx("- NOT: ", operands[2]); + //; zip_debug_rtx_pfx("- OLD: ", operands[3]); + -+ if (!REG_P(operands[2])) -+ operands[2] = force_reg(SImode, operands[2]); -+ if (REGNO(operands[0]) != REGNO(operands[2])) -+ emit_insn(gen_movsi(operands[0], operands[2])); + + rtx_code ccode = GET_CODE(operands[1]); + rtx cmpop0 = copy_rtx(XEXP(operands[1], 0)); @@ -10138,6 +10343,7 @@ + "BREAK" + [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")]) +; ++; +(define_expand "ctrapsi4" + [(set (reg:CC CC_REG) (compare:CC + (match_operand:SI 1 "register_operand" "r") @@ -10147,6 +10353,8 @@ + (match_operand 3 "const_int_operand" "O"))] + "" + ) ++; ++; +(define_insn "trapif" + [(trap_if (match_operator 0 "ordered_comparison_operator" + [(reg:CC CC_REG) (const_int 0)]) @@ -10207,11 +10415,2754 @@ +; cmove ... the conditional move, created from a +; (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X)))) +; pattern -diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-modes.def gcc-6.2.0-zip/gcc/config/zip/zip-modes.def ---- gcc-6.2.0/gcc/config/zip/zip-modes.def 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/config/zip/zip-modes.def 2017-01-10 12:46:54.791966242 -0500 -@@ -0,0 +1 @@ -+#define BITS_PER_UNIT 8 +diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-ops.md gcc-6.2.0-zip/gcc/config/zip/zip-ops.md +--- gcc-6.2.0/gcc/config/zip/zip-ops.md 1969-12-31 19:00:00.000000000 -0500 ++++ gcc-6.2.0-zip/gcc/config/zip/zip-ops.md 2018-03-22 18:33:11.175718614 -0400 +@@ -0,0 +1,2744 @@ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ++;; Filename: zip-ops.md ++;; ++;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core ++;; ++;; Purpose: This is a computer generated machine description of the ++;; ZipCPU's operations. It is computer generated simply for ++;; two reasons. First, I can't seem to find a way to generate this ++;; information within GCC's current constructs. Specifically, the ++;; CPU's instructions normally set the condition codes, unless they ++;; are conditional instructions when they don't. Second, the ZipCPU is ++;; actually quite regular. Almost all of the instructions have the same ++;; form. This form turns into many, many RTL instructions. Because the ++;; CPU doesn't match any of the others within GCC, that means either ++;; I have a *lot* of cut, copy, paste, and edit to do to create the file ++;; and upon any and every edit, or I need to build a program to generate ++;; the remaining .md constructs. Hence, I chose the latter to minimize ++;; the amount of work I needed to do. ++;; ++;; ++;; Creator: Dan Gisselquist, Ph.D. ++;; Gisselquist Technology, LLC ++;; ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ++;; Copyright (C) 2017, Gisselquist Technology, LLC ++;; ++;; This program is free software (firmware): you can redistribute it and/or ++;; modify it under the terms of the GNU General Public License as published ++;; by the Free Software Foundation, either version 3 of the License, or (at ++;; your option) any later version. ++;; ++;; This program is distributed in the hope that it will be useful, but WITHOUT ++;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or ++;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++;; for more details. ++;; ++;; License: GPL, v3, as defined and found on www.gnu.org, ++;; http://www.gnu.org/licenses/gpl.html ++;; ++;; ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;; ++;; ++; ++; ++; ++; ADD (genzipop_long) ++; ++; ++; ++(define_insn "addsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "ADD\t%2,%0 ; addsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "addsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "ADD\t%1,%0 ; addsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "addsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ADD.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ADD.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ADD.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ADD.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ADD.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ADD.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; ADD (genzipop_long) ++; ++; ++; ++(define_insn "addsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "ADD\t%2,%0 ; addsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "addsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "ADD\t%1,%0 ; addsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "addsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ADD.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ADD.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ADD.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ADD.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ADD.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "addsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (plus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ADD.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; SUB (genzipop_long) ++; ++; ++; ++(define_insn "subsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "SUB\t%2,%0 ; subsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "subsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "SUB\t%1,%0 ; subsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "subsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "SUB.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "SUB.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "SUB.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "SUB.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "SUB.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "SUB.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; SUB (genzipop_long) ++; ++; ++; ++(define_insn "subsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "SUB\t%2,%0 ; subsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "subsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "SUB\t%1,%0 ; subsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "subsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "SUB.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "SUB.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "SUB.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "SUB.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "SUB.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "subsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (minus:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "SUB.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; MPY (genzipop_long) ++; ++; ++; ++(define_insn "mulsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "MPY\t%2,%0 ; mulsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "mulsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "MPY\t%1,%0 ; mulsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "mulsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "MPY.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "MPY.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "MPY.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "MPY.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "MPY.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "MPY.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; MPY (genzipop_long) ++; ++; ++; ++(define_insn "mulsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "MPY\t%2,%0 ; mulsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "mulsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "MPY\t%1,%0 ; mulsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "mulsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "MPY.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "MPY.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "MPY.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "MPY.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "MPY.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "mulsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (mult:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "MPY.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; DIVS (genzipop_long) ++; ++; ++; ++(define_insn "divsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "(ZIP_DIVIDE)" ++ "DIVS\t%2,%0 ; divsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "divsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "(ZIP_DIVIDE)" ++ "DIVS\t%1,%0 ; divsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "divsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; DIVS (genzipop_long) ++; ++; ++; ++(define_insn "divsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "(ZIP_DIVIDE)" ++ "DIVS\t%2,%0 ; divsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "divsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "(ZIP_DIVIDE)" ++ "DIVS\t%1,%0 ; divsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "divsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "divsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (div:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVS.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; DIVU (genzipop_long) ++; ++; ++; ++(define_insn "udivsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "(ZIP_DIVIDE)" ++ "DIVU\t%2,%0 ; udivsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "udivsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "(ZIP_DIVIDE)" ++ "DIVU\t%1,%0 ; udivsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "udivsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; DIVU (genzipop_long) ++; ++; ++; ++(define_insn "udivsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "(ZIP_DIVIDE)" ++ "DIVU\t%2,%0 ; udivsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "udivsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "(ZIP_DIVIDE)" ++ "DIVU\t%1,%0 ; udivsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "udivsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "udivsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (udiv:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "(ZIP_DIVIDE)" ; Condition ++ "DIVU.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; AND (genzipop_long) ++; ++; ++; ++(define_insn "andsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "AND\t%2,%0 ; andsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "andsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "AND\t%1,%0 ; andsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "andsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "AND.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "AND.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "AND.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "AND.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "AND.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "AND.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; AND (genzipop_long) ++; ++; ++; ++(define_insn "andsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "AND\t%2,%0 ; andsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "andsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "AND\t%1,%0 ; andsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "andsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "AND.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "AND.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "AND.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "AND.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "AND.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "andsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (and:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "AND.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; OR (genzipop_long) ++; ++; ++; ++(define_insn "iorsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "OR\t%2,%0 ; iorsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "iorsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "OR\t%1,%0 ; iorsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "iorsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "OR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "OR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "OR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "OR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "OR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "OR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; OR (genzipop_long) ++; ++; ++; ++(define_insn "iorsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "OR\t%2,%0 ; iorsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "iorsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "OR\t%1,%0 ; iorsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "iorsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "OR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "OR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "OR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "OR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "OR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "iorsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ior:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "OR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; XOR (genzipop_long) ++; ++; ++; ++(define_insn "xorsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "XOR\t%2,%0 ; xorsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "xorsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "XOR\t%1,%0 ; xorsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "xorsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "XOR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "XOR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "XOR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "XOR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "XOR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "XOR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; XOR (genzipop_long) ++; ++; ++; ++(define_insn "xorsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "XOR\t%2,%0 ; xorsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "xorsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "XOR\t%1,%0 ; xorsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "xorsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "XOR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "XOR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "XOR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "XOR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "XOR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "xorsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (xor:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "XOR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; ASR (genzipop_long) ++; ++; ++; ++(define_insn "ashrsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "ASR\t%2,%0 ; ashrsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashrsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "ASR\t%1,%0 ; ashrsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashrsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ASR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ASR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ASR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ASR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ASR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "ASR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; ASR (genzipop_long) ++; ++; ++; ++(define_insn "ashrsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "ASR\t%2,%0 ; ashrsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashrsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "ASR\t%1,%0 ; ashrsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashrsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ASR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ASR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ASR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ASR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ASR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashrsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "ASR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; LSL (genzipop_long) ++; ++; ++; ++(define_insn "ashlsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "LSL\t%2,%0 ; ashlsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashlsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "LSL\t%1,%0 ; ashlsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashlsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSL.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSL.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSL.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSL.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSL.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSL.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; LSL (genzipop_long) ++; ++; ++; ++(define_insn "ashlsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "LSL\t%2,%0 ; ashlsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashlsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "LSL\t%1,%0 ; ashlsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "ashlsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSL.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSL.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSL.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSL.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSL.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "ashlsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (ashift:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSL.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; LSR (genzipop_long) ++; ++; ++; ++(define_insn "lshrsi3" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") ++ (match_operand:SI 2 "zip_opb_single_operand_p" "rO"))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "LSR\t%2,%0 ; lshrsi3" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "lshrsi3_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "LSR\t%1,%0 ; lshrsi3_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "lshrsi3_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))] ++ "" ; Condition ++ "LSR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; LSR (genzipop_long) ++; ++; ++; ++(define_insn "lshrsi3_off" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") ++ (plus:SI (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "const_int_operand" "N")))) ++ (clobber (reg:CC CC_REG))] ++ "" ++ "LSR\t%2,%0 ; lshrsi3_off" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "lshrsi3_off_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "" ++ "LSR\t%1,%0 ; lshrsi3_off_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "lshrsi3_off_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSR.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_off_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSR.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_off_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSR.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_off_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSR.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_off_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSR.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "lshrsi3_off_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (lshiftrt:SI (match_dup 0) ++ (plus:SI (match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "const_int_operand" "N")))))] ++ "" ; Condition ++ "LSR.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; MPYSHI (genzipop_long) ++; ++; ++; ++(define_insn "smulsi_highpart" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_operand:SI 1 "register_operand" "0")) ++ (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))) ++ (clobber (reg:CC CC_REG))] ++ "(ZIP_HAS_DI)" ++ "MPYSHI\t%2,%0 ; smulsi_highpart" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "smulsi_highpart_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "(ZIP_HAS_DI)" ++ "MPYSHI\t%1,%0 ; smulsi_highpart_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "smulsi_highpart_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYSHI.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "smulsi_highpart_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYSHI.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "smulsi_highpart_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYSHI.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "smulsi_highpart_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYSHI.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "smulsi_highpart_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYSHI.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "smulsi_highpart_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (sign_extend:DI (match_dup 0)) ++ (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYSHI.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; ++; MPYUHI (genzipop_long) ++; ++; ++; ++(define_insn "umulsi_highpart" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_operand:SI 1 "register_operand" "0")) ++ (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))) ++ (clobber (reg:CC CC_REG))] ++ "(ZIP_HAS_DI)" ++ "MPYUHI\t%2,%0 ; umulsi_highpart" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "umulsi_highpart_raw" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))) ++ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))] ++ "(ZIP_HAS_DI)" ++ "MPYUHI\t%1,%0 ; umulsi_highpart_raw" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "set")]) ++; ++; ++(define_insn "umulsi_highpart_eq" ++ [(cond_exec (eq (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYUHI.Z\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "umulsi_highpart_ne" ++ [(cond_exec (ne (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYUHI.NZ\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "umulsi_highpart_lt" ++ [(cond_exec (lt (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYUHI.LT\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "umulsi_highpart_ge" ++ [(cond_exec (ge (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYUHI.GE\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "umulsi_highpart_ltu" ++ [(cond_exec (ltu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYUHI.C\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "umulsi_highpart_geu" ++ [(cond_exec (geu (reg:CC CC_REG) (const_int 0)) ++ (set (match_operand:SI 0 "register_operand" "=r") ++ (truncate:SI (ashiftrt:DI (mult:DI ++ (zero_extend:DI (match_dup 0)) ++ (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO"))) ++ (const_int 32)))))] ++ "(ZIP_HAS_DI)" ; Condition ++ "MPYUHI.NC\t%1,%0 ; genzip, conditional operator" ; Template ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; ++; ++; Conditional move instructions ++; ++; ++; ++; ++(define_insn "cmov_eq" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.Z %1,%0 ; cmov ++ LW.Z %1,%0 ; cmov ++ LDI.Z %1,%0 ; cmov ++ SW.Z %1,%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cmov_ne" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.NZ %1,%0 ; cmov ++ LW.NZ %1,%0 ; cmov ++ LDI.NZ %1,%0 ; cmov ++ SW.NZ %1,%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cmov_lt" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.LT %1,%0 ; cmov ++ LW.LT %1,%0 ; cmov ++ LDI.LT %1,%0 ; cmov ++ SW.LT %1,%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cmov_ge" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.GE %1,%0 ; cmov ++ LW.GE %1,%0 ; cmov ++ LDI.GE %1,%0 ; cmov ++ SW.GE %1,%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cmov_ltu" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.C %1,%0 ; cmov ++ LW.C %1,%0 ; cmov ++ LDI.C %1,%0 ; cmov ++ SW.C %1,%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cmov_geu" ++ [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (match_operand:SI 1 "general_operand" "r,Q,i,r") ++ (match_dup 0)))] ++ "" ++ "@ ++ MOV.NC %1,%0 ; cmov ++ LW.NC %1,%0 ; cmov ++ LDI.NC %1,%0 ; cmov ++ SW.NC %1,%0 ; cmov" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; Conditional add instructions ++; ++; ++; ++; ++(define_insn "cadd_eq" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.Z %1,%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cadd_ne" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.NZ %1,%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cadd_lt" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.LT %1,%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cadd_ge" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.GE %1,%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cadd_ltu" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.C %1,%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cadd_geu" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (plus:SI (match_dup 0) ++ (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "ADD.NC %1,%0 ; cadd" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; Conditional negate instructions ++; ++; ++; ++; ++(define_insn "cneg_eq" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.Z %0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cneg_ne" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.NZ %0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cneg_lt" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.LT %0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cneg_ge" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.GE %0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cneg_ltu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.C %0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cneg_geu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (neg:SI (match_dup 0)) ++ (match_dup 0)))] ++ "" ++ "NEG.NC %0 ; cneg" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; Conditional not instructions ++; ++; ++; ++; ++(define_insn "cnot_eq" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.Z %0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cnot_ne" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.NZ %0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cnot_lt" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.LT %0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cnot_ge" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.GE %0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cnot_ltu" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.C %0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cnot_geu" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) ++ (const_int -1)) ++ (match_dup 0)))] ++ "" ++ "NOT.NC %0 ; cnot" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; Conditional and instructions ++; ++; ++; ++; ++(define_insn "cand_eq" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.Z %1,%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cand_ne" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.NZ %1,%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cand_lt" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.LT %1,%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cand_ge" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.GE %1,%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cand_ltu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.C %1,%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cand_geu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "AND.NC %1,%0 ; cand" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; Conditional ior instructions ++; ++; ++; ++; ++(define_insn "cior_eq" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.Z %1,%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cior_ne" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.NZ %1,%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cior_lt" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.LT %1,%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cior_ge" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.GE %1,%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cior_ltu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.C %1,%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cior_geu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "OR.NC %1,%0 ; cior" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++; Conditional xor instructions ++; ++; ++; ++; ++(define_insn "cxor_eq" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.Z %1,%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cxor_ne" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.NZ %1,%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cxor_lt" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.LT %1,%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cxor_ge" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.GE %1,%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cxor_ltu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.C %1,%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) ++; ++; ++(define_insn "cxor_geu" ++ [(set (match_operand:SI 0 "register_operand" "+r") ++ (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0)) ++ (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO")) ++ (match_dup 0)))] ++ "" ++ "XOR.NC %1,%0 ; cxor" ++ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")]) diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-peephole.md gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md --- gcc-6.2.0/gcc/config/zip/zip-peephole.md 1969-12-31 19:00:00.000000000 -0500 +++ gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md 2017-03-01 15:46:02.440221158 -0500 @@ -11517,7 +14468,7 @@ exit 1 diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cse.c gcc-6.2.0-zip/gcc/cse.c --- gcc-6.2.0/gcc/cse.c 2016-02-04 04:56:13.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/cse.c 2017-02-06 21:46:10.525049918 -0500 ++++ gcc-6.2.0-zip/gcc/cse.c 2018-06-05 21:17:32.963050314 -0400 @@ -42,6 +42,16 @@ #include "dbgcnt.h" #include "rtl-iter.h" @@ -11819,7 +14770,7 @@ delta = simplify_gen_binary (MINUS, mode, tmp1, delta); diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/optabs.c gcc-6.2.0-zip/gcc/optabs.c --- gcc-6.2.0/gcc/optabs.c 2016-02-16 10:15:40.000000000 -0500 -+++ gcc-6.2.0-zip/gcc/optabs.c 2017-03-01 15:46:15.660221429 -0500 ++++ gcc-6.2.0-zip/gcc/optabs.c 2018-03-23 07:13:51.664427524 -0400 @@ -43,6 +43,17 @@ #include "optabs-tree.h" #include "libfuncs.h" @@ -11845,7 +14796,7 @@ +#ifdef DO_ZIP_DEBUGS +fprintf(stderr, "ICODE = %d\n", icode); +fprintf(stderr, "NOPS = %d\n", nops); -+for(int i=0; i>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER; cmpnop &= mask; } +diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/ubsan.c gcc-6.2.0-zip/gcc/ubsan.c +--- gcc-6.2.0/gcc/ubsan.c 2016-08-12 15:57:35.000000000 -0400 ++++ gcc-6.2.0-zip/gcc/ubsan.c 2017-08-23 09:29:11.196719450 -0400 +@@ -1469,7 +1469,7 @@ + + expanded_location xloc = expand_location (loc); + if (xloc.file == NULL || strncmp (xloc.file, "\1", 2) == 0 +- || xloc.file == '\0' || xloc.file[0] == '\xff' ++ || xloc.file[0] == '\0' || xloc.file[0] == '\xff' + || xloc.file[1] == '\xff') + return false; + diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/varasm.c gcc-6.2.0-zip/gcc/varasm.c --- gcc-6.2.0/gcc/varasm.c 2016-03-31 11:30:33.000000000 -0400 +++ gcc-6.2.0-zip/gcc/varasm.c 2016-12-31 17:03:08.629193673 -0500 @@ -12038,8 +15001,8 @@ elt = GEN_INT (data[i]); diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config/zip/sfp-machine.h gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h --- gcc-6.2.0/libgcc/config/zip/sfp-machine.h 1969-12-31 19:00:00.000000000 -0500 -+++ gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h 2017-01-27 12:27:05.094921759 -0500 -@@ -0,0 +1,53 @@ ++++ gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h 2018-03-23 07:16:33.779338866 -0400 +@@ -0,0 +1,55 @@ +#ifndef ZIP_SFP_MACHINE_H +#define ZIP_SFP_MACHINE_H + @@ -12046,6 +15009,8 @@ +#define __BIG_ENDIAN 4321 +#define __BYTE_ORDER __BIG_ENDIAN + ++#include "fp-bit.h" ++ +#define _FP_W_TYPE_SIZE 32 +#define _FP_W_TYPE unsigned int +#define _FP_WS_TYPE signed int @@ -12095,7 +15060,7 @@ +#endif diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config.host gcc-6.2.0-zip/libgcc/config.host --- gcc-6.2.0/libgcc/config.host 2016-05-17 02:15:52.000000000 -0400 -+++ gcc-6.2.0-zip/libgcc/config.host 2017-01-27 12:28:31.470410459 -0500 ++++ gcc-6.2.0-zip/libgcc/config.host 2018-03-23 07:31:08.573591955 -0400 @@ -197,6 +197,9 @@ tic6x-*-*) cpu_type=c6x @@ -12111,7 +15076,7 @@ extra_parts="crt0.o" ;; +zip*) -+ tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp" ++ tmake_file="$tmake_file t-softfp-sfdf t-softfp t-fdpbit" + # extra_parts="crt0.o" + ;; *)
/nlib-script.sh
1,12 → 1,57
#!/bin/bash
 
################################################################################
##
## Filename: nlib-script.sh
##
## Project: Zip CPU -- a small, lightweight, RISC CPU soft core
##
## Purpose: To handle all of the newlib configuration options properly.
## This runs the newlib C-library configure script, using options
## that are currently known to work.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
VERSION="newlib-2.5.0"
INSTALL_BASE=`pwd`/install
if [[ -z "$INSTALLD" ]]
then
INSTALLD=`pwd`/install
fi
INSTALL_BASE=${INSTALLD}
if [[ ! -d $INSTALL_BASE ]]
then
echo "I cant seem to find the install directory," $INSTALL_BASE
exit;
exit -1
fi
which zip-gcc > /dev/null
if [[ $? != 0 ]]
then
echo "Nlib-script Error: Unable to find zip-gcc in your path"
echo "PATH=$PATH"
exit -1
fi
 
if [[ -d build-nlib ]]
then
26,5 → 71,4
GCC_BASE=${INSTALL_BASE}/../build-gcc/
PATH=$PATH:${INSTALL_BASE}/cross-tools/bin:${GCC_BASE}/gcc
../$VERSION-zip/configure --prefix=${INSTALL_BASE}/cross-tools \
--target=${CLFS_TARGET} --host=$MACHTYPE --without-fp
 
--target=${CLFS_TARGET} --host=$MACHTYPE
/nlib-zippatch.patch
6174,7 → 6174,7
#undef _FVWRITE_IN_STREAMIO
diff -Naur '--exclude=*.swp' newlib-2.5.0/newlib/configure.host newlib-2.5.0-zip/newlib/configure.host
--- newlib-2.5.0/newlib/configure.host 2016-12-22 21:33:54.000000000 -0500
+++ newlib-2.5.0-zip/newlib/configure.host 2017-01-25 10:26:38.562136630 -0500
+++ newlib-2.5.0-zip/newlib/configure.host 2018-03-22 19:19:26.894978411 -0400
@@ -310,6 +310,9 @@
z8k)
machine_dir=z8k
6185,7 → 6185,7
spu)
stdio_dir=
libm_machine_dir=spu
@@ -565,6 +568,12 @@
@@ -565,6 +568,11 @@
z8k-*-coff)
sys_dir=z8ksim
;;
6192,13 → 6192,12
+ zip*)
+# sys_dir=zip # But ... I don't have a directory in newlib/libc/sys
+ newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED "
+ newlib_cflags="${newlib_cflags} -DNO_FLOATING_POINT"
+# have_crt0="yes"
+ ;;
esac
# Host specific flag settings -- usually for features that are not
@@ -851,6 +860,9 @@
@@ -851,6 +859,9 @@
z8k-*-*)
syscall_dir=syscalls
;;
/zasm/.gitignore
3,3 → 3,5
zasm
tags
obj-pc/*
optest.cpp
sys.i
zasm Property changes : Modified: svn:ignore ## -3,3 +3,4 ## zasm zdump zpp +obj-pc Index: . =================================================================== --- . (revision 206) +++ . (revision 209)
. Property changes : Modified: svn:ignore ## -1,8 +1,12 ## binutils-2.25 +binutils-2.27 +binutils-2.27-zip build-gas build-gcc +build-nlib gcc-5.3.0-zip gcc-6.2.0-zip +newlib-2.5.0-zip install lib tmp ## -10,3 +14,4 ## zipdbg zipos zlibc +genzipops

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.