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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk/sw
    from Rev 55 to Rev 59
    Reverse comparison

Rev 55 → Rev 59

/lib/mpy32u.S
1,7 → 1,41
mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1
PUSH R2
PUSH R3
PUSH R4
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename: mpyu.S
;
; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose: Zip assembly file for running doing an unsigned 32x32 bit
; multiply..
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; License: GPL, v3, as defined and found on www.gnu.org,
; http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
;
mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1, R2 = rtn addr (on stack)
SUB 2,SP
STO R3,1(SP)
STO R4,2(SP)
MOV R0,R2
MULU R1,R2 ; R2 = Low order bits, low(R0) * low(R1)
MOV R0,R3
21,7 → 55,9
ADD R4,R2 ; R2 = low order bits plus low order mid-bits
ADD.C 1,R0 ; Add in the carry to R0 (if it happened)
MOV R2,R1 ; Place low order bits into R1
POP R4
POP R3
POP R2
RET
;
LOD 1(SP),R3
LOD 2(SP),R4
LOD 3(SP),R2
ADD 2,SP
JMP R2
/lib/divs.S
39,6 → 39,7
NEG.NE R1 ; Then negate R1
ret_div32s:
LOD 2(SP),R3
LOD 3(SP),R2
ADD 2,SP
RETN
JMP R2
 
/lib/divu.S
1,7 → 1,37
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename: divu.S
;
; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose: Zip assembly file for running doing an unsigned divide.
; This routine is also called by the signed divide.
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; License: GPL, v3, as defined and found on www.gnu.org,
; http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
;
divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
TST -1,R1
; BNZ divu_valid_divide
93,6 → 123,7
MOV R0,R1
MOV R3,R0
LOD 1(SP),R3
LOD 2(SP),R2
ADD 1,SP
RETN
JMP R2
 
/lib/mpy32s.S
1,16 → 1,62
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename: mpy32s.S
;
; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose: Zip assembly file for running a 32-bit by 32-bit signed
; multiply. It works by adjusting the sign of the 32x32-bit
; unsigned multiply.
;
; Creator: Dan Gisselquist, Ph.D.
; Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; License: GPL, v3, as defined and found on www.gnu.org,
; http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
;
; We could build mul32s (32-bit signed multiply) as
;
; R0 - incoming value to be multiplied
; R1 - Second multiplicand
; R2 - Comes in as scratch
; R3 - used as scratch internally
mpy32s:
PUSH R2
CLR R2 ; Keep track of resulting sign in R2
ADD 2,SP
STO R3,2(SP)
;
CLR R3 ; Keep track of resulting sign in R2
TST R0 ; Is R0 negative?
XOR.LT #1,R2 ; If so, resulting sign will be negative, and
XOR.LT #1,R3 ; If so, resulting sign will be negative, and
NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0))
TST R1 ; Is R1 negative?
XOR.LT #1,R2 ; If so, result will be opposite sign of before
TST R1 ; Need to retest since xor modified flags
XOR.LT #1,R3 ; If so, result will be opposite sign of before
NEG.LT R1 ; Now we get R1=ABS(R1)
JSR mpy32u ; Do our unsigned multiply
CMP R2 ; Check resulting sign
 
; JSR mpy32u
MOV __HERE__+2,R2 ; Do our unsigned multiply
STO R2,1(SP)
BRA mpy32u
;
TST 0,R3 ; Check resulting sign
BZ ret_mul32s ; If positive, do nothing more
NOT R0 ; If negative, negate the result
NOT R1
17,6 → 63,8
ADD $1,R1
ADD.C $1,R0
ret_mul32s:
POP R2
RET
LOD 2(SP),R3
LOD 3(SP),R2
ADD 2,SP
JMP R2
 

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