OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk
    from Rev 10 to Rev 11
    Reverse comparison

Rev 10 → Rev 11

/bench/asm/wdt.S
41,7 → 41,7
MOV $1+PC,R11 ; Get a memory address for a variable
BRA $1
.DAT 0
LDI $800h,R0 ; Start the watchdog timer
LDI $-1,R0 ; Start the watchdog timer
STO R0,$1(R12)
LSR $1,R0
STO R0,$4(R12)
/bench/asm/lfsr.S
0,0 → 1,11
loop:
LDI $2408bh,R10
LDI $1,R9
loop:
MOV R9,R0
LSR $1,R9
TST $1,R0
XOR.NE R10,R9
BRA $-5
 
HALT
/bench/cpp/zippy_tb.cpp
525,9 → 525,14
m_core->o_qspi_dat);
*/
 
int stb = m_core->o_wb_stb;
if ((m_core->o_wb_addr & (-1<<20))!=1)
stb = 0;
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data,
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb))
m_core->i_wb_ack = 1;
 
if ((dbg_flag)&&(dbg_fp)) {
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n",
/rtl/core/pipefetch.v
164,7 → 164,9
end
 
always @(posedge i_clk)
if ((~o_wb_cyc)&&(
if (i_rst) // Required, so we can reload memoy and then reset
r_nvalid <= 0;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
r_nvalid <= 0;
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
/rtl/zipsystem.v
206,7 → 206,7
initial cmd_halt = 1'b1;
always @(posedge i_clk)
if (i_rst)
cmd_halt <= 1'b0;
cmd_halt <= 1'b1;
else if (dbg_cmd_write)
cmd_halt <= dbg_idata[10];
else if ((cmd_step)||(cpu_break))

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