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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk
    from Rev 104 to Rev 105
    Reverse comparison

Rev 104 → Rev 105

/bench/cpp/zippy_tb.cpp
348,7 → 348,12
 
#ifdef OPT_EARLY_BRANCHING
printw(" %s",
(m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)?"EB":" ");
(m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":" ");
if (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
printw(" 0x%08x", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc);
else printw(" %10s", "");
printw(" %s",
(m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":" ");
#endif
/*
784,9 → 789,9
printf("dcd_stalled = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
#endif
printf("pf_valid = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
#ifdef OPT_EARLY_BRANCHING
// #ifdef OPT_EARLY_BRANCHING
// printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
#endif
// #endif
 
exit(-2);
}
1187,8 → 1192,8
fprintf(dbg_fp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
(m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
m_core->v__DOT__thecpu__DOT__pf_pc,
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_branch_pc,
((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch)
m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc,
((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
&&(dcdvalid())
&&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
/rtl/core/idecode.v
55,7 → 55,7
o_cond, o_wF,
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
o_wR, o_rA, o_rB,
o_early_branch, o_branch_pc,
o_early_branch, o_branch_pc, o_ljmp,
o_pipe
);
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
79,6 → 79,7
output reg o_wR, o_rA, o_rB;
output wire o_early_branch;
output wire [(AW-1):0] o_branch_pc;
output wire o_ljmp;
output reg o_pipe;
 
wire dcdA_stall, dcdB_stall, dcdF_stall;
96,8 → 97,16
wire [3:0] w_cond;
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
wire w_wR, w_rA, w_rB, w_wR_n;
wire w_ljmp;
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
wire [31:0] iword;
`ifdef OPT_VLIW
reg [16:0] r_nxt_half;
127,7 → 136,7
// 0 LUTs
assign w_dcdA = w_dcdR;
// 2 LUTs, 1 delay each
// assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
// 0 LUTs
assign w_dcdA_pc = w_dcdR_pc;
330,37 → 339,54
`endif
end
 
 
generate
if (EARLY_BRANCHING!=0)
begin
reg r_early_branch;
reg r_early_branch, r_ljmp;
reg [(AW-1):0] r_branch_pc;
 
initial r_ljmp = 1'b0;
always @(posedge i_clk)
if (i_ce)
if (i_rst)
r_ljmp <= 1'b0;
else if ((i_ce)&&(i_pf_valid))
r_ljmp <= (w_ljmp);
assign o_ljmp = r_ljmp;
 
always @(posedge i_clk)
if (i_rst)
r_early_branch <= 1'b0;
else if ((i_ce)&&(i_pf_valid))
begin
if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
if (r_ljmp)
// LOD (PC),PC
r_early_branch <= 1'b1;
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
begin
if (w_op[4:1] == 4'hb) // LDI to PC
begin // LDI x,PC
// LDI x,PC
r_early_branch <= 1'b1;
end else if ((w_op[4:0]==5'h02)&&(~iword[18]))
begin // Add x,PC
else if ((w_op[4:0]==5'h02)&&(~iword[18]))
// Add x,PC
r_early_branch <= 1'b1;
end else begin
else begin
r_early_branch <= 1'b0;
end
end else
r_early_branch <= 1'b0;
end
end else if (i_ce)
r_early_branch <= 1'b0;
 
always @(posedge i_clk)
if (i_ce)
begin
if (w_op[4:1] == 4'hb) // LDI
if (r_ljmp)
r_branch_pc <= iword[(AW-1):0];
else if (w_op[4:1] == 4'hb) // LDI
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
else // Add x,PC
r_branch_pc <= i_pc
+ {{(AW-18){iword[17]}},iword[16:0]}
+ {{(AW-17){iword[17]}},iword[16:0]}
+ {{(AW-1){1'b0}},1'b1};
end
 
369,6 → 395,7
end else begin
assign o_early_branch = 1'b0;
assign o_branch_pc = {(AW){1'b0}};
assign o_ljmp = 1'b0;
end endgenerate
 
 
396,6 → 423,8
always @(posedge i_clk)
if (i_rst)
r_valid <= 1'b0;
else if ((i_ce)&&(o_ljmp))
r_valid <= 1'b0;
else if ((i_ce)&&(i_pf_valid))
r_valid <= 1'b1;
else if (~i_stalled)
/rtl/core/idecode_deprecated.v
101,7 → 101,7
assign o_branch_pc = r_branch_pc;
 
always @(posedge i_clk)
if ((i_ce)&&(i_instruction[27:24]==`CPU_PC_REG))
if ((i_ce)&&(i_pf_valid)&&(i_instruction[27:24]==`CPU_PC_REG))
begin
r_early_branch <= 1'b0;
// First case, a move to PC instruction
/rtl/core/zipcpu.v
252,7 → 252,7
wire dcdR_wr, dcdA_rd, dcdB_rd,
dcdALU, dcdM, dcdDV, dcdFP,
dcdF_wr, dcd_gie, dcd_break, dcd_lock,
dcd_pipe;
dcd_pipe, dcd_ljmp;
reg r_dcdvalid;
wire dcdvalid;
wire [(AW-1):0] dcd_pc;
523,8 → 523,8
if (i_rst)
r_dcdvalid <= 1'b0;
else if (dcd_ce)
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
else if ((op_ce)||(clear_pipeline))
r_dcdvalid <= (pf_valid);
else if (op_ce)
r_dcdvalid <= 1'b0;
assign dcdvalid = r_dcdvalid;
 
532,11 → 532,11
 
`ifdef OPT_TRADITIONAL_PFCACHE
pfcache #(LGICACHE, ADDRESS_WIDTH)
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
i_clear_pf_cache,
// dcd_pc,
~dcd_stalled,
((dcd_early_branch)&&(dcdvalid)&&(~new_pc))
((dcd_early_branch)&&(~clear_pipeline))
? dcd_branch_pc:pf_pc,
instruction, instruction_pc, pf_valid,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
544,7 → 544,7
pf_illegal);
`else
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(dcdvalid)),
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
i_clear_pf_cache, ~dcd_stalled,
(new_pc)?pf_pc:dcd_branch_pc,
instruction, instruction_pc, pf_valid,
565,7 → 565,7
if ((i_rst)||(clear_pipeline))
r_dcdvalid <= 1'b0;
else if (dcd_ce)
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&((~r_dcdvalid)||(~dcd_early_branch));
r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
else if (op_ce)
r_dcdvalid <= 1'b0;
assign dcdvalid = r_dcdvalid;
585,7 → 585,7
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
dcdR_wr,dcdA_rd, dcdB_rd,
dcd_early_branch,
dcd_branch_pc,
dcd_branch_pc, dcd_ljmp,
dcd_pipe);
`else
idecode_deprecated
604,6 → 604,7
dcd_early_branch,
dcd_branch_pc,
dcd_pipe);
assign dcd_ljmp = 1'b0;
`endif
 
`ifdef OPT_PIPELINED_BUS_ACCESS
736,7 → 737,7
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
 
wire w_opvalid;
assign w_opvalid = (~clear_pipeline)&&(dcdvalid);
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
initial opvalid = 1'b0;
initial opvalid_alu = 1'b0;
initial opvalid_mem = 1'b0;
1557,7 → 1558,7
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
pf_pc <= wr_reg_vl[(AW-1):0];
`ifdef OPT_PIPELINED
else if ((~new_pc)&&((dcd_early_branch)&&(dcdvalid)))
else if ((dcd_early_branch)&&(~clear_pipeline))
pf_pc <= dcd_branch_pc + 1;
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
/rtl/Makefile
83,6 → 83,7
@echo "Building cpudefs.h"
@echo "// " > $@
@echo "// Do not edit this file, it is automatically generated!" >> $@
@echo "// To generate this file, \"make cpudefs.h\" in the rtl directory." >> $@
@echo "// " >> $@
@grep "^\`" $^ | sed -e '{ s/^`/#/ }' >> $@
 
/rtl/zipbones.v
31,6 → 31,8
//
///////////////////////////////////////////////////////////////////////////
//
`include "cpudefs.v"
//
module zipbones(i_clk, i_rst,
// Wishbone master interface from the CPU
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
/sw/zasm/test.S
77,6 → 77,7
sys.bus.ustl equ 0x00f
#define DO_TEST_ASSEMBLER
#define LJMP_TEST
#define EARLY_BRANCH_TEST
#define BREAK_TEST
#define OVERFLOW_TEST
#define CARRY_TEST
241,6 → 242,18
#endif /* and after endif */
 
#ifdef LJMP_TEST
// A long jump is a 32-bit instruction followed by a 32-bit address.
// The CPU is supposed to jump to this address. At issue in this test,
// which can only really be verified by watching it in person currently,
// is how fast this branch can take place. Currently, it takes four
// clocks--not that bad.
//
// Although really long jumps, we also test some of our early branching
// forms here as well:
// 1. Add to PC
// 2. LOD (PC),PC (the long jump itself)
// 3. LDI x,PC // An early branch target not tested elsewhere
//
CLR R0
CLR R1
LJMP
270,6 → 283,77
CMP 4,R0
BNZ test_failure
#endif
#ifdef EARLY_BRANCH_TEST
// Unlike the previous test, this test is going to see whether or not
// early branching messes with the pipeline.
BRA eb_a
BUSY
eb_a:
BRA eb_b
NOP
BUSY
eb_b:
BRA eb_c
NOP
NOP
BUSY
eb_c:
BRA eb_d
NOP
NOP
NOP
BUSY
eb_d:
BRA eb_e
NOP
NOP
NOP
NOP
BUSY
eb_e:
NOOP
// Only problem is, I don't expect it to mess with the pipeline unless
// the pipeline is full. Therefore we are interested in something which
// is not an early branch, conflicting with early branches. So let's
// try loading our pipeline in all kinds of different configurations,
// just to see which if the conditional branch always annihilates the
// early branch as desired.
//
CLR R0
BZ ebz_a
BUSY
ebz_a:
BZ ebz_b
NOP
BUSY
ebz_b:
BZ ebz_c
NOP
NOP
BUSY
// Let's repeat that last test, just in case the cache reloaded itself
// in the middle and we didn't get our proper test.
ebz_c:
BZ ebz_d
NOP
NOP
BUSY
ebz_d:
BZ ebz_e
NOP
NOP
NOP
BUSY
ebz_e:
BZ ebz_f
NOP
NOP
NOP
NOP
BUSY
ebz_f:
NOOP
#endif
 
#ifdef BREAK_TEST
breaktest:

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