URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
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/zipcpu/trunk
- from Rev 35 to Rev 36
- ↔ Reverse comparison
Rev 35 → Rev 36
/bench/asm/lfsrleds.S
0,0 → 1,123
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
; |
; Filename: lfsrleds.S |
; |
; Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
; |
; Purpose: A test of whether or not we can generate a pseudorandom |
; number stream. This will test the timer peripheral, as well |
; as the LED peripheral external to the Zip CPU. |
; |
; Creator: Dan Gisselquist, Ph.D. |
; Gisselquist Tecnology, LLC |
; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
; |
; Copyright (C) 2015, Gisselquist Technology, LLC |
; |
; This program is free software (firmware): you can redistribute it and/or |
; modify it under the terms of the GNU General Public License as published |
; by the Free Software Foundation, either version 3 of the License, or (at |
; your option) any later version. |
; |
; This program is distributed in the hope that it will be useful, but WITHOUT |
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
; for more details. |
; |
; License: GPL, v3, as defined and found on www.gnu.org, |
; http://www.gnu.org/licenses/gpl.html |
; |
; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
; |
; Registers: |
; R12 - Peripheral base address, for access to the timer(s) |
; R11 - Address of the LED peripheral |
; R10 - LFSR Taps (Galois) |
; R9 - Currend LFSR (Galois) Fill |
; R8 - Curent/next value for the LED register |
; R7 - Value to clear/reset the PIC |
; R6 - Number of ticks in one second |
; R5 - One past top LED bit |
; R4 - LED Update time |
start: |
BRA supervisor_task_start |
user_task: |
WAIT |
BRA user_task |
supervisor_task_start: |
MOV user_task+PC,uPC |
CLR R12 ; Load the address of the peripherals into R12 |
LDIHI $c000h,R12 |
LDI $8,R11 ; Load the address of the LEDs into R11 |
LDI $10000h,R8 ; Clear the value for the LED register |
STO R8,(R11) ; Clear the LEDs |
LDIHI $8010h,R7 ; Clear the PIC |
LDILO $7fffh,R7 |
STO R7,(R12) |
LDI $5f5e1h,R6 ; Set the number of ticks per second |
; LDI $5f5h,R6 ; Set the number of ticks per second |
LSL $8,R6 |
MOV R6,R0 |
LSL $1,R0 ; Wait 2 seconds with the LEDs off |
STO R0,$4(R12) ; Use timer A |
LDI $-1,R0 ; Set a watchdog timer |
STO R0,$1(R12) |
RTU ; Execute our wait |
|
STO R7,(R12) ; Reset our interrupt controller |
LDI $-1,R0 ; (Re)Set a watchdog timer |
STO R0,$1(R12) |
LDI $1ffffh,R8 ; Turn all the LEDs on |
STO R8,(R11) ; |
STO R6,$4(R12) ; Wait one second with LEDs on |
RTU ; Execute our wait |
|
wait_til_leds_off: |
STO R7,(R12) ; Reset our interrupt controller |
LDI $-1,R0 ; (Re)Set a watchdog timer |
STO R0,$1(R12) |
MOV R6,R0 ; Set a time, 1/2 second |
LSR $1,R0 ; Now ahalf second |
STO R0,$4(R12) ; Wait one half second with LEDs on |
AND $0ffffh,R8 |
LSR $1,R8 ; Shift on LEDs to the right |
OR $10000h,R8 |
STO R8,(R11) ; |
RTU ; Execute our wait |
|
TST 0x0ffff,R8 |
BNZ wait_til_leds_off ; Repeat until all LEDs are off again |
|
; Now, start our pseudorandom LED test |
|
STO R7,(R12) ; Reset our interrupt controller |
LDI $-1,R0 ; (Re)Set a watchdog timer |
STO R0,$1(R12) |
LDI $2408bh,R10 ; Set up our LFSR register |
LDI $1,R9 |
LDI $10000,R5 ; One past the number of LEDs in LED register |
MOV R6,R4 |
LSR $2,R4 ; Update 4x/second |
loop: |
STO R7,(R12) ; Reset our interrupt controller |
STO R4,$4(R12) ; Wait one quarter second |
LDI $-1,R0 ; (Re)Set a watchdog timer |
STO R0,$1(R12) |
AND $0ffffh,R8 |
MOV R9,R0 ; Shift top bit of LFSR into LED |
AND $1,R0 |
OR.NE $10000h,R8 |
LSR $1,R8 |
OR $10000h,R8 |
LSR $1,R9 |
TST $1,R0 |
STO R8,(R11) ; Update the LEDs with our pseudorandom info |
XOR.NE R10,R9 |
RTU ; Wait for next interrupt |
|
BRA loop ; Loop until kingdom come |
HALT |
|
|
/bench/asm/lodsto.S
34,15 → 34,16
; |
start: |
LDI $2,R2 |
LOD $5(PC),R0 |
LOD $5(PC),R1 |
LOD peripheral_memory_address(PC),R0 |
LOD $enable_all_interrupts_const(PC),R1 |
STO R1,(R0) |
LDI $1(PC),R0 |
LDI infloop(PC),R0 |
infloop: |
MOV R0,PC |
MOV R0,PC |
MOV R0,PC |
.DAT 0xc0000000 |
.DAT 0x8001ffff |
HALT ; We should never get here. |
peripheral_memory_address |
WORD 0xc0000000 |
enable_all_interrupts_const |
WORD 0x8001ffff |
|
|
/bench/cpp/zippy_tb.cpp
55,12 → 55,13
#define CMD_DATA 1 |
#define CMD_HALT (1<<10) |
#define CMD_STALL (1<<9) |
#define CMD_STEP (1<<8) |
#define CMD_INT (1<<7) |
#define CMD_RESET (1<<6) |
#define CMD_STEP ((1<<8)|CMD_HALT) |
|
#define KEY_ESCAPE 27 |
#define KEY_RETURN 10 |
#define CTRL(X) ((X)&0x01f) |
|
// No particular "parameters" need definition or redefinition here. |
class ZIPPY_TB : public TESTB<Vzipsystem> { |
73,9 → 74,13
int m_cursor; |
|
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) { |
// dbg_fp = fopen("dbg.txt", "w"); |
dbg_fp = NULL; |
dbg_flag = false; |
if (true) { |
dbg_fp = fopen("dbg.txt", "w"); |
dbg_flag = true; |
} else { |
dbg_fp = NULL; |
dbg_flag = false; |
} |
bomb = false; |
m_cursor = 0; |
} |
179,7 → 184,20
int ln= 0; |
|
mvprintw(ln,0, "Peripherals-SS"); ln++; |
printw(" %s", |
// (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":" " |
); |
/* |
printw(" %s%s%s", |
(m_core->v__DOT__thecpu__DOT__ill_err)?"IL":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch)?"EB":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ", |
(m_core->v__DOT__thecpu__DOT__dcd_early_branch_stb)?"S":" ", |
); |
*/ |
|
/* |
showval(ln, 1, "TRAP", m_core->v__DOT__trap_data); |
mvprintw(ln, 17, "%s%s", |
((m_core->v__DOT__sys_cyc) |
189,7 → 207,7
*/ |
showval(ln, 0, "PIC ", m_core->v__DOT__pic_data, (m_cursor==0)); |
showval(ln,20, "WDT ", m_core->v__DOT__watchdog__DOT__r_value, (m_cursor==1)); |
showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2)); |
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2)); |
showval(ln,60, "PIC2", m_core->v__DOT__ctri__DOT__r_int_state, (m_cursor==3)); |
|
ln++; |
237,11 → 255,13
|
showreg(ln, 0, "sR12", 12, (m_cursor==24)); |
showreg(ln,20, "sSP ", 13, (m_cursor==25)); |
mvprintw(ln,40, "sCC :%s%s%s%s%s%s%s%s", |
(m_core->v__DOT__thecpu__DOT__trap)?"TRP":" ", |
(m_core->v__DOT__thecpu__DOT__step)?"STP":" ", |
(m_core->v__DOT__thecpu__DOT__sleep)?"SLP":" ", |
(m_core->v__DOT__thecpu__DOT__gie)?"GIE":" ", |
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s", |
(m_cursor==26)?">":" ", |
(m_core->v__DOT__thecpu__DOT__trap)?"TP":" ", |
(m_core->v__DOT__thecpu__DOT__break_en)?"BK":" ", |
(m_core->v__DOT__thecpu__DOT__step)?"ST":" ", |
(m_core->v__DOT__thecpu__DOT__sleep)?"SL":" ", |
(m_core->v__DOT__thecpu__DOT__gie)?"IE":" ", |
(m_core->v__DOT__thecpu__DOT__iflags&8)?"V":" ", |
(m_core->v__DOT__thecpu__DOT__iflags&4)?"N":" ", |
(m_core->v__DOT__thecpu__DOT__iflags&2)?"C":" ", |
285,13 → 305,16
attroff(A_BOLD); |
ln+=1; |
|
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d", |
mvprintw(ln, 0, "PFPIPE: rda=%08x/%d, bas=%08x, off=%08x, nv=%03x, ackw=%d,%d%d,%04x", |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_base, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cache_offset, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_nvalid, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting); |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_acks_waiting, |
m_core->v__DOT__thecpu__DOT__pf__DOT__w_cv, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_cv, |
m_core->v__DOT__thecpu__DOT__pf__DOT__r_addr&0x0ffff); |
ln++; |
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x", |
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":" ", |
300,20 → 323,23
(m_core->v__DOT__thecpu__DOT__pf_addr), |
0, // (m_core->v__DOT__thecpu__DOT__pf_data), |
(m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":" ", |
(m_core->v__DOT__cpu_stall)?"STL":" ", |
(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ", |
(m_core->v__DOT__wb_data)); ln++; |
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x", |
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"CYC":" ", |
(m_core->v__DOT__thecpu__DOT__mem_stb)?"STB":" ", |
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GCY" |
:((m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LCY":" "), |
(m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB" |
:((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":" "), |
(m_core->v__DOT__thecpu__DOT__mem_we )?"WE":" ", |
(m_core->v__DOT__thecpu__DOT__mem_addr), |
(m_core->v__DOT__thecpu__DOT__mem_data), |
(m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":" ", |
(m_core->v__DOT__cpu_stall)?"STL":" ", |
(m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":" ", |
(m_core->v__DOT__thecpu__DOT__mem_result)); ln++; |
|
mvprintw(ln, 0, "SYSBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x", |
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x", |
(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P', |
(m_core->o_wb_cyc)?"CYC":" ", |
(m_core->o_wb_stb)?"STB":" ", |
(m_core->o_wb_we )?"WE":" ", |
329,8 → 355,8
//m_core->v__DOT__thecpu__DOT__instruction_gie, |
m_core->v__DOT__thecpu__DOT__gie, |
0, |
// m_core->v__DOT__thecpu__DOT__instruction_pc); ln++; |
m_core->v__DOT__thecpu__DOT__pf_pc); ln++; |
m_core->v__DOT__thecpu__DOT__instruction_pc); ln++; |
// m_core->v__DOT__thecpu__DOT__pf_pc); ln++; |
|
showins(ln, "Dc", |
m_core->v__DOT__thecpu__DOT__dcd_ce, |
454,7 → 480,7
} ln++; |
showval(ln, 0, "PIC ", cmd_read(32+ 0), (m_cursor==0)); |
showval(ln,20, "WDT ", cmd_read(32+ 1), (m_cursor==1)); |
showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2)); |
// showval(ln,40, "CACH", cmd_read(32+ 2), (m_cursor==2)); |
showval(ln,60, "PIC2", cmd_read(32+ 3), (m_cursor==3)); |
ln++; |
showval(ln, 0, "TMRA", cmd_read(32+ 4), (m_cursor==4)); |
499,9 → 525,10
dispreg(ln, 0, "sR12", cmd_read(12), (m_cursor==24)); |
dispreg(ln,20, "sSP ", cmd_read(13), (m_cursor==25)); |
|
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s", |
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s%s%s", |
(m_cursor==26)?">":" ", |
(cc & 0x100)?"TP":" ", |
(cc & 0x200)?"TP":" ", |
(cc & 0x080)?"BK":" ", |
(cc & 0x040)?"ST":" ", |
(cc & 0x020)?"IE":" ", |
(cc & 0x010)?"SL":" ", |
536,7 → 563,7
dispreg(ln,20, "uSP ", cmd_read(29), (m_cursor==41)); |
cc = cmd_read(30); |
mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s%s", |
(m_cursor == 42)?">":" ", |
(m_cursor == 42)?'>':' ', |
(cc&0x100)?"TP":" ", |
(cc&0x040)?"ST":" ", |
(cc&0x020)?"IE":" ", |
592,14 → 619,11
int stb = m_core->o_wb_stb; |
if ((m_core->o_wb_addr & (-1<<20))!=1) |
stb = 0; |
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we, |
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data, |
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data); |
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb)) |
m_core->i_wb_ack = 1; |
|
if ((dbg_flag)&&(dbg_fp)) { |
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s\n", |
fprintf(dbg_fp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n", |
(m_core->i_dbg_cyc)?"CYC":" ", |
(m_core->i_dbg_stb)?"STB": |
((m_core->v__DOT__dbg_stb)?"DBG":" "), |
614,7 → 638,8
(m_core->v__DOT__thecpu__DOT__dcdvalid)?"DCDV ":"", |
(m_core->v__DOT__thecpu__DOT__opvalid)?"OPV ":"", |
(m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"", |
(m_core->v__DOT__thecpu__DOT__mem_cyc)?"MCYC ":"", |
(m_core->v__DOT__thecpu__DOT__mem_cyc_gbl)?"GC":" ", |
(m_core->v__DOT__thecpu__DOT__mem_cyc_lcl)?"LC":" ", |
(m_core->v__DOT__thecpu__DOT__alu_wr)?"ALUW ":"", |
(m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"", |
(m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"", |
672,9 → 697,19
m_core->v__DOT__thecpu__DOT__mem_valid, |
m_core->v__DOT__thecpu__DOT__w_iflags, |
m_core->v__DOT__thecpu__DOT__w_uflags); |
fprintf(dbg_fp, "\tbrk=%d,%d\n", |
fprintf(dbg_fp, "\tbrk=%s %d,%d\n", |
(m_core->v__DOT__thecpu__DOT__master_ce)?"CE":" ", |
m_core->v__DOT__thecpu__DOT__break_en, |
m_core->v__DOT__thecpu__DOT__op_break); |
} else if ((dbg_fp)&& |
((m_core->v__DOT__thecpu__DOT__op_break) |
||(m_core->v__DOT__thecpu__DOT__dcd_break))) { |
fprintf(dbg_fp, "NOT SWITCHING TO GIE (gie = %d)\n", gie); |
fprintf(dbg_fp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d\n", |
(m_core->v__DOT__thecpu__DOT__master_ce)?"CE":" ", |
m_core->v__DOT__thecpu__DOT__break_en, |
m_core->v__DOT__thecpu__DOT__dcd_break, |
m_core->v__DOT__thecpu__DOT__op_break); |
} |
|
if (dbg_fp) { |
684,7 → 719,26
fprintf(dbg_fp, "\tNew PC\n"); |
} |
|
TESTB<Vzipsystem>::tick(); |
if (dbg_fp) |
fprintf(dbg_fp, "----------- TICK ----------\n"); |
if (false) { |
m_core->i_clk = 1; |
m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we, |
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data, |
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data); |
eval(); |
m_core->i_clk = 0; |
m_mem(m_core->i_clk, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we, |
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data, |
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data); |
eval(); |
m_tickcount++; |
} else { |
m_mem(1, m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we, |
m_core->o_wb_addr & ((1<<20)-1), m_core->o_wb_data, |
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data); |
TESTB<Vzipsystem>::tick(); |
} |
if ((dbg_fp)&&(gie != m_core->v__DOT__thecpu__DOT__gie)) { |
fprintf(dbg_fp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n", |
(gie)?"User":"Supervisor", |
716,10 → 770,12
bool test_failure(void) { |
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid) |
&&(m_mem[m_core->v__DOT__thecpu__DOT__alu_pc-1] |
== 0x2f0f7fff)); |
== 0x2f0f7fff) |
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline)); |
} |
|
void wb_write(unsigned a, unsigned int v) { |
int errcount = 0; |
mvprintw(0,35, "%40s", ""); |
mvprintw(0,40, "wb_write(%d,%x)", a, v); |
m_core->i_dbg_cyc = 1; |
729,11 → 785,11
m_core->i_dbg_data = v; |
|
tick(); |
while(m_core->o_dbg_stall) |
while((errcount++ < 100)&&(m_core->o_dbg_stall)) |
tick(); |
|
m_core->i_dbg_stb = 0; |
while(!m_core->o_dbg_ack) |
while((errcount++ < 100)&&(!m_core->o_dbg_ack)) |
tick(); |
|
// Release the bus |
742,10 → 798,15
tick(); |
mvprintw(0,35, "%40s", ""); |
mvprintw(0,40, "wb_write -- complete"); |
|
|
if (errcount >= 100) |
bomb = true; |
} |
|
unsigned long wb_read(unsigned a) { |
unsigned int v; |
int errcount = 0; |
mvprintw(0,35, "%40s", ""); |
mvprintw(0,40, "wb_read(0x%08x)", a); |
m_core->i_dbg_cyc = 1; |
754,11 → 815,11
m_core->i_dbg_addr = a & 1; |
|
tick(); |
while(m_core->o_dbg_stall) |
while((errcount++<100)&&(m_core->o_dbg_stall)) |
tick(); |
|
m_core->i_dbg_stb = 0; |
while(!m_core->o_dbg_ack) |
while((errcount++<100)&&(!m_core->o_dbg_ack)) |
tick(); |
v = m_core->o_dbg_data; |
|
770,6 → 831,8
mvprintw(0,35, "%40s", ""); |
mvprintw(0,40, "wb_read = 0x%08x", v); |
|
if (errcount >= 100) |
bomb = true; |
return v; |
} |
|
824,6 → 887,7
case KEY_LEFT: case KEY_BACKSPACE: |
if (pos > 0) pos--; |
break; |
case CTRL('L'): redrawwin(stdscr); break; |
case KEY_CLEAR: |
pos = 0; |
break; |
889,7 → 953,7
break; |
case 32: tb->m_core->v__DOT__pic_data = v; break; |
case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break; |
case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break; |
// case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break; |
case 35: tb->m_core->v__DOT__ctri__DOT__r_int_state = v; break; |
case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break; |
case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break; |
931,7 → 995,7
int main(int argc, char **argv) { |
Verilated::commandArgs(argc, argv); |
ZIPPY_TB *tb = new ZIPPY_TB(); |
bool autorun = false, exit_on_done = false; |
bool autorun = false, exit_on_done = false, autostep=false; |
|
// mem[0x00000] = 0xbe000010; // Halt instruction |
unsigned int mptr = 0; |
953,6 → 1017,9
usage(); |
exit(0); |
break; |
case 's': |
autostep = true; |
break; |
default: |
usage(); |
exit(-1); |
994,6 → 1061,15
|
done = (tb->test_success())||(tb->test_failure()); |
} |
} else if (autostep) { |
bool done = false; |
|
printf("Running in non-interactive mode, via step commands\n"); |
tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET); |
while(!done) { |
tb->wb_write(CMD_REG, CMD_STEP); |
done = (tb->test_success())||(tb->test_failure()); |
} |
} else { // Interactive |
initscr(); |
raw(); |
1034,7 → 1110,10
done = true; |
break; |
case 'r': case 'R': |
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT); |
if (manual) |
tb->reset(); |
else |
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT); |
halted = true; |
erase(); |
break; |
1062,6 → 1141,7
case KEY_DOWN: tb->cursor_down(); break; |
case KEY_LEFT: tb->cursor_left(); break; |
case KEY_RIGHT: tb->cursor_right(); break; |
case CTRL('L'): redrawwin(stdscr); break; |
case ERR: case KEY_CLEAR: |
default: |
if (!manual) |
1113,12 → 1193,18
printf("Instructions / Clock: %.2f\n", |
(double)tb->m_core->v__DOT__mic_data |
/ (double)tb->m_core->v__DOT__mtc_data); |
if (tb->test_success()) |
|
int rcode = 0; |
if (tb->bomb) { |
printf("TEST BOMBED\n"); |
rcode = -1; |
} else if (tb->test_success()) { |
printf("SUCCESS!\n"); |
else if (tb->test_failure()) |
} else if (tb->test_failure()) { |
rcode = -2; |
printf("TEST FAILED!\n"); |
else |
} else |
printf("User quit\n"); |
exit(0); |
exit(rcode); |
} |
|
/bench/cpp/testb.h
50,10 → 50,10
} |
|
virtual void tick(void) { |
m_core->i_clk = 1; |
eval(); |
m_core->i_clk = 0; |
eval(); |
m_core->i_clk = 1; |
eval(); |
|
m_tickcount++; |
} |
63,7 → 63,7
tick(); |
m_core->i_rst = 0; |
m_tickcount = 0l; |
printf("RESET\n"); |
// printf("RESET\n"); |
} |
}; |
|
/bench/cpp/memsim.cpp
79,11 → 79,11
m_mem[nr] = 0l; |
} |
|
void MEMSIM::apply(const unsigned char wb_cyc, |
void MEMSIM::apply(const unsigned int clk, const unsigned char wb_cyc, |
const unsigned char wb_stb, const unsigned char wb_we, |
const BUSW wb_addr, const BUSW wb_data, |
unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) { |
if ((wb_cyc)&&(wb_stb)) { |
if ((wb_cyc)&&(wb_stb)&&(clk)) { |
if (wb_we) |
m_mem[wb_addr & m_mask] = wb_data; |
o_ack = 1; |
95,7 → 95,7
(wb_we)?"WRITE":"READ", |
wb_addr, o_data); |
*/ |
} else { |
} else if (clk) { |
o_ack = 0; |
o_stall = 0; |
} |
/bench/cpp/Makefile
45,11 → 45,21
LIBS := $(RAWLIB) -lncurses |
TESTF := ../../sw/zasm/z.out |
|
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h |
zippy_tb: $(SOURCES) $(RAWLIB) $(ZASM)/zopcodes.h $(ZASM)/zparser.h testb.h |
$(CXX) $(FLAGS) $(INCS) $(SOURCES) $(LIBS) -o $@ |
|
.PHONY: stest |
stest: zippy_tb |
./zippy_tb -s $(TESTF) |
|
.PHONY: itest |
itest: zippy_tb |
./zippy_tb $(TESTF) |
|
test: zippy_tb |
.PHONY: test |
test: zippy_tb stest |
./zippy_tb -a $(TESTF) |
|
.PHONY: clean |
clean: |
rm ./zippy_tb |
/bench/cpp/memsim.h
51,13 → 51,14
MEMSIM(const unsigned int nwords); |
~MEMSIM(void); |
void load(const char *fname); |
void apply(const uchar wb_cyc, const uchar wb_stb, const uchar wb_we, |
void apply(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, |
const uchar wb_we, |
const BUSW wb_addr, const BUSW wb_data, |
uchar &o_ack, uchar &o_stall, BUSW &o_data); |
void operator()(const uchar wb_cyc, const uchar wb_stb, const uchar wb_we, |
void operator()(const unsigned clk, const uchar wb_cyc, const uchar wb_stb, const uchar wb_we, |
const BUSW wb_addr, const BUSW wb_data, |
uchar &o_ack, uchar &o_stall, BUSW &o_data) { |
apply(wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data); |
apply(clk, wb_cyc, wb_stb, wb_we, wb_addr, wb_data, o_ack, o_stall, o_data); |
} |
BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; } |
}; |
/rtl/core/memops.v
11,6 → 11,9
// before it completes the last one. Unpredictable results might then |
// occurr. |
// |
// 20150919 -- Added support for handling BUS ERR's (i.e., the WB |
// error signal). |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
36,9 → 39,11
// |
module memops(i_clk, i_rst, i_stb, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_valid, o_wreg, o_result, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data); |
o_busy, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
input i_clk, i_rst; |
input i_stb; |
// CPU interface |
49,29 → 54,49
// CPU outputs |
output wire o_busy; |
output reg o_valid; |
output reg o_err; |
output reg [4:0] o_wreg; |
output reg [31:0] o_result; |
// Wishbone outputs |
output reg o_wb_cyc, o_wb_stb, o_wb_we; |
output reg o_wb_cyc_gbl, o_wb_stb_gbl; |
output reg o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we; |
output reg [31:0] o_wb_addr, o_wb_data; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall; |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
|
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
always @(posedge i_clk) |
if (i_rst) |
o_wb_cyc <= 1'b0; |
else if (o_wb_cyc) |
o_wb_cyc <= (~i_wb_ack); |
else if (i_stb) // New memory operation |
// Grab the wishbone |
o_wb_cyc <= 1'b1; |
begin |
o_wb_cyc_gbl <= 1'b0; |
o_wb_cyc_lcl <= 1'b0; |
end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl)) |
begin |
if ((i_wb_ack)||(i_wb_err)) |
begin |
o_wb_cyc_gbl <= 1'b0; |
o_wb_cyc_lcl <= 1'b0; |
end |
end else if (i_stb) // New memory operation |
begin // Grab the wishbone |
o_wb_cyc_lcl <= lcl_stb; |
o_wb_cyc_gbl <= gbl_stb; |
end |
always @(posedge i_clk) |
if (o_wb_cyc) |
o_wb_stb <= (o_wb_stb)&&(i_wb_stall); |
if (o_wb_cyc_gbl) |
o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall); |
else |
o_wb_stb <= i_stb; // Grab wishbone on new operation |
o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation |
always @(posedge i_clk) |
if (o_wb_cyc_lcl) |
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); |
else |
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation |
always @(posedge i_clk) |
if (i_stb) |
begin |
o_wb_we <= i_op; |
81,8 → 106,11
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we); |
assign o_busy = o_wb_cyc; |
o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we); |
initial o_err = 1'b0; |
always @(posedge i_clk) |
o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err); |
assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl); |
|
always @(posedge i_clk) |
if (i_stb) |
/rtl/core/prefetch.v
13,6 → 13,12
// a suggestion of what to load. Other wires may be loaded |
// instead. i_pc is what must be output, not necessarily input. |
// |
// 20150919 -- Added support for the WB error signal. When reading an |
// instruction results in this signal being raised, the pipefetch |
// module will set an illegal instruction flag to be returned to |
// the CPU together with the instruction. Hence, the ZipCPU |
// can trap on it if necessary. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
42,9 → 48,9
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read, |
// or 72 clocks to fetch one instruction. |
module prefetch(i_clk, i_rst, i_ce, i_pc, i_aux, |
o_i, o_pc, o_aux, o_valid, |
o_i, o_pc, o_aux, o_valid, o_illegal, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data); |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter AW = 1; |
input i_clk, i_rst, i_ce; |
input [31:0] i_pc; |
52,7 → 58,7
output reg [31:0] o_i; |
output reg [31:0] o_pc; |
output reg [(AW-1):0] o_aux; |
output wire o_valid; |
output wire o_valid, o_illegal; |
// Wishbone outputs |
output reg o_wb_cyc, o_wb_stb; |
output wire o_wb_we; |
59,7 → 65,7
output reg [31:0] o_wb_addr; |
output wire [31:0] o_wb_data; |
// And return inputs |
input i_wb_ack, i_wb_stall; |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
|
assign o_wb_we = 1'b0; |
103,5 → 109,6
o_pc <= o_wb_addr; |
|
assign o_valid = (i_pc == o_pc)&&(i_aux == o_aux)&&(~o_wb_cyc); |
assign o_illegal = (o_wb_cyc)&&(i_wb_err); |
|
endmodule |
/rtl/core/pipefetch.v
14,6 → 14,17
// the purposes of this instruction fetch module: 1) Pipeline |
// wishbone accesses, and 2) an instruction cache. |
// |
// 20150919 -- Fixed a nasty race condition whereby the pipefetch routine |
// would produce either the same instruction twice, or skip |
// an instruction. This condition was dependent on the CPU stall |
// condition, and would only take place if the pipeline wasn't |
// completely full throughout the stall. |
// |
// Interface support was also added for trapping on illegal |
// instructions (i.e., instruction fetches that cause bus errors), |
// however the internal interface has not caught up to supporting |
// these exceptions yet. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
40,7 → 51,8
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc, |
o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_request); |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request, |
o_illegal); |
parameter RESET_ADDRESS=32'h0010_0000, |
LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN), |
BUSW=32; |
56,12 → 68,15
output reg [(BUSW-1):0] o_wb_addr; |
output wire [(BUSW-1):0] o_wb_data; |
// |
input i_wb_ack, i_wb_stall; |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [(BUSW-1):0] i_wb_data; |
// |
// Is the (data) memory unit also requesting access to the bus? |
input i_wb_request; |
output wire o_illegal; |
|
assign o_illegal = 1'b0; |
|
// Fixed bus outputs: we read from the bus only, never write. |
// Thus the output data is ... irrelevant and don't care. We set it |
// to zero just to set it to something. |
93,7 → 108,6
assign w_running_out_of_cache = (r_addr_set) |
&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2)) |
+ (1<<(LGCACHELEN-1))); |
initial r_nvalid = 0; |
initial r_cache_base = RESET_ADDRESS; |
always @(posedge i_clk) |
begin |
161,10 → 175,12
// r_nvalid <= r_nvalid + 1; |
if ((r_acks_waiting == 1)&&(~o_wb_stb)) |
o_wb_cyc <= 1'b0; |
end |
end else if ((r_acks_waiting == 0)&&(~o_wb_stb)) |
o_wb_cyc <= 1'b0; |
end |
end |
|
initial r_nvalid = 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset |
r_nvalid <= 0; |
210,9 → 226,9
if (~o_wb_cyc) |
r_acks_waiting <= 0; |
else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) |
r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1); |
r_acks_waiting <= r_acks_waiting + 1; |
else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) |
r_acks_waiting <= r_acks_waiting - 1; |
r_acks_waiting <= r_acks_waiting - 1; |
|
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
232,13 → 248,13
assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base) |
&&(r_addr-r_cache_base < bus_nvalid)); |
always @(posedge i_clk) |
r_cv <= (~i_new_pc)&&(w_cv); |
r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv))); |
assign o_v = (r_cv)&&(~i_new_pc); |
|
always @(posedge i_clk) |
if (i_new_pc) |
r_addr <= i_pc; |
else if ((i_stall_n)&&(w_cv)) |
else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) ) |
r_addr <= r_addr + 1; |
|
wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base; |
245,10 → 261,10
assign c_cache_base = r_cache_base[(LGCACHELEN-1):0]; |
assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset; |
always @(posedge i_clk) |
if (i_stall_n) |
if ((~o_v)||((i_stall_n)&&(o_v))) |
o_i <= cache[c_rdaddr]; |
always @(posedge i_clk) |
if (i_stall_n) |
if ((~o_v)||((i_stall_n)&&(o_v))) |
o_pc <= r_addr; |
|
endmodule |
/rtl/core/zipcpu.v
106,6 → 106,20
// |
/////////////////////////////////////////////////////////////////////////////// |
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
// Slice LUTs ZipSystem ZipCPU |
// Single Fetching 2521 1734 |
// Pipelined fetching 2796 2046 |
// |
// `define SINGLE_FETCH |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_TRAP_BIT 9 |
113,6 → 127,13
`define CPU_STEP_BIT 6 |
`define CPU_GIE_BIT 5 |
`define CPU_SLEEP_BIT 4 |
// Compile time defines |
// `define SINGLE_FETCH |
`define NG_CONDITIONAL_FLAGS |
`define NG_PRECLEAR_BUS // 0.61 w/ or w/o |
// `define NG_BRANCH_DELAY_SLOT |
`define NG_ILLEGAL_INSTRUCTION |
`define NG_EARLY_BRANCHING // 0.60 w/, 0.61 w/o ???? |
module zipcpu(i_clk, i_rst, i_interrupt, |
// Debug interface |
i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data, |
119,8 → 140,11
o_dbg_stall, o_dbg_reg, o_dbg_cc, |
o_break, |
// CPU interface to the wishbone bus |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
o_wb_gbl_cyc, o_wb_gbl_stb, |
o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_err, |
// Accounting/CPU usage interface |
o_op_stall, o_pf_stall, o_i_count); |
parameter RESET_ADDRESS=32'h0100000; |
136,11 → 160,13
output reg [1:0] o_dbg_cc; |
output wire o_break; |
// Wishbone interface -- outputs |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
output wire o_wb_gbl_cyc, o_wb_gbl_stb; |
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we; |
output wire [31:0] o_wb_addr, o_wb_data; |
// Wishbone interface -- inputs |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
// Accounting outputs ... to help us count stalls and usage |
output wire o_op_stall; |
output wire o_pf_stall; |
152,8 → 178,12
|
// Condition codes |
reg [3:0] flags, iflags; // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
wire [9:0] w_uflags, w_iflags; |
wire [10:0] w_uflags, w_iflags; |
reg trap, break_en, step, gie, sleep; |
`ifdef NG_ILLEGAL_INSTRUCTION |
reg ill_err; |
`endif |
reg bus_err_flag; |
|
// The master chip enable |
wire master_ce; |
166,13 → 196,13
reg [31:0] pf_pc; |
reg new_pc, op_break; |
wire clear_pipeline; |
assign clear_pipeline = new_pc || i_clear_pf_cache || op_break; |
assign clear_pipeline = new_pc || i_clear_pf_cache; // || op_break; |
|
wire dcd_stalled; |
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall; |
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err; |
wire [31:0] pf_addr, pf_data; |
wire [31:0] instruction, instruction_pc; |
wire pf_valid, instruction_gie; |
wire pf_valid, instruction_gie, pf_illegal; |
|
// |
// |
192,6 → 222,19
reg [23:0] r_dcdI; |
wire dcdA_stall, dcdB_stall, dcdF_stall; |
|
`ifdef NG_PRECLEAR_BUS |
reg dcd_clear_bus; |
`endif |
`ifdef NG_ILLEGAL_INSTRUCTION |
reg dcd_illegal; |
`endif |
`ifdef NG_EARLY_BRANCHING |
reg dcd_early_branch_stb, dcd_early_branch; |
reg [31:0] dcd_branch_pc; |
`else |
wire dcd_early_branch_stb, dcd_early_branch; |
wire [31:0] dcd_branch_pc; |
`endif |
|
|
// |
210,13 → 253,18
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opR_cc, opF_wr, op_gie, |
opA_rd, opB_rd; |
wire [9:0] opFl; |
wire [10:0] opFl; |
reg [6:0] r_opF; |
wire [8:0] opF; |
wire op_ce; |
`ifdef NG_PRECLEAR_BUS |
reg op_clear_bus; |
`endif |
`ifdef NG_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`endif |
|
|
|
// |
// |
// PIPELINE STAGE #4 :: ALU / Memory |
231,12 → 279,15
wire alu_valid; |
wire set_cond; |
reg alu_wr, alF_wr, alu_gie; |
`ifdef NG_ILLEGAL_INSTRUCTION |
reg alu_illegal; |
`endif |
|
|
|
wire mem_ce, mem_stalled; |
wire mem_valid, mem_ack, mem_stall, |
mem_cyc, mem_stb, mem_we; |
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err, |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we; |
wire [4:0] mem_wreg; |
|
wire mem_busy, mem_rdbusy; |
274,7 → 325,10
assign dcd_stalled = (dcdvalid)&&( |
(op_stall) |
||((dcdA_stall)||(dcdB_stall)||(dcdF_stall)) |
||((opvalid)&&((op_wr_pc)||(opR_cc)))); |
`ifndef NG_BRANCH_DELAY_SLOT |
||((opvalid_mem)&&(op_wr_pc)) |
`endif |
||((opvalid_mem)&&(opR_cc))); |
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
285,9 → 339,25
// |
// PIPELINE STAGE #4 :: ALU / Memory |
// Calculate stall conditions |
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) |
// |
// 1. Basic stall is if the previous stage is valid and the next is |
// busy. |
// 2. Also stall if the prior stage is valid and the master clock enable |
// is de-selected |
// 3. Next case: Stall if we want to start a memory operation and the |
// prior operation will write either the PC or CC registers. |
// 4. Last case: Stall if we would otherwise move a break instruction |
// through the ALU. Break instructions are not allowed through |
// the ALU. |
assign alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2 |
`ifdef BEFORE |
||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie) |
&&(wr_write_pc)||(wr_write_cc)); |
&&((wr_write_pc)||(wr_write_cc)) // Case 3 |
`else |
||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie) |
&&((wr_write_pc)||(wr_write_cc))) // Case 3 |
`endif |
||((opvalid)&&(op_break)); // Case 4 |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline); |
// |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond); |
311,31 → 381,90
assign pf_ce = (~dcd_stalled); |
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, |
pf_data, |
pf_ack, pf_stall, i_wb_data); |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data); |
`else // Pipe fetch |
pipefetch #(RESET_ADDRESS) |
pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc, |
pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb), |
i_clear_pf_cache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, i_wb_data, |
mem_cyc); |
pf_ack, pf_stall, pf_err, i_wb_data, |
`ifdef NG_PRECLEAR_BUS |
((dcd_clear_bus)&&(dcdvalid)) |
||((op_clear_bus)&&(opvalid)) |
|| |
`endif |
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
assign instruction_gie = gie; |
`endif |
|
initial dcdvalid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
dcdvalid <= 1'b0; |
else if (dcd_ce) |
dcdvalid <= (~clear_pipeline); |
else if ((~dcd_stalled)||(clear_pipeline)) |
dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb); |
else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch)) |
dcdvalid <= 1'b0; |
|
`ifdef NG_EARLY_BRANCHING |
always @(posedge i_clk) |
if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)) |
begin |
dcd_early_branch <= 1'b0; |
// First case, a move to PC instruction |
if ((instruction[31:28] == 4'h2) |
&&((instruction_gie) |
||((~instruction[20])&&(~instruction[15]))) |
&&(instruction[23:21]==3'h0)) |
begin |
dcd_early_branch_stb <= 1'b1; |
dcd_early_branch <= 1'b1; |
// r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] }; |
|
end else // Next case, an Add Imm -> PC instruction |
if ((instruction[31:28] == 4'ha) // Add |
&&(~instruction[20]) // Immediate |
&&(instruction[23:21]==3'h0)) // Always |
begin |
dcd_early_branch_stb <= 1'b1; |
dcd_early_branch <= 1'b1; |
// r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] }; |
end else // Next case: load Immediate to PC |
if (instruction[31:28] == 4'h3) |
begin |
dcd_early_branch_stb <= 1'b1; |
dcd_early_branch <= 1'b1; |
// r_dcdI <= { instruction[23:0] }; |
end |
end else |
begin |
if (dcd_ce) dcd_early_branch <= 1'b0; |
dcd_early_branch_stb <= 1'b0; |
end |
always @(posedge i_clk) |
if (dcd_ce) |
begin |
if (instruction[31]) // Add |
dcd_branch_pc <= instruction_pc+32'h01+{ {(12){instruction[19]}}, instruction[19:0] }; |
else if (~instruction[28]) // 4'h2 = MOV |
dcd_branch_pc <= instruction_pc+32'h01+{ {(17){instruction[14]}}, instruction[14:0] }; |
else // if (instruction[28]) // 4'h3 = LDI |
dcd_branch_pc <= instruction_pc+32'h01+{ {(8){instruction[23]}}, instruction[23:0] }; |
end |
`else // NG_EARLY_BRANCHING |
assign dcd_early_branch_stb = 1'b0; |
assign dcd_early_branch = 1'b0; |
assign dcd_branch_pc = 32'h00; |
`endif // NG_EARLY_BRANCHING |
|
always @(posedge i_clk) |
if (dcd_ce) |
begin |
dcd_pc <= instruction_pc+1; |
|
// Record what operation we are doing |
349,7 → 478,17
dcdA_pc <= (instruction[27:24] == `CPU_PC_REG); |
dcdB_pc <= (instruction[19:16] == `CPU_PC_REG); |
dcdM <= 1'b0; |
`ifdef NG_CONDITIONAL_FLAGS |
dcdF_wr <= (instruction[23:21]==3'h0); |
`else |
dcdF_wr <= 1'b1; |
`endif |
`ifdef NG_PRECLEAR_BUS |
dcd_clear_bus <= 1'b0; |
`endif |
`ifdef NG_ILLEGAL_INSTRUCTION |
dcd_illegal <= pf_illegal; |
`endif |
|
// Set the condition under which we do this operation |
// The top four bits are a mask, the bottom four the |
378,8 → 517,15
dcdOp <= 4'h2; |
end |
4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK |
`ifdef NG_CONDITIONAL_FLAGS |
// Don't write flags except for multiplies |
// and then only if they are unconditional |
dcdF_wr <= ((instruction[27:25] != 3'h7) |
&&(instruction[23:21]==3'h0)); |
`else |
// Don't write flags except for multiplies |
dcdF_wr <= (instruction[27:25] != 3'h7); |
`endif |
r_dcdI <= { 8'h00, instruction[15:0] }; |
if (instruction[27:24] == 4'he) |
begin |
388,6 → 534,11
dcdA_rd <= 1'b0; |
dcdB_rd <= 1'b0; |
dcdOp <= 4'h2; |
// Might also be a break. Big |
// instruction set hole here. |
`ifdef NG_ILLEGAL_INSTRUCTION |
dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0); |
`endif |
end else if (instruction[27:24] == 4'hf) |
begin // Load partial immediate(s) |
dcdA_wr <= 1'b1; |
414,6 → 565,9
else |
r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] }; |
dcdM <= 1'b1; // Memory operation |
`ifdef NG_PRECLEAR_BUS |
dcd_clear_bus <= (instruction[23:21]==3'h0); |
`endif |
end |
default: begin |
dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5); |
432,7 → 586,7
always @(posedge i_clk) |
if (dcd_ce) |
dcd_break <= (instruction[31:0] == 32'h4e000001); |
else |
else if ((clear_pipeline)||(~dcdvalid)) |
dcd_break <= 1'b0; |
|
|
453,28 → 607,21
else if (dcdA_pc) |
r_opA <= upc; |
else if (dcdA_cc) |
r_opA <= { w_opA[31:10], (dcd_gie)?w_uflags:w_iflags }; |
r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags }; |
else |
r_opA <= w_opA; |
end |
wire [31:0] dcdI; |
wire [31:0] dcdI, w_opBnI; |
assign dcdI = { {(8){r_dcdI[23]}}, r_dcdI }; |
assign w_opBnI = (~dcdB_rd) ? 32'h00 |
: (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl |
: (((dcdB_pc)&&(dcdB[4] == dcd_gie)) ? dcd_pc |
: ((dcdB_pc) ? upc |
: ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags} |
: regset[dcdB])))); |
always @(posedge i_clk) |
if (op_ce) // &&(dcdvalid)) |
begin |
if (~dcdB_rd) |
r_opB <= dcdI; |
else if ((wr_reg_ce)&&(wr_reg_id == dcdB)) |
r_opB <= wr_reg_vl + dcdI; |
else if ((dcdB_pc)&&(dcdB[4] == dcd_gie)) |
r_opB <= dcd_pc + dcdI; |
else if (dcdB_pc) // & dcdB[4] != dcd_gie thus is user |
r_opB <= upc + dcdI; |
else if (dcdB_cc) |
r_opB <= { w_opB[31:10], (dcd_gie)?w_uflags:w_iflags} + dcdI; |
else |
r_opB <= regset[dcdB] + dcdI; |
end |
r_opB <= w_opBnI + dcdI; |
|
// The logic here has become more complex than it should be, no thanks |
// to Xilinx's Vivado trying to help. The conditions are supposed to |
487,7 → 634,7
// opF. |
always @(posedge i_clk) |
if (op_ce) |
begin // Set the flag condition codes |
begin // Set the flag condition codes, bit order is [3:0]=VNCZ |
case(dcdF[2:0]) |
3'h0: r_opF <= 7'h80; // Always |
3'h1: r_opF <= 7'h11; // Z |
498,9 → 645,12
3'h6: r_opF <= 7'h02; // C |
3'h7: r_opF <= 7'h08; // V |
endcase |
end |
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } |
assign opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
|
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
518,8 → 668,13
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
`ifdef NG_ILLEGAL_INSTRUCTION |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
`else |
opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled); |
`endif |
end else if ((~op_stall)||(clear_pipeline)) |
begin |
opvalid <= 1'b0; |
543,15 → 698,26
else if ((clear_pipeline)||(~opvalid)) |
op_break <= 1'b0; |
|
`ifdef NG_ILLEGAL_INSTRUCTION |
always @(posedge i_clk) |
if(op_ce) |
op_illegal <= dcd_illegal; |
`endif |
|
always @(posedge i_clk) |
if (op_ce) |
begin |
opn <= dcdOp; // Which ALU operation? |
// opM <= dcdM; // Is this a memory operation? |
`ifdef NG_EARLY_BRANCH |
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch); |
opR_wr <= (dcdA_wr)&&(~dcd_early_branch); |
`else |
// Will we write the flags/CC Register with our result? |
opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr)); |
// Will we be writing our results into a register? |
opR_wr <= dcdA_wr; |
`endif |
// What register will these results be written into? |
opR <= dcdA; |
opR_cc <= (dcdA_wr)&&(dcdA_cc); |
567,7 → 733,15
opB_rd <= dcdB_rd; |
op_pc <= dcd_pc; |
// |
`ifdef NG_EARLY_BRANCHING |
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch); |
`else |
op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie)); |
`endif |
|
`ifdef NG_PRECLEAR_BUS |
op_clear_bus <= dcd_clear_bus; |
`endif |
end |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
|
583,45 → 757,29
// We'll create a flag here to start our coordination. Once we |
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
`define DONT_STALL_ON_OPA |
`ifdef DONT_STALL_ON_OPA |
reg opA_alu; |
always @(posedge i_clk) |
if (op_ce) |
opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd); |
assign opA = (opA_alu) ? alu_result : r_opA; |
`else |
assign opA = r_opA; |
`endif |
|
assign dcdA_stall = (dcdvalid)&&(dcdA_rd)&&( |
`define DONT_STALL_ON_OPA |
`ifdef DONT_STALL_ON_OPA |
// Skip the requirement on writing back opA |
// Stall on memory, since we'll always need to stall for a |
// memory access anyway |
((opvalid_mem)&&(opR_wr)&&(opR == dcdA))|| |
((opvalid_alu)&&(opF_wr)&&(dcdA_cc))|| |
`else |
((opvalid)&&(opR_wr)&&(opR == dcdA))|| |
`endif |
((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA))); |
`define DONT_STALL_ON_OPB |
`ifdef DONT_STALL_ON_OPB |
|
reg opB_alu; |
always @(posedge i_clk) |
if (op_ce) |
opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0); |
assign opB = (opB_alu) ? alu_result : r_opB; |
`else |
assign opB = r_opB; |
`endif |
assign dcdB_stall = (dcdvalid)&&(dcdB_rd)&&( |
((opvalid)&&(opR_wr)&&(opR == dcdB) |
&&((opvalid_mem)||(dcdI != 0))) |
||((opvalid_alu)&&(opF_wr)&&(dcdB_cc)) |
`ifdef DONT_STALL_ON_OPB |
`endif |
||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB))); |
assign dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc)) |
&&(opvalid)&&(opR_cc); |
666,21 → 824,26
|
memops domem(i_clk, i_rst, mem_ce, |
(opn[0]), opB, opA, opR, |
mem_busy, mem_valid, mem_wreg, mem_result, |
mem_cyc, mem_stb, mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, i_wb_data); |
assign mem_rdbusy = ((mem_cyc)&&(~mem_we)); |
mem_busy, mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, mem_err, i_wb_data); |
assign mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we)); |
|
// Either the prefetch or the instruction gets the memory bus, but |
// never both. |
wbarbiter #(32,32) pformem(i_clk, i_rst, |
wbdblpriarb #(32,32) pformem(i_clk, i_rst, |
// Memory access to the arbiter, priority position |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err, |
// Prefetch access to the arbiter |
pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall, |
// Memory access to the arbiter |
mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall, |
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, |
// Common wires, in and out, of the arbiter |
o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack, |
i_wb_stall); |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err); |
|
// |
// |
700,7 → 863,11
// bus instruction, so they don't need to be checked here. |
// Further, alu_wr includes (set_cond), so we don't need to |
// check for that here either. |
assign wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid); |
`ifdef NG_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid); |
`else |
assign wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid); |
`endif |
// Which register shall be written? |
assign wr_reg_id = (alu_wr)?alu_reg:mem_wreg; |
// Are we writing to the CC register? |
719,9 → 886,14
// Write back to the condition codes/flags register ... |
// When shall we write to our flags register? alF_wr already |
// includes the set condition ... |
assign wr_flags_ce = (alF_wr)&&(alu_valid); |
assign w_uflags = { trap, 1'b0, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { trap, 1'b0, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
assign wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal); |
`ifdef NG_ILLEGAL_INSTRUCTION |
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
`else |
assign w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags }; |
assign w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
`endif |
// What value to write? |
always @(posedge i_clk) |
// If explicitly writing the register itself |
767,7 → 939,18
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b0, `CPU_CC_REG })) |
break_en <= i_dbg_data[`CPU_BREAK_BIT]; |
assign o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy); |
`ifdef NG_ILLEGAL_INSTRUCTION |
assign o_break = ((break_en)||(~op_gie))&&(op_break) |
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy) |
&&(~clear_pipeline) |
||((~alu_gie)&&(bus_err)) |
||((~alu_gie)&&(alu_valid)&&(alu_illegal)); |
`else |
assign o_break = (((break_en)||(~op_gie))&&(op_break) |
&&(~alu_valid)&&(~mem_valid)&&(~mem_busy) |
&&(~clear_pipeline)) |
||((~alu_gie)&&(bus_err)) |
`endif |
|
|
// The sleep register. Setting the sleep register causes the CPU to |
811,8 → 994,12
// If we are stepping the CPU |
||((master_ce)&&(alu_pc_valid)&&(step)) |
// If we encounter a break instruction, if the break |
// enable isn't not set. |
// enable isn't set. |
||((master_ce)&&(op_break)&&(~break_en)) |
`ifdef NG_ILLEGAL_INSTRUCTION |
// On an illegal instruction |
||((alu_valid)&&(alu_illegal)) |
`endif |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
849,6 → 1036,25
else if (w_release_from_interrupt) |
trap <= 1'b0; |
|
`ifdef NG_ILLEGAL_INSTRUCTION |
initial ill_err = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
ill_err <= 1'b0; |
else if (w_release_from_interrupt) |
ill_err <= 1'b0; |
else if ((alu_valid)&&(alu_illegal)&&(gie)) |
ill_err <= 1'b1; |
`endif |
initial bus_err_flag = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
bus_err_flag <= 1'b0; |
else if (w_release_from_interrupt) |
bus_err_flag <= 1'b0; |
else if ((bus_err)&&(alu_gie)) |
bus_err_flag <= 1'b1; |
|
// |
// Write backs to the PC register, and general increments of it |
// We support two: upc and ipc. If the instruction is normal, |
862,7 → 1068,7
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
upc <= wr_reg_vl; |
else if ((alu_gie)&&(alu_pc_valid)) |
else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
upc <= alu_pc; |
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b1, `CPU_PC_REG })) |
873,7 → 1079,7
ipc <= RESET_ADDRESS; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= wr_reg_vl; |
else if ((~alu_gie)&&(alu_pc_valid)) |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
ipc <= alu_pc; |
else if ((i_halt)&&(i_dbg_we) |
&&(i_dbg_reg == { 1'b0, `CPU_PC_REG })) |
918,7 → 1124,7
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
o_dbg_reg[9:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
end |
always @(posedge i_clk) |
o_dbg_cc <= { gie, sleep }; |
925,7 → 1131,7
|
always @(posedge i_clk) |
o_dbg_stall <= (i_halt)&&( |
(pf_cyc)||(mem_cyc)||(mem_busy) |
(pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy) |
||((~opvalid)&&(~i_rst)) |
||((~dcdvalid)&&(~i_rst))); |
|
/rtl/zipsystem.v
82,33 → 82,61
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// While I hate adding delays to any bus access, these two are required |
// While I hate adding delays to any bus access, this next delay is required |
// to make timing close in my Basys-3 design. |
`define DELAY_EXT_BUS |
`define DELAY_DBG_BUS |
// On my previous version, I needed to add a delay to access the external |
// bus. Activate the define below and that delay will be put back into place. |
// This particular version no longer needs the delay in order to run at |
// 100 MHz. Timing indicates I may even run this at 250 MHz without the |
// delay too, so we're doing better. To get rid of this, I placed the logic |
// determining whether or not I was accessing the local system bus one clock |
// earlier, or into the memops.v file. This also required my wishbone bus |
// arbiter to maintain the bus selection as well, so that got updated ... |
// you get the picture. But, the bottom line is that I no longer need this |
// delay. |
// |
// `define DELAY_EXT_BUS // Required no longer!k |
// |
// |
// If space is tight, you might not wish to have your performance and |
// accounting counters, so let's make those optional here |
// Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU) |
// When including counters, |
// Slice LUTs ZipSystem ZipCPU |
// With Counters 3315 2432 |
// Without Counters 2796 2046 |
`define INCLUDE_ACCOUNTING_COUNTERS |
|
// |
// Now, where am I placing all of my peripherals? |
`define PERIPHBASE 32'hc0000000 |
`define INTCTRL 4'h0 // |
`define WATCHDOG 4'h1 // Interrupt generates reset signal |
`define CACHECTRL 4'h2 // Sets IVEC[0] |
`define CTRINT 4'h3 // Sets IVEC[5] |
`define TIMER_A 4'h4 // Sets IVEC[4] |
`define TIMER_B 4'h5 // Sets IVEC[3] |
`define TIMER_C 4'h6 // Sets IVEC[2] |
`define JIFFIES 4'h7 // Sets IVEC[1] |
`define INTCTRL 5'h0 // |
`define WATCHDOG 5'h1 // Interrupt generates reset signal |
// `define CACHECTRL 5'h2 // Sets IVEC[0] |
`define CTRINT 5'h3 // Sets IVEC[5] |
`define TIMER_A 5'h4 // Sets IVEC[4] |
`define TIMER_B 5'h5 // Sets IVEC[3] |
`define TIMER_C 5'h6 // Sets IVEC[2] |
`define JIFFIES 5'h7 // Sets IVEC[1] |
|
`define MSTR_TASK_CTR 4'h8 |
`define MSTR_MSTL_CTR 4'h9 |
`define MSTR_PSTL_CTR 4'ha |
`define MSTR_INST_CTR 4'hb |
`define USER_TASK_CTR 4'hc |
`define USER_MSTL_CTR 4'hd |
`define USER_PSTL_CTR 4'he |
`define USER_INST_CTR 4'hf |
|
`define CACHEBASE 16'hc010 // |
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
`define MSTR_TASK_CTR 5'h08 |
`define MSTR_MSTL_CTR 5'h09 |
`define MSTR_PSTL_CTR 5'h0a |
`define MSTR_INST_CTR 5'h0b |
`define USER_TASK_CTR 5'h0c |
`define USER_MSTL_CTR 5'h0d |
`define USER_PSTL_CTR 5'h0e |
`define USER_INST_CTR 5'h0f |
`endif |
|
// Although I have a hole at 5'h2, the DMA controller requires four wishbone |
// addresses, therefore we place it by itself and expand our address bus |
// width here by another bit. |
`define DMAC 5'h10 |
|
// `define RTC_CLOCK 32'hc0000008 // A global something |
// `define BITREV 32'hc0000003 |
// |
126,7 → 154,7
module zipsystem(i_clk, i_rst, |
// Wishbone master interface from the CPU |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, |
// Incoming interrupts |
i_ext_int, |
// Our one outgoing interrupt |
143,6 → 171,7
output wire [31:0] o_wb_data; |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
// Incoming interrupts |
input [(EXTERNAL_INTERRUPTS-1):0] i_ext_int; |
// Outgoing interrupt |
161,11 → 190,13
wire [31:0] dbg_idata, dbg_odata; |
reg dbg_ack; |
`ifdef DELAY_DBG_BUS |
wire dbg_err, no_dbg_err; |
assign dbg_err = 1'b0; |
busdelay #(1,32) wbdelay(i_clk, |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data, |
o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err, |
dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, |
dbg_ack, dbg_stall, dbg_odata); |
dbg_ack, dbg_stall, dbg_odata, dbg_err); |
`else |
assign dbg_cyc = i_dbg_cyc; |
assign dbg_stb = i_dbg_stb; |
181,10 → 212,10
// |
// |
wire sys_cyc, sys_stb, sys_we; |
wire [3:0] sys_addr; |
wire [4:0] sys_addr; |
wire [31:0] cpu_addr; |
wire [31:0] sys_data; |
// wire sys_ack, sys_stall; |
wire sys_ack, sys_stall; |
|
// |
// The external debug interface |
214,7 → 245,7
if (i_rst) |
cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0; |
else if (dbg_cmd_write) |
cmd_halt <= dbg_idata[10]; |
cmd_halt <= ((dbg_idata[10])||(dbg_idata[8])); |
else if ((cmd_step)||(cpu_break)) |
cmd_halt <= 1'b1; |
|
235,7 → 266,7
cmd_addr <= dbg_idata[5:0]; |
|
wire cpu_reset; |
assign cpu_reset = (cmd_reset)||(wdt_reset); |
assign cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst); |
|
wire cpu_halt, cpu_dbg_stall; |
assign cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step)); |
280,26 → 311,13
wdt_ack, wdt_stall, wdt_data, wdt_reset); |
|
// |
// The Flash Cache, a pre-read cache to memory that can be used to |
// create a fast memory access area |
// Position two ... unclaimed / unused |
// |
wire cache_int; |
wire [31:0] cache_data; |
wire cache_stb, cache_ack, cache_stall; |
wire fc_cyc, fc_stb, fc_we, fc_ack, fc_stall; |
wire [31:0] fc_data, fc_addr; |
flashcache #(10) manualcache(i_clk, |
sys_cyc, cache_stb, |
((sys_stb)&&(sys_addr == `CACHECTRL)), |
sys_we, cpu_addr[9:0], sys_data, |
cache_ack, cache_stall, cache_data, |
// Need the outgoing CACHE wishbone bus |
fc_cyc, fc_stb, fc_we, fc_addr, fc_data, |
fc_ack, fc_stall, ext_idata, |
// Cache interrupt, for upon completion |
cache_int); |
|
|
wire cache_stall; |
assign cache_stall = 1'b0; |
reg cache_ack; |
always @(posedge i_clk) |
cache_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02); |
// Counters -- for performance measurement and accounting |
// |
// Here's the stuff we'll be counting .... |
306,6 → 324,7
// |
wire cpu_op_stall, cpu_pf_stall, cpu_i_count; |
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
// |
// The master counters will, in general, not be reset. They'll be used |
// for an overall counter. |
313,7 → 332,7
// Master task counter |
wire mtc_ack, mtc_stall, mtc_int; |
wire [31:0] mtc_data; |
zipcounter mtask_ctr(i_clk, (~cmd_halt), sys_cyc, |
zipcounter mtask_ctr(i_clk, (~cpu_halt), sys_cyc, |
(sys_stb)&&(sys_addr == `MSTR_TASK_CTR), |
sys_we, sys_data, |
mtc_ack, mtc_stall, mtc_data, mtc_int); |
349,7 → 368,7
// User task counter |
wire utc_ack, utc_stall, utc_int; |
wire [31:0] utc_data; |
zipcounter utask_ctr(i_clk,(~cmd_halt), sys_cyc, |
zipcounter utask_ctr(i_clk,(~cpu_halt), sys_cyc, |
(sys_stb)&&(sys_addr == `USER_TASK_CTR), |
sys_we, sys_data, |
utc_ack, utc_stall, utc_data, utc_int); |
393,9 → 412,54
: ((uoc_ack) ? uoc_data |
: ((upc_ack) ? upc_data |
: uic_data))))))); |
`else // INCLUDE_ACCOUNTING_COUNTERS |
reg actr_ack; |
wire actr_stall; |
wire [31:0] actr_data; |
assign actr_stall = 1'b0; |
assign actr_data = 32'h0000; |
|
wire utc_int, uoc_int, upc_int, uic_int; |
wire mtc_int, moc_int, mpc_int, mic_int; |
assign mtc_int = 1'b0; |
assign moc_int = 1'b0; |
assign mpc_int = 1'b0; |
assign mic_int = 1'b0; |
assign utc_int = 1'b0; |
assign uoc_int = 1'b0; |
assign upc_int = 1'b0; |
assign uic_int = 1'b0; |
|
always @(posedge i_clk) |
actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01); |
`endif // INCLUDE_ACCOUNTING_COUNTERS |
|
// |
// The DMA Controller |
// |
wire dmac_int, dmac_stb, dc_err; |
wire [31:0] dmac_data; |
wire dmac_ack, dmac_stall; |
wire dc_cyc, dc_stb, dc_we, dc_ack, dc_stall; |
wire [31:0] dc_data, dc_addr; |
wire cpu_gbl_cyc; |
assign dmac_stb = (sys_stb)&&(sys_addr[4]); |
wbdmac dma_controller(i_clk, |
sys_cyc, dmac_stb, sys_we, |
sys_addr[1:0], sys_data, |
dmac_ack, dmac_stall, dmac_data, |
// Need the outgoing DMAC wishbone bus |
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, |
dc_ack, dc_stall, ext_idata, dc_err, |
// External device interrupts |
{ {(32-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int }, |
// DMAC interrupt, for upon completion |
dmac_int, |
// Whether or not the CPU wants the bus |
cpu_gbl_cyc); |
|
|
`ifdef INCLUDE_ACCOUNTING_COUNTERS |
// |
// Counter Interrupt controller |
// |
410,8 → 474,20
sys_data, ctri_data, ctri_vector, ctri_int); |
always @(posedge i_clk) |
ctri_ack <= ctri_sel; |
assign ctri_stall = 1'b0; |
`else // INCLUDE_ACCOUNTING_COUNTERS |
reg ctri_ack; |
wire ctri_stall, ctri_int; |
wire [31:0] ctri_data; |
assign ctri_stall = 1'b0; |
assign ctri_data = 32'h0000; |
assign ctri_int = 1'b0; |
|
always @(posedge i_clk) |
ctri_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT); |
`endif // INCLUDE_ACCOUNTING_COUNTERS |
|
|
// |
// Timer A |
// |
458,12 → 534,14
wire pic_interrupt; |
wire [(5+EXTERNAL_INTERRUPTS):0] int_vector; |
assign int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int, |
jif_int, cache_int }; |
jif_int, dmac_int }; |
icontrol #(6+EXTERNAL_INTERRUPTS) pic(i_clk, cpu_reset, |
(sys_cyc)&&(sys_stb)&&(sys_we) |
&&(sys_addr==`INTCTRL), |
sys_data, pic_data, |
int_vector, pic_interrupt); |
wire pic_stall; |
assign pic_stall = 1'b0; |
reg pic_ack; |
always @(posedge i_clk) |
pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL); |
471,9 → 549,10
// |
// The CPU itself |
// |
wire cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we; |
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_dbg_we; |
wire [31:0] cpu_data, wb_data; |
wire cpu_ack, cpu_stall; |
wire cpu_ack, cpu_stall, cpu_err; |
wire [31:0] cpu_dbg_data; |
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5]) |
&&(dbg_we)&&(dbg_addr)); |
481,20 → 560,39
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
dbg_idata, cpu_dbg_stall, cpu_dbg_data, |
cpu_dbg_cc, cpu_break, |
cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data, |
cpu_gbl_cyc, cpu_gbl_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_addr, cpu_data, |
cpu_ack, cpu_stall, wb_data, |
cpu_err, |
cpu_op_stall, cpu_pf_stall, cpu_i_count); |
|
// Now, arbitrate the bus ... first for the local peripherals |
assign sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc)); |
assign sys_stb = (cpu_cyc) |
? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000)) |
// For the debugger to have access to the local system bus, the |
// following must be true: |
// (dbg_cyc) The debugger must request the bus |
// (~cpu_lcl_cyc) The CPU cannot be using it (CPU gets priority) |
// (dbg_addr) The debugger must be requesting its data |
// register, not just the control register |
// and one of two other things. Either |
// ((cpu_halt)&&(~cpu_dbg_stall)) the CPU is completely halted, |
// or |
// (~cmd_addr[5]) we are trying to read a CPU register |
// while in motion. Let the user beware that, |
// by not waiting for the CPU to fully halt, |
// his results may not be what he expects. |
// |
wire sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr)) |
&&(((cpu_halt)&&(~cpu_dbg_stall)) |
||(~cmd_addr[5])); |
assign sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc); |
assign sys_stb = (cpu_lcl_cyc) |
? (cpu_lcl_stb) |
: ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5])); |
|
assign sys_we = (cpu_cyc) ? cpu_we : dbg_we; |
assign sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0]; |
assign sys_data= (cpu_cyc) ? cpu_data : dbg_idata; |
assign cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE)); |
assign sys_we = (cpu_lcl_cyc) ? cpu_we : dbg_we; |
assign sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0]; |
assign sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata; |
|
// Return debug response values |
assign dbg_odata = (~dbg_addr)?cmd_data |
501,11 → 599,8
:((~cmd_addr[5])?cpu_dbg_data : wb_data); |
initial dbg_ack = 1'b0; |
always @(posedge i_clk) |
dbg_ack <= (dbg_cyc)&&(dbg_stb)&& |
((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall))); |
assign dbg_stall=(dbg_addr)&&(dbg_cyc) |
&&((cpu_cyc)||((cmd_halt)&&(~cpu_halt)) |
||(cpu_dbg_stall)); |
dbg_ack <= (dbg_cyc)&&(~dbg_stall); |
assign dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr); |
|
// Now for the external wishbone bus |
// Need to arbitrate between the flash cache and the CPU |
512,24 → 607,24
// The way this works, though, the CPU will stall once the flash |
// cache gets access to the bus--the CPU will be stuck until the |
// flash cache is finished with the bus. |
wire ext_cyc, ext_stb, ext_we; |
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall; |
wire ext_cyc, ext_stb, ext_we, ext_err; |
wire cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall, |
cpu_ext_err; |
wire [31:0] ext_addr, ext_odata; |
wbarbiter #(32,32) flashvcpu(i_clk, i_rst, |
fc_addr, fc_data, fc_we, fc_stb, fc_cyc, |
fc_ack, fc_stall, |
cpu_addr, cpu_data, cpu_we, |
((cpu_stb)&&(~sys_stb)&&(~cache_stb)), |
cpu_cyc, cpu_ext_ack, cpu_ext_stall, |
ext_addr, ext_odata, ext_we, ext_stb, |
ext_cyc, ext_ack, ext_stall); |
wbpriarbiter #(32,32) dmacvcpu(i_clk, i_rst, |
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, |
cpu_ext_ack, cpu_ext_stall, cpu_ext_err, |
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, |
dc_ack, dc_stall, dc_err, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, |
ext_ack, ext_stall, ext_err); |
|
`ifdef DELAY_EXT_BUS |
busdelay #(32,32) extbus(i_clk, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, |
ext_ack, ext_stall, ext_idata, |
ext_ack, ext_stall, ext_idata, ext_err, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data); |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err); |
`else |
assign o_wb_cyc = ext_cyc; |
assign o_wb_stb = ext_stb; |
539,6 → 634,7
assign ext_ack = i_wb_ack; |
assign ext_stall = i_wb_stall; |
assign ext_idata = i_wb_data; |
assign ext_err = i_wb_err; |
`endif |
|
wire tmr_ack; |
549,14 → 645,17
:(tmc_ack ? tmc_data |
:jif_data)); |
assign wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data) |
:((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data) |
:((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data) |
:((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data) |
:(ext_idata))); |
|
assign cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall |
| wdt_stall | cache_stall |
| cpu_ext_stall); |
assign cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack); |
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall |
| wdt_stall | ctri_stall | actr_stall |
| pic_stall | dmac_stall | cache_stall); |
assign cpu_stall = (sys_stall)|(cpu_ext_stall); |
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|cache_ack); |
assign cpu_ack = (sys_ack)||(cpu_ext_ack); |
assign cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc); |
|
assign o_ext_int = (cmd_halt) && (~cpu_stall); |
|
/rtl/Makefile
38,13 → 38,14
PRPHD:= peripherals |
AUXD := aux |
VSRC := zipsystem.v \ |
$(PRPHD)/flashcache.v $(PRPHD)/icontrol.v \ |
$(PRPHD)/wbdmac.v $(PRPHD)/icontrol.v \ |
$(PRPHD)/zipcounter.v $(PRPHD)/zipjiffies.v \ |
$(PRPHD)/ziptimer.v $(PRPHD)/ziptrap.v \ |
$(CORED)/zipcpu.v $(CORED)/cpuops.v \ |
$(CORED)/pipefetch.v $(CORED)/prefetch.v \ |
$(CORED)/memops.v \ |
$(AUXD)/busdelay.v $(AUXD)/wbarbiter.v |
$(AUXD)/busdelay.v $(AUXD)/wbarbiter.v \ |
$(AUXD)/wbdblpriarb.v $(AUXD)/wbpriarbiter.v |
|
VOBJ := obj_dir |
|
/rtl/aux/wbpriarbiter.v
0,0 → 1,118
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbpriarbiter.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This is a priority bus arbiter. It allows two separate wishbone |
// masters to connect to the same bus, while also guaranteeing |
// that one master can have the bus with no delay any time the |
// other master is not using the bus. The goal is to eliminate |
// the combinatorial logic required in the other wishbone |
// arbiter, while still guarateeing access time for the priority |
// channel. |
// |
// The core logic works like this: |
// |
// 1. When no one requests the bus, 'A' is granted the bus and |
// guaranteed that any access will go right through. |
// 2. If 'B' requests the bus (asserts cyc), and the bus is idle, |
// then 'B' will be granted the bus. |
// 3. Bus grants last as long as the 'cyc' line is high. |
// 4. Once 'cyc' is dropped, the bus returns to 'A' as the owner. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbpriarbiter(i_clk, i_rst, |
// Bus A |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
// what it would (might) do to the synchronous reset signal, i_rst. |
input i_clk, i_rst; |
// Bus A |
input i_a_cyc, i_a_stb, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc, i_b_stb, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
output wire o_cyc, o_stb, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
input i_ack, i_stall, i_err; |
|
// Go high immediately (new cycle) if ... |
// Previous cycle was low and *someone* is requesting a bus cycle |
// Go low immadiately if ... |
// We were just high and the owner no longer wants the bus |
// WISHBONE Spec recommends no logic between a FF and the o_cyc |
// This violates that spec. (Rec 3.15, p35) |
assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc; |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
if (~i_b_cyc) |
r_a_owner <= 1'b1; |
else if ((i_b_cyc)&&(~i_a_cyc)) |
r_a_owner <= 1'b0; |
|
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb; |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
// low if the particular master doesn't own the bus. |
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (~r_a_owner) ? i_ack : 1'b0; |
|
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (~r_a_owner) ? i_stall : 1'b1; |
|
// |
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
|
endmodule |
|
/rtl/aux/wbarbiter.v
57,11 → 57,11
`define WBA_ALTERNATING |
module wbarbiter(i_clk, i_rst, |
// Bus A |
i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, |
i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, |
i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall); |
o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err); |
// 18 bits will address one GB, 4 bytes at a time. |
// 19 bits will allow the ability to address things other than just |
// the 1GB of memory we are expecting. |
73,11 → 73,12
input [(DW-1):0] i_a_dat, i_b_dat; |
input i_a_we, i_a_stb, i_a_cyc; |
input i_b_we, i_b_stb, i_b_cyc; |
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall; |
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall, |
o_a_err, o_b_err; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire o_we, o_stb, o_cyc; |
input i_ack, i_stall; |
input i_ack, i_stall, i_err; |
|
// All the fancy stuff here is done with the three primary signals: |
// o_cyc |
113,6 → 114,11
wire w_a_owner, w_b_owner; |
`ifdef WBA_ALTERNATING |
reg r_a_last_owner; |
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = (w_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (w_b_owner) ? i_stall : 1'b1; |
|
`endif |
always @(posedge i_clk) |
if (i_rst) |
169,10 → 175,10
assign o_a_ack = (w_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (w_b_owner) ? i_ack : 1'b0; |
|
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = (w_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (w_b_owner) ? i_stall : 1'b1; |
// |
// |
assign o_a_err = (w_a_owner) ? i_err : 1'b0; |
assign o_b_err = (w_b_owner) ? i_err : 1'b0; |
|
endmodule |
|
/rtl/aux/busdelay.v
44,10 → 44,10
module busdelay(i_clk, |
// The input bus |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err, |
// The delayed bus |
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data, |
i_dly_ack, i_dly_stall, i_dly_data); |
i_dly_ack, i_dly_stall, i_dly_data, i_dly_err); |
parameter AW=32, DW=32; |
input i_clk; |
// Input/master bus |
57,6 → 57,7
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(DW-1):0] o_wb_data; |
output wire o_wb_err; |
// Delayed bus |
output reg o_dly_cyc, o_dly_stb, o_dly_we; |
output reg [(AW-1):0] o_dly_addr; |
64,6 → 65,7
input i_dly_ack; |
input i_dly_stall; |
input [(DW-1):0] i_dly_data; |
input i_dly_err; |
|
initial o_dly_cyc = 1'b0; |
initial o_dly_stb = 1'b0; |
91,5 → 93,6
// there's a way to register this? |
// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such? |
assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(o_dly_stb)); |
assign o_wb_err = i_dly_err; |
|
endmodule |
/rtl/aux/wbdblpriarb.v
0,0 → 1,142
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbdblpriarb.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: This should almost be identical to the priority arbiter, save |
// for a simple diffence: it allows the arbitration of two |
// separate wishbone buses. The purpose of this is to push the address |
// resolution back one cycle, so that by the first clock visible to this |
// core, it is known which of two parts of the bus the desired address |
// will be on, save that we still use the arbiter since the underlying |
// device doesn't know that there are two wishbone buses. |
// |
// So at this point we've deviated from the WB spec somewhat, by allowing |
// two CYC and two STB lines. Everything else is the same. This allows |
// (in this case the Zip CPU) to determine whether or not the access |
// will be to the local ZipSystem bus or the external WB bus on the clock |
// before the local bus access, otherwise peripherals were needing to do |
// multiple device selection comparisons/test within a clock: 1) is this |
// for the local or external bus, and 2) is this referencing me as a |
// peripheral. This then caused the ZipCPU to fail all timing specs. |
// By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the |
// determination of local vs external can be made one clock earlier |
// where there's still time for the logic, and the second comparison |
// now has time to complete. |
// |
// So let me try to explain this again. To use this arbiter, one of the |
// two masters sets CYC and STB before, only the master determines which |
// of two address spaces the CYC and STB apply to before the clock and |
// only sets the appropriate CYC and STB lines. Then, on the clock tick, |
// the arbiter determines who gets *both* busses, as they both share every |
// other WB line. Thus, only one of CYC_A and CYC_B going out will ever |
// be high at a given time. |
// |
// Hopefully this makes more sense than it sounds. If not, check out the |
// code below for a better explanation. |
// |
// 20150919 -- Added supported for the WB error signal. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module wbdblpriarb(i_clk, i_rst, |
// Bus A |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, |
i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
// what it would (might) do to the synchronous reset signal, i_rst. |
input i_clk, i_rst; |
// Bus A |
input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
input i_ack, i_stall, i_err; |
|
// All of our logic is really captured in the 'r_a_owner' register. |
// This register determines who owns the bus. If no one is requesting |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// requesting the bus and A is not, then ownership goes to not A on |
// the next clock. (Sounds simple ...) |
// |
// The CYC logic is here to make certain that, by the time we determine |
// who the bus owner is, we can do so based upon determined criteria. |
assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
if (i_rst) |
r_a_owner <= 1'b1; |
else if ((~o_cyc_a)&&(~o_cyc_b)) |
r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1; |
|
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on these various lines are |
// irrelevant. |
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a; |
assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b; |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
// low if the particular master doesn't own the bus. |
assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (~r_a_owner) ? i_ack : 1'b0; |
|
// Stall must be asserted on the same cycle the input master asserts |
// the bus, if the bus isn't granted to him. |
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (~r_a_owner) ? i_stall : 1'b1; |
|
// |
// These error lines will be implemented soon, as soon as the rest of |
// the Zip CPU is ready to support them. |
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
|
endmodule |
|
/rtl/peripherals/wbdmac.v
0,0 → 1,329
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: wbdmac.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Wishbone DMA controller |
// |
// This module is controllable via the wishbone, and moves values from |
// one location in the wishbone address space to another. The amount of |
// memory moved at any given time can be up to 4kB, or equivalently 1kW. |
// Four registers control this DMA controller: a control/status register, |
// a length register, a source WB address and a destination WB address. |
// These register may be read at any time, but they may only be written |
// to when the controller is idle. |
// |
// The meanings of three of the setup registers should be self explanatory: |
// - The length register controls the total number of words to |
// transfer. |
// - The source address register controls where the DMA controller |
// reads from. This address may or may not be incremented |
// after each read, depending upon the setting in the |
// control/status register. |
// - The destination address register, which controls where the DMA |
// controller writes to. This address may or may not be |
// incremented after each write, also depending upon the |
// setting in the control/status register. |
// |
// It is the control/status register, at local address zero, that needs |
// more definition: |
// |
// Bits: |
// 31 R Write protect If this is set to one, it means the |
// write protect bit is set and the controller |
// is therefore idle. This bit will be set upon |
// completing any transfer. |
// 30 R Error. The controller stopped mid-transfer |
// after receiving a bus error. |
// 29 R/W inc_s_n If set to one, the source address |
// will not increment from one read to the next. |
// 28 R/W inc_d_n If set to one, the destination address |
// will not increment from one write to the next. |
// 27 R Always 0 |
// 26..16 R nread Indicates how many words have been read, |
// and not necessarily written (yet). This |
// combined with the cfg_len parameter should tell |
// exactly where the controller is at mid-transfer. |
// 27..16 W WriteProtect When a 12'h3db is written to these |
// bits, the write protect bit will be cleared. |
// |
// 15 R/W on_dev_trigger When set to '1', the controller will |
// wait for an external interrupt before starting. |
// 14..10 R/W device_id This determines which external interrupt |
// will trigger a transfer. |
// 9..0 R/W transfer_len How many bytes to transfer at one time. |
// The minimum transfer length is one, while zero |
// is mapped to a transfer length of 1kW. |
// |
// |
// To use this, follow this checklist: |
// 1. Wait for any prior DMA operation to complete |
// (Read address 0, wait 'till either top bit is set or cfg_len==0) |
// 2. Write values into length, source and destination address. |
// (writei(3, &vals) should be sufficient for this.) |
// 3. Enable the DMAC interrupt in whatever interrupt controller is present |
// on the system. |
// 4. Write the final start command to the setup/control/status register: |
// Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger, |
// appropriately for your task |
// Write 12'h3db to the upper word. |
// Set the lower word to either all zeros, or a smaller transfer |
// length if desired. |
// 5. wait() for the interrupt and the operation to complete. |
// Prior to completion, number of items successfully transferred |
// be read from the length register. If the internal buffer is |
// being used, then you can read how much has been read into that |
// buffer by reading from bits 25..16 of this control/status |
// register. |
// |
// Creator: Dan Gisselquist |
// Gisselquist Tecnology, LLC |
// |
// Copyright: 2015 |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbdmac(i_clk, |
i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data, |
o_swb_ack, o_swb_stall, o_swb_data, |
o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data, |
i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err, |
i_dev_ints, |
o_interrupt, |
i_other_busmaster_requests_bus); |
parameter LGMEMLEN = 10, DW=32, LGDV=5; |
input i_clk; |
// Slave/control wishbone inputs |
input i_swb_cyc, i_swb_stb, i_swb_we; |
input [1:0] i_swb_addr; |
input [(DW-1):0] i_swb_data; |
// Slave/control wishbone outputs |
output reg o_swb_ack; |
output wire o_swb_stall; |
output reg [(DW-1):0] o_swb_data; |
// Master/DMA wishbone control |
output reg o_mwb_cyc, o_mwb_stb, o_mwb_we; |
output reg [(DW-1):0] o_mwb_addr, o_mwb_data; |
// Master/DMA wishbone responses from the bus |
input i_mwb_ack, i_mwb_stall; |
input [(DW-1):0] i_mwb_data; |
input i_mwb_err; |
// The interrupt device interrupt lines |
input [(DW-1):0] i_dev_ints; |
// An interrupt to be set upon completion |
output reg o_interrupt; |
// Need to release the bus for a higher priority user |
input i_other_busmaster_requests_bus; |
|
|
reg cfg_wp; // Write protect |
reg cfg_err; |
reg [(DW-1):0] cfg_waddr, cfg_raddr, cfg_len; |
reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one; |
reg cfg_incs, cfg_incd; |
reg [(LGDV-1):0] cfg_dev_trigger; |
reg cfg_on_dev_trigger; |
|
// Single block operations: We'll read, then write, up to a single |
// memory block here. |
|
reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)]; |
reg [(LGMEMLEN):0] nread, nwritten, nacks; |
wire [(DW-1):0] bus_nacks; |
assign bus_nacks = { {(DW-LGMEMLEN-1){1'b0}}, nacks }; |
|
initial o_interrupt = 1'b0; |
initial o_mwb_cyc = 1'b0; |
initial cfg_err = 1'b0; |
initial cfg_wp = 1'b0; |
initial cfg_len = 32'h00; |
initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}}; |
initial cfg_on_dev_trigger = 1'b0; |
always @(posedge i_clk) |
if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle |
begin |
if ((o_mwb_stb)&&(~i_mwb_stall)) |
begin |
nwritten <= nwritten+1; |
if ((nwritten == nread-1) |
||(i_other_busmaster_requests_bus)) |
// Wishbone interruptus |
o_mwb_stb <= 1'b0; |
else if (cfg_incd) begin |
o_mwb_addr <= o_mwb_addr + 1; |
cfg_waddr <= cfg_waddr + 1; |
end |
// o_mwb_data <= dma_mem[nwritten + 1]; |
end |
|
if (i_mwb_err) |
begin |
o_mwb_cyc <= 1'b0; |
cfg_err <= 1'b1; |
cfg_len <= 0; |
nread <= 0; |
end else if (i_mwb_ack) |
begin |
nacks <= nacks+1; |
cfg_len <= cfg_len - 1; |
if ((nacks+1 == nwritten)&&(~o_mwb_stb)) |
begin |
o_mwb_cyc <= 1'b0; |
nread <= 0; |
o_interrupt <= (cfg_len == 1); |
// Turn write protect back on |
cfg_wp <= 1'b1; |
end |
end |
end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle |
begin |
if ((o_mwb_stb)&&(~i_mwb_stall)) |
begin |
nacks <= nacks+1; |
if ((nacks == {1'b0, cfg_blocklen_sub_one}) |
||(bus_nacks <= cfg_len-1) |
||(i_other_busmaster_requests_bus)) |
// Wishbone interruptus |
o_mwb_stb <= 1'b0; |
else if (cfg_incs) begin |
o_mwb_addr <= o_mwb_addr + 1; |
end |
end |
|
if (i_mwb_err) |
begin |
o_mwb_cyc <= 1'b0; |
cfg_err <= 1'b1; |
cfg_len <= 0; |
nread <= 0; |
end else if (i_mwb_ack) |
begin |
nread <= nread+1; |
if ((~o_mwb_stb)&&(nread+1 == nacks)) |
begin |
o_mwb_cyc <= 1'b0; |
nacks <= 0; |
end |
if (cfg_incs) |
cfg_raddr <= cfg_raddr + 1; |
// dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data; |
end |
end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err)) |
begin // Initiate/continue a write cycle |
o_mwb_cyc <= 1'b1; |
o_mwb_stb <= 1'b1; |
o_mwb_we <= 1'b1; |
// o_mwb_data <= dma_mem[0]; |
o_mwb_addr <= cfg_waddr; |
// nwritten <= 0; // Can't set to zero, in case we're |
// nacks <= 0; // continuing a cycle |
end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp) |
&&((~cfg_on_dev_trigger) |
||(i_dev_ints[cfg_dev_trigger]))) |
begin // Initiate a read cycle |
o_mwb_cyc <= 1'b1; |
o_mwb_stb <= 1'b1; |
o_mwb_we <= 1'b0; |
o_mwb_addr<= cfg_raddr; |
nwritten <= 0; |
nread <= 0; |
nacks <= 0; |
end else begin |
o_mwb_cyc <= 1'b0; |
o_mwb_stb <= 1'b0; |
o_mwb_we <= 1'b0; |
o_mwb_addr <= cfg_raddr; |
o_interrupt<= 1'b0; |
nwritten <= 0; |
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)) |
begin |
cfg_wp <= 1'b1; |
case(i_swb_addr) |
2'b00: begin |
cfg_wp <= (i_swb_data[27:16]!=12'hfed); |
cfg_blocklen_sub_one |
<= i_swb_data[(LGMEMLEN-1):0]-1; |
cfg_dev_trigger <= i_swb_data[14:10]; |
cfg_on_dev_trigger <= i_swb_data[15]; |
cfg_incs <= ~i_swb_data[29]; |
cfg_incd <= ~i_swb_data[28]; |
cfg_err <= 1'b0; |
end |
2'b01: cfg_len <= i_swb_data; |
2'b10: cfg_raddr <= i_swb_data; |
2'b11: cfg_waddr <= i_swb_data; |
endcase |
end |
end |
|
// |
// This is tricky. In order for Vivado to consider dma_mem to be a |
// proper memory, it must have a simple address fed into it. Hence |
// the read_address (rdaddr) register. The problem is that this |
// register must always be one greater than the address we actually |
// want to read from, unless we are idling. So ... the math is touchy. |
// |
reg [(LGMEMLEN-1):0] rdaddr; |
always @(posedge i_clk) |
if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)) |
// This would be the normal advance, save that we are |
// already one ahead of nwritten |
rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1}; |
else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err)) |
// Here's where we do our extra advance |
rdaddr <= nwritten[(LGMEMLEN-1):0]+1; |
else if ((~o_mwb_cyc)||(~o_mwb_we)) |
rdaddr <= nwritten[(LGMEMLEN-1):0]; |
always @(posedge i_clk) |
if ((~o_mwb_cyc)||((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))) |
o_mwb_data <= dma_mem[rdaddr]; |
always @(posedge i_clk) |
if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack)) |
dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data; |
|
always @(posedge i_clk) |
casez(i_swb_addr) |
2'b00: o_swb_data <= { ~cfg_wp, cfg_err, |
~cfg_incs, ~cfg_incd, |
1'b0, nread, |
cfg_on_dev_trigger, cfg_dev_trigger, |
cfg_blocklen_sub_one |
}; |
2'b01: o_swb_data <= cfg_len; |
2'b10: o_swb_data <= cfg_raddr; |
2'b11: o_swb_data <= cfg_waddr; |
endcase |
|
always @(posedge i_clk) |
if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we)) |
o_swb_ack <= 1'b1; |
// else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0)) |
else |
o_swb_ack <= 1'b0; |
|
assign o_swb_stall = 1'b0; |
|
endmodule |
|
/rtl/peripherals/zipport.v
0,0 → 1,129
/////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipport.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: A communications port for passing data between CPU's in a |
// multi-cpu system. |
// |
// Example: Imagine a signal processing system with many 'CPUs' working |
// together. Each communicates its outputs to the next CPU. |
// Writes to this port will send values to the next port over, |
// and reads from this port will read such values. |
// |
// These ports are ripe for adding FIFO's too, but the port |
// itself doesn't offer a FIFO. Worse, as written, the port |
// offers no flags to a FIFO to know when to read the next |
// value. |
// |
// Note: There are other means of message passing, this is just |
// one--perhaps not even the best one. |
// |
// Interface: |
// 2-bits of control: |
// top bit means valid data that hasn't been read. |
// next bit means data has not been read, but instead has been |
// lost |
// These statuses are cleared upon any read. |
// 30-bits of data. |
// |
// External CPU: |
// Can read/write to the port. |
// Writes to the port take place by setting i_port_v and strobing i_port_w. |
// Writes from this port to other ports take place the same way. |
// Reads/writes to/from this port by the CPU take place via the single |
// wishbone address. |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Tecnology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
module zipport(i_clk, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
i_port_w, i_port_v, |
o_port_w, o_port_v, |
o_int_full, o_int_ovflw); |
parameter BW = 32, DW = (BW-2); |
input i_clk; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(BW-1):0] i_wb_data; |
// Wishbone outputs |
output reg o_wb_ack; |
output wire o_wb_stall; |
output wire [(BW-1):0] o_wb_data; |
// Port connections |
input i_port_w; // Write strobe |
input [(DW-1):0] i_port_v; // Value received |
output reg o_port_w; // Writing strobe |
output reg [(BW-1):0] o_port_v; // Value being sent |
// Interrupt line |
output wire o_int_full, o_int_ovflw; |
|
wire wb_write, wb_read, wb_cycle; |
assign wb_write = (i_wb_cyc)&&(i_wb_stb)&&(i_wb_we); |
assign wb_read = (i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we); |
assign wb_cycle = (i_wb_cyc)&&(i_wb_stb); |
|
reg r_valid, r_ovflw; |
reg [(DW-1):0] r_data; |
|
initial r_valid = 1'b0; |
initial r_ovflw = 1'b0; |
always @(posedge i_clk) |
if (wb_write) |
begin |
o_port_w <= 1'b1; |
o_port_v <= i_wb_data; |
end else |
o_port_w <= 1'b0; |
|
always @(posedge i_clk) |
if (i_port_w) |
r_valid <= 1'b1; |
else if (wb_read) |
r_valid <= 1'b0; |
|
always @(posedge i_clk) |
if (i_port_w) |
r_ovflw <= (r_valid); |
else if (wb_read) |
r_ovflw <= 1'b0; |
|
always @(posedge i_clk) |
if (i_port_w) |
r_data <= i_port_v; |
|
assign o_int_full = r_valid; |
assign o_int_ovflw= r_ovflw; |
|
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= wb_cycle; |
assign o_wb_stall = 1'b0; |
|
assign o_wb_data = { r_valid, r_ovflw, {(BW-2-DW){1'b0}}, r_data }; |
|
endmodule |
/doc/spec.pdf
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/doc/gfx/zippipe.dia
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doc/gfx/zippipe.dia
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## -0,0 +1 ##
+application/octet-stream
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Index: doc/src/spec.tex
===================================================================
--- doc/src/spec.tex (revision 35)
+++ doc/src/spec.tex (revision 36)
@@ -48,7 +48,13 @@
\title{Specification}
\author{Dan Gisselquist, Ph.D.}
\email{dgisselq (at) opencores.org}
-\revision{Rev.~0.3}
+\revision{Rev.~0.4}
+\definecolor{webred}{rgb}{0.2,0,0}
+\definecolor{webgreen}{rgb}{0,0.2,0}
+\usepackage[dvips,ps2pdf,colorlinks=true,
+ anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames,
+ pdfauthor={Dan Gisselquist},
+ pdfsubject={Zip CPU}]{hyperref}
\begin{document}
\pagestyle{gqtekspecplain}
\titlepage
@@ -70,6 +76,7 @@
copy.
\end{license}
\begin{revisionhistory}
+0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline
0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline
@@ -89,13 +96,16 @@
There's more to it, though. There's a lot that I would like to do with a
processor, and I want to be able to do it in a vendor independent fashion.
-I would like to be able to generate Verilog code that can run equivalently
-on both Xilinx and Altera chips, and that can be easily ported from one
-manufacturer's chipsets to another. Even more, before purchasing a chip or a
-board, I would like to know that my soft core works. I would like to build a test
-bench to test components with, and Verilator is my chosen test bench. This
-forces me to use all Verilog, and it prevents me from using any proprietary
-cores. For this reason, Microblaze and Nios are out of the question.
+First, I would like to be able to place this processor inside an FPGA. Without
+paying royalties, ARM is out of the question. I would then like to be able to
+generate Verilog code, both for the processor and the system it sits within,
+that can run equivalently on both Xilinx and Altera chips, and that can be
+easily ported from one manufacturer's chipsets to another. Even more, before
+purchasing a chip or a board, I would like to know that my soft core works. I
+would like to build a test bench to test components with, and Verilator is my
+chosen test bench. This forces me to use all Verilog, and it prevents me from
+using any proprietary cores. For this reason, Microblaze and Nios are out of
+the question.
Why not OpenRISC? That's a hard question. The OpenRISC team has done some
wonderful work on an amazing processor, and I'll have to admit that I am
@@ -122,7 +132,7 @@
\setcounter{page}{1}
-The original goal of the ZIP CPU was to be a very simple CPU. You might
+The original goal of the Zip CPU was to be a very simple CPU. You might
think of it as a poor man's alternative to the OpenRISC architecture.
For this reason, all instructions have been designed to be as simple as
possible, and are all designed to be executed in one instruction cycle per
@@ -297,7 +307,7 @@
\section{Simplified Bus}
The bus architecture of the Zip CPU is that of a simplified WISHBONE bus.
It has been simplified in this fashion: all operations are 32--bit operations.
-The bus is neither little endian nor bit endian. For this reason, all words
+The bus is neither little endian nor big endian. For this reason, all words
are 32--bits. All instructions are also 32--bits wide. Everything has been
built around the 32--bit word.
@@ -318,9 +328,28 @@
The CPU can access both register sets via move instructions from the
supervisor state, whereas the user state can only access the user registers.
-The status register is special, and bears further mention. The lower
-10 bits of the status register form a set of CPU state and condition codes.
-Writes to other bits of this register are preserved.
+The status register is special, and bears further mention. As shown in
+Fig.~\ref{tbl:cc-register},
+\begin{table}\begin{center}
+\begin{bitlist}
+31\ldots 11 & R/W & Reserved for future uses\\\hline
+10 & R & (Reserved for) Bus-Error Flag\\\hline
+9 & R & Trap, or user interrupt, Flag. Cleared on return to userspace.\\\hline
+8 & R & (Reserved for) Illegal Instruction Flag\\\hline
+7 & R/W & Break--Enable\\\hline
+6 & R/W & Step\\\hline
+5 & R/W & Global Interrupt Enable (GIE)\\\hline
+4 & R/W & Sleep. When GIE is also set, the CPU waits for an interrupt.\\\hline
+3 & R/W & Overflow\\\hline
+2 & R/W & Negative. The sign bit was set as a result of the last ALU instruction.\\\hline
+1 & R/W & Carry\\\hline
+0 & R/W & Zero. The last ALU operation produced a zero.\\\hline
+\end{bitlist}
+\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
+\end{center}\end{table}
+the lower 11~bits of the status register form
+a set of CPU state and condition codes. Writes to other bits of this register
+are preserved.
Of the condition codes, the bottom four bits are the current flags:
Zero (Z),
@@ -371,13 +400,11 @@
This functionality was added to enable an external debugger to
set and manage breakpoints.
-The ninth bit is reserved for a floating point enable bit. When set, the
-arithmetic for the next instruction will be sent to a floating point unit.
-Such a unit may later be added as an extension to the Zip CPU. If the
-CPU does not support floating point instructions, this bit will never be set.
-The instruction set could also be simply extended to allow other data types
-in this fashion, such as two by 16--bit vector operations or four by 8--bit
-vector operations.
+The ninth bit is reserved for an illegal instruction bit. When the CPU
+tries to execute either a non-existant instruction, or an instruction from
+an address that produces a bus error, the CPU will (once implemented) switch
+to supervisor mode while setting this bit. The bit will automatically be
+cleared upon any return to user mode.
The tenth bit is a trap bit. It is set whenever the user requests a soft
interrupt, and cleared on any return to userspace command. This allows the
@@ -404,7 +431,7 @@
\end{center}\end{table}
\section{Conditional Instructions}
-Most, although not quite all, instructions are conditionally executed. From
+Most, although not quite all, instructions may be conditionally executed. From
the four condition code flags, eight conditions are defined. These are shown
in Tbl.~\ref{tbl:conditions}.
\begin{table}
@@ -424,9 +451,12 @@
\end{center}
\end{table}
There is no condition code for less than or equal, not C or not V. Sorry,
-I ran out of space in 3--bits. Using these conditions will take an extra
-instruction and a pipeline stall. (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})
+I ran out of space in 3--bits. Conditioning on a non--supported condition
+is still possible, but it will take an extra instruction and a pipeline stall. (Ex: \hbox{\em (Stall)}; \hbox{\tt TST \$4,CC;} \hbox{\tt STO.NZ R0,(R1)})
+Conditionally executed ALU instructions will not further adjust the
+condition codes.
+
\section{Operand B}
Many instruction forms have a 21-bit source ``Operand B'' associated with them.
This Operand B is either equal to a register plus a signed immediate offset,
@@ -448,7 +478,7 @@
instruction possibilities.
\section{Address Modes}
-The ZIP CPU supports two addressing modes: register plus immediate, and
+The Zip CPU supports two addressing modes: register plus immediate, and
immediate address. Addresses are therefore encoded in the same fashion as
Operand B's, shown above.
@@ -484,12 +514,11 @@
all MOV registers are supervisor registers, and display them as normal.
Anything with the user bit set will be treated as a user register. The CPU
will quietly ignore the supervisor bits while in user mode, and anything
-marked as a user register will always be valid. (Did I just say that in the
-last paragraph?)
+marked as a user register will always be valid.
\section{Multiply Operations}
-The Zip CPU supports two Multiply operations, a
-16x16 bit signed multiply (MPYS) and the same but unsigned (MPYU). In both
+The Zip CPU supports two Multiply operations, a 16x16 bit signed multiply
+({\tt MPYS}) and a 16x16 bit unsigned multiply ({\tt MPYU}). In both
cases, the operand is a register plus a 16-bit immediate, subject to the
rule that the register cannot be the PC or CC registers. The PC register
field has been stolen to create a multiply by immediate instruction. The
@@ -496,13 +525,14 @@
CC register field is reserved.
\section{Floating Point}
-The ZIP CPU does not support floating point operations. However, the
+The Zip CPU does not (yet) support floating point operations. However, the
instruction set reserves two possibilities for future floating point
operations.
The first floating point operation hole in the instruction set involves
-setting the floating point bit in the CC register. The next instruction
-will simply interpret its operands as floating point instructions.
+setting a proposed (but non-existent) floating point bit in the CC register.
+The next instruction
+would then simply interpret its operands as floating point instructions.
Not all instructions, however, have floating point equivalents. Further, the
immediate fields do not apply in floating point mode, and must be set to
zero. Not all instructions make sense as floating point operations.
@@ -513,15 +543,15 @@
The other possibility for floating point operations involves exploiting the
hole in the instruction set that the NOOP and BREAK instructions reside within.
-These two instructions use 24--bits of address space. A simple adjustment
-to this space could create instructions with 4--bit register addresses for
-each register, a 3--bit field for conditional execution, and a 2--bit field
-for which operation. In this fashion, such a floating point capability would
-only fill 13--bits of the 24--bit field, still leaving lots of room for
-expansion.
+These two instructions use 24--bits of address space, when only a single bit
+is necessary. A simple adjustment to this space could create instructions
+with 4--bit register addresses for each register, a 3--bit field for
+conditional execution, and a 2--bit field for which operation.
+In this fashion, such a floating point capability would only fill 13--bits of
+the 24--bit field, still leaving lots of room for expansion.
In both cases, the Zip CPU would support 32--bit single precision floats
-only.
+only, since other choices would complicate the pipeline.
The current architecture does not support a floating point not-implemented
interrupt. Any soft floating point emulation must be done deliberately.
@@ -531,9 +561,10 @@
Tbl.~\ref{tbl:zip-instructions}.
\begin{table}\begin{center}
\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline
+\rowcolor[gray]{0.85}
Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}
& \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}
- & Sets CC? \\\hline
+ & Sets CC? \\\hline\hline
CMP(Sub) & \multicolumn{4}{l|}{4'h0}
& \multicolumn{4}{l|}{D. Reg}
& \multicolumn{3}{l|}{Cond.}
@@ -564,7 +595,7 @@
& \multicolumn{4}{l|}{4'he}
& \multicolumn{24}{l|}{24'h01}
& \\\hline
-{\em Rsrd} & \multicolumn{4}{l|}{4'h4}
+{\em Reserved} & \multicolumn{4}{l|}{4'h4}
& \multicolumn{4}{l|}{4'he}
& \multicolumn{24}{l|}{24'bits, but not 0 or 1.}
& \\\hline
@@ -667,22 +698,22 @@
As you can see, there's lots of room for instruction set expansion. The
NOOP and BREAK instructions are the only instructions within one particular
-24--bit hole. This spaces are reserved for future enhancements. For example,
-floating point operations, consisting of a 3-bit floating point operation,
-two 4-bit registers, no immediate offset, and a 3-bit condition would fit
-nicely into 14--bits of this address space--making it so that the floating
-point bit in the CC register need not be used.
+24--bit hole. The rest of this space is reserved for future enhancements.
\section{Derived Instructions}
-The ZIP CPU supports many other common instructions, but not all of them
+The Zip CPU supports many other common instructions, but not all of them
are single cycle instructions. The derived instruction tables,
-Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, and~\ref{tbl:derived-3},
+Tbls.~\ref{tbl:derived-1}, \ref{tbl:derived-2}, \ref{tbl:derived-3}
+and~\ref{tbl:derived-4},
help to capture some of how these other instructions may be implemented on
-the ZIP CPU. Many of these instructions will have assembly equivalents,
+the Zip CPU. Many of these instructions will have assembly equivalents,
such as the branch instructions, to facilitate working with the CPU.
\begin{table}\begin{center}
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
Mapped & Actual & Notes \\\hline
+ABS Rx
+ & \parbox[t]{1.5in}{TST -1,Rx\\NEG.LT Rx}
+ & Absolute value, depends upon derived NEG.\\\hline
\parbox[t]{1.4in}{ADD Ra,Rx\\ADDC Rb,Ry}
& \parbox[t]{1.5in}{Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
& Add with carry \\\hline
@@ -730,7 +761,11 @@
MOV \$Addr+PC,PC \\
ADD \$1,SP}
& Jump to Subroutine. Note the required cleanup instruction after
- returning. \\\hline
+ returning. This could easily be turned into a three instruction
+ operand, removing the preliminary stack instruction before and
+ the cleanup after, by adjusting how any stack frame was built for
+ this routine to include space at the top of the stack for the PC.
+ \\\hline
JSR PC+\$Addr
& \parbox[t]{1.5in}{MOV \$3+PC,R12 \\ MOV \$addr+PC,PC}
&This is the high speed
@@ -789,6 +824,7 @@
OR Rz,Rx}
& Logical shift right with carry \\\hline
NEG Rx & \parbox[t]{1.5in}{XOR \$-1,Rx \\ ADD \$1,Rx} & \\\hline
+NEG.C Rx & \parbox[t]{1.5in}{MOV.C \$-1+Rx,Rx\\XOR.C \$-1,Rx} & \\\hline
NOOP & NOOP & While there are many
operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these
operations have consequences in that they might stall the bus if
@@ -802,10 +838,24 @@
(SP). Hence you read from it, then increment it, lest having
incremented it first something then comes along and writes to that
value before you can read the result. \\\hline
+\end{tabular}
+\caption{Derived Instructions, continued}\label{tbl:derived-2}
+\end{center}\end{table}
+\begin{table}\begin{center}
+\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
PUSH Rx
& \parbox[t]{1.5in}{SUB \$1,SP \\
STO Rx,\$1(SP)}
& \\\hline
+PUSH Rx-Ry
+ & \parbox[t]{1.5in}{SUB \$n,SP \\
+ STO Rx,\$n(SP)
+ \ldots \\
+ STO Ry,\$1(SP)}
+ & Multiple pushes at once only need the single subtract from the
+ stack pointer. This derived instruction is analogous to a similar one
+ on the Motoroloa 68k architecture, although the Zip Assembler
+ does not support this instruction (yet).\\\hline
RESET
& \parbox[t]{1in}{STO \$1,\$watchdog(R12)\\NOOP\\NOOP}
& \parbox[t]{3in}{This depends upon the peripheral base address being
@@ -813,14 +863,9 @@
Another opportunity might be to jump to the reset address from within
supervisor mode.}\\\hline
-RET & \parbox[t]{1.5in}{LOD \$-1(SP),PC}
+RET & \parbox[t]{1.5in}{LOD \$1(SP),PC}
& Note that this depends upon the calling context to clean up the
stack, as outlined for the JSR instruction. \\\hline
-\end{tabular}
-\caption{Derived Instructions, continued}\label{tbl:derived-2}
-\end{center}\end{table}
-\begin{table}\begin{center}
-\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
RET & MOV R12,PC
& This is the high(er) speed version, that doesn't touch the stack.
As such, it doesn't suffer a stall on memory read/write to the stack.
@@ -859,14 +904,19 @@
& While no extra registers are needed, this example
does take 3-clocks. \\\hline
TRAP \#X
- & LDILO \$x,CC
- & This approach uses the unused bits of the CC register as a TRAP
- address. The user will need to make certain
- that the SLEEP and GIE bits are not set in \$x. LDI would also work,
- however using LDILO permits the use of conditional traps. (i.e.,
- trap if the zero flag is set.) Should you wish to trap off of a
- register value, you could equivalently load \$x into the register and
- then MOV it into the CC register. \\\hline
+ & \parbox[t]{1.5in}{LDI \$x,R0 \\ AND ~\$GIE,CC }
+ & This works because whenever a user lowers the \$GIE flag, it sets
+ a TRAP bit within the CC register. Therefore, upon entering the
+ supervisor state, the CPU only need check this bit to know that it
+ got there via a TRAP. The trap could be made conditional by making
+ the LDI and the AND conditional. In that case, the assembler would
+ quietly turn the LDI instruction into an LDILO and LDIHI pair,
+ but the effectt would be the same. \\\hline
+\end{tabular}
+\caption{Derived Instructions, continued}\label{tbl:derived-3}
+\end{center}\end{table}
+\begin{table}\begin{center}
+\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
TST Rx
& TST \$-1,Rx
& Set the condition codes based upon Rx. Could also do a CMP \$0,Rx,
@@ -878,20 +928,36 @@
& Wait 'til interrupt. In an interrupts disabled context, this
becomes a HALT instruction.
\end{tabular}
-\caption{Derived Instructions, continued}\label{tbl:derived-3}
+\caption{Derived Instructions, continued}\label{tbl:derived-4}
\end{center}\end{table}
-\iffalse
-\fi
\section{Pipeline Stages}
As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},
the Zip CPU supports a five stage pipeline.
\begin{enumerate}
-\item {\bf Prefetch}: Read instruction from memory (cache if possible). This
+\item {\bf Prefetch}: Reads instruction from memory and into a cache, if so
+ configured. This
stage is actually pipelined itself, and so it will stall if the PC
ever changes. Stalls are also created here if the instruction isn't
in the prefetch cache.
-\item {\bf Decode}: Decode instruction into op code, register(s) to read, and
- immediate offset. This stage also determines whether the flags will
+
+ The Zip CPU supports one of two prefetch methods, depending upon a flag
+ set at build time within the {\tt zipcpu.v} file. The simplest is a
+ non--cached implementation of a prefetch. This implementation is
+ fairly small, and ideal for
+ users of the Zip CPU who need the extra space on the FPGA fabric.
+ However, because this non--cached version has no cache, the maximum
+ number of instructions per clock is limited to about one per five.
+
+ The second prefetch module is a pipelined prefetch with a cache. This
+ module tries to keep the instruction address within a window of valid
+ instruction addresses. While effective, it is not a traditional
+ cache implementation. One unique feature of this cache implementation,
+ however, is that it can be cleared in a single clock. A disappointing
+ feature, though, was that it needs an extra internal pipeline stage
+ to be implemented.
+
+\item {\bf Decode}: Decodes an instruction into op code, register(s) to read,
+ and immediate offset. This stage also determines whether the flags will
be set or whether the result will be written back.
\item {\bf Read Operands}: Read registers and apply any immediate values to
them. There is no means of detecting or flagging arithmetic overflow
@@ -898,164 +964,26 @@
or carry when adding the immediate to the operand. This stage will
stall if any source operand is pending.
\item Split into two tracks: An {\bf ALU} which will accomplish a simple
- instruction, and the {\bf MemOps} stage which accomplishes memory
- read/write.
+ instruction, and the {\bf MemOps} stage which handles {\tt LOD} (load)
+ and {\tt STO} (store) instructions.
\begin{itemize}
- \item Loads stall instructions that access the register until it is
- written to the register set.
- \item Condition codes are available upon completion
- \item Issuing an instruction to the memory while the memory is busy will
- stall the entire pipeline. If the bus deadlocks, only a reset
- will release the CPU. (Watchdog timer, anyone?)
+ \item Loads will stall the entire pipeline until complete.
+ \item Condition codes are available upon completion of the ALU stage
+ \item Issuing an instruction to the memory unit while the memory unit
+ is busy will stall the entire pipeline. If the bus deadlocks,
+ only a reset will release the CPU. (Watchdog timer, anyone?)
\item The Zip CPU currently has no means of reading and acting on any
error conditions on the bus.
\end{itemize}
\item {\bf Write-Back}: Conditionally write back the result to the register
- set, applying the condition. This routine is bi-re-entrant: either the
+ set, applying the condition. This routine is bi-entrant: either the
memory or the simple instruction may request a register write.
\end{enumerate}
The Zip CPU does not support out of order execution. Therefore, if the memory
unit stalls, every other instruction stalls. Memory stores, however, can take
-place concurrently with ALU operations, although memory reads cannot.
+place concurrently with ALU operations, although memory reads (loads) cannot.
-\iffalse
-
-\section{Pipeline Logic}
-How the CPU handles some instruction combinations can be telling when
-determining what happens in the pipeline. The following lists some examples:
-\begin{itemize}
-\item {\bf Delayed Branching}
-
- I had originally hoped to implement delayed branching. My goal
- was that the compiler would handle any pipeline stall conditions so
- that the pipeline logic could be simpler within the CPU. I ran into
- two problems with this.
-
- The first problem has to deal with debug mode. When the debugger
- single steps an instruction, that instruction goes to completion.
- This means that if the instruction moves a value to the PC register,
- the PC register would now contain that value, indicating that the
- next instruction would be on the other side of the branch. There's
- just no easy way around this: the entire CPU state must be captured
- by the registers, to include the program counter. What value should
- the program counter be equal to? The branch? Fine. The address
- you are branching to? Fine. The address of the delay slot? Problem.
-
- The second problem with delayed branching is the idea of suspending
- processing for an interrupt. Which address should the CPU return
- to upon completing the interrupt processing? The branch? Good. The
- address after the branch? Also good. The address of the delay slot?
- Not so good.
-
- If you then add into this mess the idea that, if the CPU is running
- from a really slow memory such as the flash, the delay slot may never
- be filled before the branch is determined, then this makes even less
- sense.
-
- For all of these reasons, this CPU does not support delayed branching.
-
-\item {\bf Register Result:} {\tt MOV R0,R1; MOV R1,R2 }
-
- What value does R2 get, the value of R1 before the first move or the
- value of R0? The Zip CPU has been optimized so that neither of these
- instructions require a pipeline stall--unless an immediate were to
- be added to R1 in the second instruction.
-
- The ZIP CPU architecture requires that R2 must equal R0 at the end of
- this operation. Even better, such combinations do not (normally)
- stall the pipeline.
-
-\item {\bf Condition Codes Result:} {\tt CMP R0,R1;} {\tt MOV.EQ \$x,PC}
-
- At issue is the same item as above, save that the CMP instruction
- updates the flags that the MOV instruction depends upon.
-
- The Zip CPU architecture requires that condition codes must be updated
- and available immediately for the next instruction without stalling the
- pipeline.
-
-\item {\bf Condition Codes Register Result:} {\tt CMP R0,R1; MOV CC,R2}
-
- At issue is the
- fact that the logic supporting the CC register is more complicated than
- the logic supporting any other register.
-
- The ZIP CPU will stall for a cycle cycle on this instruction.
-\item {\bf Condition Codes Register Operand:} {\tt MOV R0,R1; MOV CC,R2}
-
- Unlike the previous case, this move prior to reading the {\tt CC}
- register does not impact the {\tt CC} register. Therefore, this
- does not stall the bus, whereas the previous one would.
-\end{itemize}
-
-As I've studied this, I find several approaches to handling pipeline
- issues. These approaches (and their consequences) are listed below.
-
-\begin{itemize}
-\item {\bf All issued instructions complete, stages stall individually}
-
- What about a slow pre-fetch?
-
- Nominally, this works well: any issued instruction
- just runs to completion. If there are four issued instructions in the
- pipeline, with the writeback instruction being a write-to-PC
- instruction, the other three instructions naturally finish.
-
- This approach fails when reading instructions from the flash,
- since such reads require N clocks to clocks to complete. Thus
- there may be only one instruction in the pipeline if reading from flash,
- or a full pipeline if reading from cache. Each of these approaches
- would produce a different response.
-
- For this reason, the Zip CPU works off of a different basis: All
- instructions that enter either the ALU or the memory unit will
- complete. Stages still stall individually.
-
-\item {\bf Issued instructions may be canceled}
-
- The problem here is that
- memory operations cannot be canceled: even reads may have side effects
- on peripherals that cannot be canceled later. Further, in the case of
- an interrupt, it's difficult to know what to cancel. What happens in
- a \hbox{\tt MOV.C \$x,PC} followed by a \hbox{\tt MOV \$y,PC}
- instruction? Which get canceled?
-
- Because it isn't clear what would need to be canceled, the Zip CPU
- will not permit this combination. A MOV to the PC register will be
- followed by a stall, and possibly many stalls, so that the second
- move to PC will never be executed.
-
-\item {\bf All issued instructions complete.}
-
- In this example, we try all issued instructions complete, but the
- entire pipeline stalls if one stage is not filled. In this approach,
- though, we again struggle with the problems associated with
- delayed branching. Upon attempting to restart the processor, where
- do you restart it from?
-
-\item {\bf Memory instructions must complete}
-
- All instructions that enter into the memory module {\em must}
- complete. Issued instructions from the prefetch, decode, or operand
- read stages may or may not complete. Jumps into code must be valid,
- so that interrupt returns may be valid. All instructions entering the
- ALU complete.
-
- This looks to be the simplest approach.
- While the logic may be difficult, this appears to be the only
- re-entrant approach.
-
- A {\tt new\_pc} flag will be high anytime the PC changes in an
- unpredictable way (i.e., it doesn't increment). This includes jumps
- as well as interrupts and interrupt returns. Whenever this flag may
- go high, memory operations and ALU operations will stall until the
- result is known. When the flag does go high, anything in the prefetch,
- decode, and read-op stage will be invalidated.
-
-\end{itemize}
-\fi
-
\section{Pipeline Stalls}
The processing pipeline can and will stall for a variety of reasons. Some of
these are obvious, some less so. These reasons are listed below:
@@ -1062,20 +990,23 @@
\begin{itemize}
\item When the prefetch cache is exhausted
-This should be obvious. If the prefetch cache doesn't have the instruction
-in memory, the entire pipeline must stall until enough of the prefetch cache
-is loaded to support the next instruction.
+This reason should be obvious. If the prefetch cache doesn't have the
+instruction in memory, the entire pipeline must stall until enough of the
+prefetch cache is loaded to support the next instruction.
\item While waiting for the pipeline to load following any taken branch, jump,
- return from interrupt or switch to interrupt context (6 clocks)
+ return from interrupt or switch to interrupt context (5 stall cycles)
If the PC suddenly changes, the pipeline is subsequently cleared and needs to
be reloaded. Given that there are five stages to the pipeline, that accounts
-for five of the six delay clocks. The last clock is lost in the prefetch
+for four of the five stalls. The stall cycle is lost in the pipelined prefetch
stage which needs at least one clock with a valid PC before it can produce
-a new output. Hence, six clocks will always be lost anytime the pipeline needs
-to be cleared.
+a new output.
+The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and
+{\tt LDI \$X,PC} instructions specially, however. These instructions, when
+not conditioned on the flags, can execute with only 3~stall cycles.
+
\item When reading from a prior register while also adding an immediate offset
\begin{enumerate}
\item\ {\tt OPCODE ?,RA}
@@ -1088,12 +1019,15 @@
any instruction that will write back an operand must be separated from the
opcode that will read and apply an immediate offset by one instruction. The
good news is that this stall can easily be mitigated by proper scheduling.
+That is, any instruction that does not add an immediate to {\tt RA} may be
+scheduled into the stall slot.
-\item When writing to the CC or PC Register
+\item When any write to either the CC or PC Register is followed by a memory
+ operation
\begin{enumerate}
\item\ {\tt OPCODE RA,PC} {\em Ex: a branch opcode}
\item\ {\em (stall, even if jump not taken)}
-\item\ {\tt OPCODE RA,RB}
+\item\ {\tt LOD \$X(RA),RB}
\end{enumerate}
Since branches take place in the writeback stage, the Zip CPU will stall the
pipeline for one clock anytime there may be a possible jump. This prevents
@@ -1100,12 +1034,14 @@
an instruction from executing a memory access after the jump but before the
jump is recognized.
-This stall cannot be mitigated through scheduling.
+This stall may be mitigated by shuffling the operations immediately following
+a potential branch so that an ALU operation follows the branch instead of a
+memory operation.
\item When reading from the CC register after setting the flags
\begin{enumerate}
-\item\ {\tt ALUOP RA,RB}
-\item\ {\em (stall}
+\item\ {\tt ALUOP RA,RB} {\em Ex: a compare opcode}
+\item\ {\em (stall)}
\item\ {\tt TST sys.ccv,CC}
\item\ {\tt BZ somewhere}
\end{enumerate}
@@ -1122,16 +1058,16 @@
that references the CC register. For example, {\tt MOV \$addr+PC,uPC}
followed by an {\tt RTU} ({\tt OR \$GIE,CC}) instruction will not incur
this stall, whereas an {\tt OR \$BREAKEN,CC} followed by an {\tt OR \$STEP,CC}
-will incur the stall.
+will incur the stall, while a {\tt LDI \$BREAKEN|\$STEP,CC} will not.
\item When waiting for a memory read operation to complete
\begin{enumerate}
\item\ {\tt LOD address,RA}
-\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
+\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
\item\ {\tt OPCODE I+RA,RB}
\end{enumerate}
-Remember, the ZIP CPU does not support out of order execution. Therefore,
+Remember, the Zip CPU does not support out of order execution. Therefore,
anytime the memory unit becomes busy both the memory unit and the ALU must
stall until the memory unit is cleared. This is especially true of a load
instruction, which must still write its operand back to the register file.
@@ -1146,18 +1082,35 @@
\item Memory operation followed by a memory operation
\begin{enumerate}
\item\ {\tt STO address,RA}
-\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
+\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
\item\ {\tt LOD address,RB}
-\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
+\item\ {\em (multiple stalls, bus dependent, 4 clocks best)}
\end{enumerate}
-In this case, the LOD instruction cannot start until the STALL is finished.
+In this case, the LOD instruction cannot start until the STO is finished.
With proper scheduling, it is possible to do something in the ALU while the
-STO is busy, but otherwise this pipeline will stall waiting for it to complete.
+memory unit is busy with the STO instruction, but otherwise this pipeline will
+stall waiting for it to complete.
Note that even though the Wishbone bus can support pipelined accesses at
one access per clock, only the prefetch stage can take advantage of this.
Load and Store instructions are stuck at one wishbone cycle per instruction.
+
+\item When waiting for a conditional memory read operation to complete
+\begin{enumerate}
+\item\ {\tt LOD.Z address,RA}
+\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}
+\item\ {\tt OPCODE I+RA,RB}
+\end{enumerate}
+
+In this case, the Zip CPU doesn't warn the prefetch cache to get off the bus
+two cycles before using the bus, so there's a potential for an extra three
+cycle cost due to bus contention between the prefetch and the CPU.
+
+This is true for both the LOD and the STO instructions, with the exception that
+the STO instruction will continue in parallel with any ALU instructions that
+follow it.
+
\end{itemize}
@@ -1279,23 +1232,36 @@
should be sorted, and the next alarm in terms of Jiffies should be written
to the register.
-\section{Manual Cache}
+\section{Direct Memory Access Controller}
-The manual cache is an experimental setting that may not remain with the Zip
-CPU for very long. It is designed to facilitate running from FLASH or ROM
-memory, although the pipeline prefetch cache really makes this need obsolete.
-The manual
-cache works by copying data from a wishbone address (range) into the cache
-register, and then by making that memory available as memory to the Zip System.
-It is a {\em manual cache} because the processor must first specify what
-memory to copy, and then once copied the processor can only access the cache
-memory by the cache memory location. There is no transparency. It is perhaps
-best described as a combination DMA controller and local memory.
+The Direct Memory Access (DMA) controller can be used to either move memory
+from one location to another, to read from a peripheral into memory, or to
+write from a peripheral into memory all without CPU intervention. Further,
+since the DMA controller can issue (and does issue) pipeline wishbone accesses,
+any DMA memory move will by nature be faster than a corresponding program
+accomplishing the same move. To put this to numbers, it may take a program
+18~clocks per word transferred, whereas this DMA controller can move one
+word in two clocks--provided it has bus access. (The CPU gets priority over the
+bus.)
-Worse, this cache is likely going to be removed from the ZipSystem. Having used
-the ZipSystem now for some time, I have yet to find a need or use for the manual
-cache. I will likely replace this peripheral with a proper DMA controller.
+When copying memory from one location to another, the DMA controller will
+copy in units of a given transfer length--up to 1024 words at a time. It will
+read that transfer length into its internal buffer, and then write to the
+destination address from that buffer. If the CPU interrupts a DMA transfer,
+it will release the bus, let the CPU complete whatever it needs to do, and then
+restart its transfer by writing the contents of its internal buffer and then
+re-entering its read cycle again.
+When coupled with a peripheral, the DMA controller can be configured to start
+a memory copy on an interrupt line going high. Further, the controller can be
+configured to issue reads from (or two) the same address instead of incrementing
+the address at each clock. The DMA completes once the total number of items
+specified (not the transfer length) have been transferred.
+
+In each case, once the transfer is complete and the DMA unit returns to
+idle, the DMA will issue an interrupt.
+
+
\chapter{Operation}\label{chap:ops}
The Zip CPU, and even the Zip System, is not a System on a Chip (SoC). It
@@ -1322,7 +1288,7 @@
CPU will immediately start executing your instructions.
This is, however, not how I have used the Zip CPU. I have instead used the
-ZIP CPU in a more controlled environment. For me, the CPU starts in a
+Zip CPU in a more controlled environment. For me, the CPU starts in a
halted state, and waits to be told to start. Further, the RESET address is a
location in RAM. After bringing up the board I am using, and further the
bus that is on it, the RAM memory is then loaded externally with the program
@@ -1333,7 +1299,269 @@
Eventually, I intend to place an operating system onto the ZipSystem, I'm
just not there yet.
+The rest of this chapter examines some common programming constructs, and
+how they might be applied to the Zip System.
+\section{Example: Idle Task}
+One task every operating system needs is the idle task, the task that takes
+place when nothing else can run. On the Zip CPU, this task is quite simple,
+and it is shown in assemble in Tbl.~\ref{tbl:idle-asm}.
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+{\tt idle\_task:} \\
+& {\em ; Wait for the next interrupt, then switch to supervisor task} \\
+& {\tt WAIT} \\
+& {\em ; When we come back, it's because the supervisor wishes to} \\
+& {\em ; wait for an interrupt again, so go back to the top.} \\
+& {\tt BRA idle\_task} \\
+\end{tabular}
+\caption{Example Idle Loop}\label{tbl:idle-asm}
+\end{center}\end{table}
+When this task runs, the CPU will fill up all of the pipeline stages up the
+ALU. The {\tt WAIT} instruction, upon leaving the ALU, places the CPU into
+a sleep state where nothing more moves. Sure, there may be some more settling,
+the pipe cache continue to read until full, other instructions may issue until
+the pipeline fills, but then everything will stall. Then, once an interrupt
+takes place, control passes to the supervisor task to handle the interrupt.
+When control passes back to this task, it will be on the next instruction.
+Since that next instruction sends us back to the top of the task, the idle
+task thus does nothing but wait for an interrupt.
+
+This should be the lowest priority task, the task that runs when nothing else
+can. It will help lower the FPGA power usage overall---at least its dynamic
+power usage.
+
+\section{Example: Memory Copy}
+One common operation is that of a memory move or copy. Consider the C code
+shown in Tbl.~\ref{tbl:memcp-c}.
+\begin{table}\begin{center}
+\parbox{4in}{\begin{tabbing}
+{\tt void} \= {\tt memcp(void *dest, void *src, int len) \{} \\
+ \> {\tt for(int i=0; i \hspace{0.2in} {\tt *dest++ = *src++;} \\
+\}
+\end{tabbing}}
+\caption{Example Memory Copy code in C}\label{tbl:memcp-c}
+\end{center}\end{table}
+This same code can be translated in Zip Assembly as shown in
+Tbl.~\ref{tbl:memcp-asm}.
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+memcp: \\
+& {\em ; R0 = *dest, R1 = *src, R2 = LEN} \\
+& {\em ; The following will operate in 17 clocks per word minus one clock} \\
+& {\tt CMP 0,R2} \\
+& {\tt LOD.Z -1(SP),PC} {\em ; A conditional return }\\
+& {\em ; (One stall on potentially writing to PC)} \\
+& {\tt LOD (R1),R3} \\
+& {\em ; (4 stalls, cannot be scheduled away)} \\
+& {\tt STO R3,(R2)} {\em ; (4 schedulable stalls, has no impact now)} \\
+& {\tt ADD 1,R1} \\
+& {\tt SUB 1,R2} \\
+& {\tt BNZ loop} \\
+& {\em ; (5 stalls, if branch taken, to clear and refill the pipeline)} \\
+& {\tt RET} \\
+\end{tabular}
+\caption{Example Memory Copy code in Zip Assembly}\label{tbl:memcp-asm}
+\end{center}\end{table}
+This example points out several things associated with the Zip CPU. First,
+a straightforward implementation of a for loop is not the fastest loop
+structure. For this reason, we have placed the test to continue at the
+end. Second, all pointers are {\tt void} pointers to arbitrary 32--bit
+data types. The Zip CPU does not have explicit support for smaller or larger
+data types, and so this memory copy cannot be applied at a byte level.
+Third, we've optimized the conditional jump to a return instruction into a
+conditional return instruction.
+
+\section{Context Switch}
+
+Fundamental to any multiprocessing system is the ability to switch from one
+task to the next. In the ZipSystem, this is accomplished in one of a couple
+ways. The first step is that an interrupt happens. Anytime an interrupt
+happens, the CPU needs to execute the following tasks in supervisor mode:
+\begin{enumerate}
+\item Check for a trap instruction. That is, if the user task requested a
+ trap, we may not wish to adjust the context, check interrupts, or call
+ the scheduler. Tbl.~\ref{tbl:trap-check}
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+{\tt return\_to\_user:} \\
+& {\em; The instruction before the context switch processing must} \\
+& {\em; be the RTU instruction that enacted user mode in the first} \\
+& {\em; place. We show it here just for reference.} \\
+& {\tt RTU} \\
+{\tt trap\_check:} \\
+& {\tt MOV uCC,R0} \\
+& {\tt TST \$TRAP,R0} \\
+& {\tt BNZ swap\_out} \\
+& {; \em Do something here to execute the trap} \\
+& {; \em Don't need to call the scheduler, so we can just return} \\
+& {\tt BRA return\_to\_user} \\
+\end{tabular}
+\caption{Checking for whether the user issued a TRAP instruction}\label{tbl:trap-check}
+\end{center}\end{table}
+ shows the rudiments of this code, while showing nothing of how the
+ actual trap would be implemented.
+
+You may also wish to note that the instruction before the first instruction
+in our context swap {\em must be} a return to userspace instruction.
+Remember, the supervisor process is re--entered where it left off. This is
+different from many other processors that enter interrupt mode at some vector
+or other. In this case, we always enter supervisor mode right where we last
+left.\footnote{The one exception to this rule is upon reset where supervisor
+mode is entered at a pre--programmed wishbone memory address.}
+
+\item Capture user counters. If the operating system is keeping track of
+ system usage via the accounting counters, those counters need to be
+ copied and accumulated into some master counter at this point.
+
+\item Preserve the old context. This involves pushing all the user registers
+ onto the user stack and then copying the resulting stack address
+ into the tasks task structure, as shown in Tbl.~\ref{tbl:context-out}.
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+{\tt swap\_out:} \\
+& {\tt MOV -15(uSP),R1} \\
+& {\tt STO R1,stack(R12)} \\
+& {\tt MOV uPC,R0} \\
+& {\tt STO R0,15(R1)} \\
+& {\tt MOV uCC,R0} \\
+& {\tt STO R0,14(R1)} \\
+& {\em ; We can skip storing the stack, uSP, since it'll be stored}\\
+& {\em ; elsewhere (in the task structure) }\\
+& {\tt MOV uR13,R0} \\
+& {\tt STO R0,13(R1)} \\
+ & \ldots {\em ; Need to repeat for all user registers} \\
+& {\tt MOV uR0,R0} \\
+& {\tt STO R0,1(R1)} \\
+\end{tabular}
+\caption{Example Storing User Task Context}\label{tbl:context-out}
+\end{center}\end{table}
+For the sake of discussion, we assume the supervisor maintains a
+pointer to the current task's structure in supervisor register
+{\tt R12}, and that {\tt stack} is an offset to the beginning of this
+structure indicating where the stack pointer is to be kept within it.
+
+ For those who are still interested, the full code for this context
+ save can be found as an assembler macro within the assembler
+ include file, {\tt sys.i}.
+
+\item Reset the watchdog timer. If you are using the watchdog timer, it should
+ be reset on a context swap, to know that things are still working.
+ Example code for this is shown in Tbl.~\ref{tbl:reset-watchdog}.
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+\multicolumn{2}{l}{{\tt `define WATCHDOG\_ADDRESS 32'hc000\_0002}}\\
+\multicolumn{2}{l}{{\tt `define WATCHDOG\_TICKS 32'd1\_000\_000} {; \em = 10 ms}}\\
+& {\tt LDI WATCHDOG\_ADDRESS,R0} \\
+& {\tt LDI WATCHDOG\_TICKS,R1} \\
+& {\tt STO R1,(R0)}
+\end{tabular}
+\caption{Example Watchdog Reset}\label{tbl:reset-watchdog}
+\end{center}\end{table}
+
+\item Interrupt handling. An interrupt handler within the Zip System is nothing
+ more than a task. At context swap time, the supervisor needs to
+ disable all of the interrupts that have tripped, and then enable
+ all of the tasks that would deal with each of these interrupts.
+ These can be user tasks, run at higher priority than any other user
+ tasks. Either way, they will need to re--enable their own interrupt
+ themselves, if the interrupt is still relevant.
+
+ An example of this master interrut handling is shown in
+ Tbl.~\ref{tbl:pre-handler}.
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+{\tt pre\_handler:} \\
+& {\tt LDI PIC\_ADDRESS,R0 } \\
+& {\em ; Start by grabbing the interrupt state from the interrupt}\\
+& {\em ; controller. We'll store this into the register R7 so that }\\
+& {\em ; we can keep and preserve this information for the scheduler}\\
+& {\em ; to use later. }\\
+& {\tt LOD (R0),R1} \\
+& {\tt MOV R1,R7 } \\
+& {\em ; As a next step, we need to acknowledge and disable all active}\\
+& {\em ; interrupts. We'll start by calculating all of our active}\\
+& {\em ; interrupts.}\\
+& {\tt AND 0x07fff,R1 } \\
+& {\em ; Put the active interrupts into the upper half of R1} \\
+& {\tt ROL 16,R1 } \\
+& {\tt LDILO 0x0ffff,R1 } \\
+& {\tt AND R7,R1}\\
+& {\em ; Acknowledge and disable active interrupts}\\
+& {\em ; This also disables all interrupts from the controller, so}\\
+& {\em ; we'll need to re-enable interrupts in general shortly } \\
+& {\tt STO R1,(R0) } \\
+& {\em ; We leave our active interrupt mask in R7 so the scheduler can}\\
+& {\em ; release any tasks that depended upon them. } \\
+\end{tabular}
+\caption{Example checking for active interrupts}\label{tbl:pre-handler}
+\end{center}\end{table}
+
+\item Calling the scheduler. This needs to be done to pick the next task
+ to switch to. It may be an interrupt handler, or it may be a normal
+ user task. From a priority standpoint, it would make sense that the
+ interrupt handlers all have a higher priority than the user tasks,
+ and that once they have been called the user tasks may then be called
+ again. If no task is ready to run, run the idle task to wait for an
+ interrupt.
+
+ This suggests a minimum of four task priorities:
+ \begin{enumerate}
+ \item Interrupt handlers, executed with their interrupts disabled
+ \item Device drivers, executed with interrupts re-enabled
+ \item User tasks
+ \item The idle task, executed when nothing else is able to execute
+ \end{enumerate}
+
+ For our purposes here, we'll just assume that a pointer to the current
+ task is maintained in {\tt R12}, that a {\tt JSR scheduler} is
+ called, and that the next current task is likewise placed into
+ {\tt R12}.
+
+\item Restore the new tasks context. Given that the scheduler has returned a
+ task that can be run at this time, the stack pointer needs to be
+ pulled out of the tasks task structure, placed into the user
+ register, and then the rest of the user registers need to be popped
+ back off of the stack to run this task. An example of this is
+ shown in Tbl.~\ref{tbl:context-in},
+\begin{table}\begin{center}
+\begin{tabular}{ll}
+{\tt swap\_in:} \\
+& {\tt LOD stack(R12),R1} \\
+& {\tt MOV 15(R1),uSP} \\
+& {\tt LOD 15(R1),R0} \\
+& {\tt MOV R0,uPC} \\
+& {\tt LOD 14(R1),R0} \\
+& {\tt MOV R0,uCC} \\
+& {\tt LOD 13(R1),R0} \\
+& {\tt MOV R0,uR12} \\
+ & \ldots {\em ; Need to repeat for all user registers} \\
+& {\tt LOD 1(R1),R0} \\
+& {\tt MOV R0,uR0} \\
+& {\tt BRA return\_to\_user} \\
+\end{tabular}
+\caption{Example Restoring User Task Context}\label{tbl:context-in}
+\end{center}\end{table}
+ assuming as before that the task
+ pointer is found in supervisor register {\tt R12}.
+ As with storing the user context, the full code associated with
+ restoring the user context can be found in the assembler include
+ file, {\tt sys.i}.
+
+\item Clear the userspace accounting registers. In order to keep track of
+ per process system usage, these registers need to be cleared before
+ reactivating the userspace process. That way, upon the next
+ interrupt, we'll know how many clocks the userspace program has
+ encountered, and how many instructions it was able to issue in
+ those many clocks.
+
+\item Jump back to the instruction just before saving the last tasks context,
+ because that location in memory contains the return from interrupt
+ command that we are going to need to execute, in order to guarantee
+ that we return back here again.
+\end{enumerate}
+
\chapter{Registers}\label{chap:regs}
The ZipSystem registers fall into two categories, ZipSystem internal registers
@@ -1342,7 +1570,7 @@
\begin{center}\begin{reglist}
PIC & \scalebox{0.8}{\tt 0xc0000000} & 32 & R/W & Primary Interrupt Controller \\\hline
WDT & \scalebox{0.8}{\tt 0xc0000001} & 32 & R/W & Watchdog Timer \\\hline
-CCHE & \scalebox{0.8}{\tt 0xc0000002} & 32 & R/W & Manual Cache Controller \\\hline
+ & \scalebox{0.8}{\tt 0xc0000002} & 32 & R/W & {\em (Reserved for future use)} \\\hline
CTRIC & \scalebox{0.8}{\tt 0xc0000003} & 32 & R/W & Secondary Interrupt Controller \\\hline
TMRA & \scalebox{0.8}{\tt 0xc0000004} & 32 & R/W & Timer A\\\hline
TMRB & \scalebox{0.8}{\tt 0xc0000005} & 32 & R/W & Timer B\\\hline
@@ -1356,6 +1584,10 @@
UMSTL & \scalebox{0.8}{\tt 0xc000000d} & 32 & R/W & User Stall Counter \\\hline
UPSTL & \scalebox{0.8}{\tt 0xc000000e} & 32 & R/W & User Pre--Fetch Stall Counter \\\hline
UICNT & \scalebox{0.8}{\tt 0xc000000f} & 32 & R/W & User Instruction Counter\\\hline
+DMACTRL & \scalebox{0.8}{\tt 0xc0000010} & 32 & R/W & DMA Control Register\\\hline
+DMALEN & \scalebox{0.8}{\tt 0xc0000011} & 32 & R/W & DMA total transfer length\\\hline
+DMASRC & \scalebox{0.8}{\tt 0xc0000012} & 32 & R/W & DMA source address\\\hline
+DMADST & \scalebox{0.8}{\tt 0xc0000013} & 32 & R/W & DMA destination address\\\hline
% Cache & \scalebox{0.8}{\tt 0xc0100000} & & & Base address of the Cache memory\\\hline
\end{reglist}
\caption{Zip System Internal/Peripheral Registers}\label{tbl:zpregs}
@@ -1491,6 +1723,49 @@
Operating System will read the timers back off, to determine how much of the
CPU the process had consumed.
+The final peripheral to discuss is the DMA controller. This controller
+has four registers. Of these four, the length, source and destination address
+registers should need no further explanation. They are full 32--bit registers
+specifying the entire transfer length, the starting address to read from, and
+the starting address to write to. The registers can be written to when the
+DMA is idle, and read at any time. The control register, however, will need
+some more explanation.
+
+The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.
+\begin{table}\begin{center}
+\begin{bitlist}
+31 & R & DMA Active\\\hline
+30 & R & Wishbone error, transaction aborted (cleared on any write)\\\hline
+29 & R/W & Set to '1' to prevent the controller from incrementing the source address, '0' for normal memory copy. \\\hline
+28 & R/W & Set to '0' to prevent the controller from incrementing the
+ destination address, '0' for normal memory copy. \\\hline
+27 \ldots 16 & W & The DMA Key. Write a 12'hfed to these bits to start the
+ activate any DMA transfer. \\\hline
+27 & R & Always reads '0', to force the deliberate writing of the key. \\\hline
+26 \ldots 16 & R & Indicates the number of items in the transfer buffer that
+ have yet to be written. \\\hline
+15 & R/W & Set to '1' to trigger on an interrupt, or '0' to start immediately
+ upon receiving a valid key.\\\hline
+14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
+9\ldots 0 & R/W & Intermediate transfer length minus one. Thus, to transfer
+ one item at a time set this value to 0. To transfer 1024 at a time,
+ set it to 1024.\\\hline
+\end{bitlist}
+\caption{DMA Control Register Bits}\label{tbl:dmacbits}
+\end{center}\end{table}
+This control register has been designed so that the common case of memory
+access need only set the key and the transfer length. Hence, writing a
+\hbox{32'h0fed03ff} to the control register will start any memory transfer.
+On the other hand, if you wished to read from a serial port (constant address)
+and put the result into a buffer every time a word was available, you
+might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
+have a serial port wired to the zero bit of this interrupt control. (The
+DMA controller does not use the interrupt controller, and cannot clear
+interrupts.) As a third example, if you wished to write to an external
+FIFO anytime it was less than half full (had fewer than 512 items), and
+interrupt line 2 indicated this condition, you might wish to issue a
+\hbox{32'h1fed8dff} to this port.
+
\section{Debug Port Registers}
Accessing the Zip System via the debug port isn't as straight forward as
accessing the system via the wishbone bus. The debug port itself has been
@@ -1505,7 +1780,7 @@
11 & W & Command clear PF cache\\\hline
10 & R/W & Command HALT, Set to '1' to halt the CPU\\\hline
9 & R & Stall Status, '1' if CPU is busy\\\hline
-8 & R/W & Step Command, set to '1' to step the CPU\\\hline
+8 & R/W & Step Command, set to '1' to step the CPU, also sets the halt bit\\\hline
7 & R & Interrupt Request \\\hline
6 & R/W & Command RESET \\\hline
5\ldots 0 & R/W & Debug Register Address \\\hline
@@ -1557,7 +1832,7 @@
\caption{Debug Register Addresses}\label{tbl:dbgaddrs}
\end{center}\end{table}
Primarily, these ``registers'' include access to the entire CPU register
-set, as well as the 16~internal peripherals. To read one of these registers
+set, as well as the internal peripherals. To read one of these registers
once the address is set, simply issue a read from the data port. To write
one of these registers or peripheral ports, simply write to the data port
after setting the proper address.
@@ -1646,7 +1921,7 @@
This core is based upon the Basys--3 development board sold by Digilent.
The Basys--3 development board contains one external 100~MHz clock, which is
-sufficient to run the ZIP CPU core.
+sufficient to run the Zip CPU core.
\begin{table}[htbp]
\begin{center}
\begin{clocklist}
@@ -1712,6 +1987,340 @@
detail. Finally, the Zip System produces one external interrupt whenever
the CPU halts to wait for the debugger.
+\chapter{Initial Assessment}\label{chap:assessment}
+
+Having now worked with the Zip CPU for a while, it is worth offering an
+honest assessment of how well it works and how well it was designed. At the
+end of this assessment, I will propose some changes that may take place in a
+later version of this Zip CPU to make it better.
+
+\section{The Good}
+\begin{itemize}
+\item The Zip CPU is light weight and fully featured as it exists today. For
+ anyone who wishes to build a general purpose CPU and then to
+ experiment with building and adding particular features, the Zip CPU
+ makes a good starting point--it is fairly simple. Modifications should
+ be simple enough.
+\item As an estimate of the ``weight'' of this implementation, the CPU has
+ cost me less than 150 hours to implement from its inception.
+\item The Zip CPU was designed to be an implementable soft core that could be
+ placed within an FPGA, controlling actions internal to the FPGA. It
+ fits this role rather nicely. It does not fit the role of a system on
+ a chip very well, but then it was never intended to be a system on a
+ chip but rather a system within a chip.
+\item The extremely simplified instruction set of the Zip CPU was a good
+ choice. Although it does not have many of the commonly used
+ instructions, PUSH, POP, JSR, and RET among them, the simplified
+ instruction set has demonstrated an amazing versatility. I will contend
+ therefore and for anyone who will listen, that this instruction set
+ offers a full and complete capability for whatever a user might wish
+ to do with two exceptions: bytewise character access and accelerated
+ floating-point support.
+\item This simplified instruction set is easy to decode.
+\item The simplified bus transactions (32-bit words only) were also very easy
+ to implement.
+\item The novel approach of having a single interrupt vector, which just
+ brings the CPU back to the instruction it left off at within the last
+ interrupt context doesn't appear to have been that much of a problem.
+ If most modern systems handle interrupt vectoring in software anyway,
+ why maintain hardware support for it?
+\item My goal of a high rate of instructions per clock may not be the proper
+ measure. For example, if instructions are being read from a SPI flash
+ device, such as is common among FPGA implementations, these same
+ instructions may suffer stalls of between 64 and 128 cycles per
+ instruction just to read the instruction from the flash. Executing the
+ instruction in a single clock cycle is no longer the appropriate
+ measure. At the same time, it should be possible to use the DMA
+ peripheral to copy instructions from the FLASH to a temporary memory
+ location, after which they may be executed at a single instruction
+ cycle per access again.
+\end{itemize}
+
+\section{The Not so Good}
+\begin{itemize}
+\item While one of the stated goals was to use a small amount of logic,
+ 3k~LUTs isn't that impressively small. Indeed, it's really much
+ too expensive when compared against other 8 and 16-bit CPUs that have
+ less than 1k LUTs.
+
+ Still, \ldots it's not bad, it's just not astonishingly good.
+
+\item The fact that the instruction width equals the bus width means that the
+ instruction fetch cycle will always be interfering with any load or
+ store memory operation, with the only exception being if the
+ instruction is already in the cache. {\em This has become the
+ fundamental limit on the speed and performance of the CPU!}
+ Those familiar with the Von--Neumann approach of sharing a bus
+ between data and instructions will not be surprised by this assessment.
+
+ This could be fixed in one of three ways: the instruction set
+ architecture could be modified to handle Very Long Instruction Words
+ (VLIW) so that each 32--bit word would encode two or more instructions,
+ the instruction fetch bus width could be increased from 32--bits to
+ 64--bits or more, or the instruction bus could be separated from the
+ data bus. Any and all of these approaches would increase the overall
+ LUT count.
+
+\item The (non-existant) floating point unit was an after-thought, isn't even
+ built as a potential option, and most likely won't support the full
+ IEEE standard set of FPU instructions--even for single point precision.
+ This (non-existant) capability would benefit the most from an
+ out-of-order execution capability, which the Zip CPU does not have.
+
+ Still, sharing FPU registers with the main register set was a good
+ idea and worth preserving, as it simplifies context swapping.
+
+ Perhaps this really isn't a problem, but rather a feature. By not
+ implementing FPU instructions, the Zip CPU maintains a lower LUT count
+ than it would have if it did implement these instructions.
+
+\item The CPU has no character support. This is both good and bad.
+ Realistically, the CPU works just fine without it. Characters can be
+ supported as subsets of 32-bit words without any problem. Practically,
+ though, it will make compiling non-Zip CPU code difficult--especially
+ anything that assumes sizeof(int)=4*sizeof(char), or that tries to
+ create unions with characters and integers and then attempts to
+ reference the address of the characters within that union.
+
+\item The Zip CPU does not support a data cache. One can still be built
+ externally, but this is a limitation of the CPU proper as built.
+ Further, under the theory of the Zip CPU design (that of an embedded
+ soft-core processor within an FPGA, where any ``address'' may reference
+ either memory or a peripheral that may have side-effects), any data
+ cache would need to be based upon an initial knowledge of whether or
+ not it is supporting memory (cachable) or peripherals. This knowledge
+ must exist somewhere, and that somewhere is currently (and by design)
+ external to the CPU.
+
+ This may also be written off as a ``feature'' of the Zip CPU, since
+ the addition of a data cache can greatly increase the LUT count of
+ a soft core.
+
+\item Many other instruction sets offer three operand instructions, whereas
+ the Zip CPU only offers two operand instructions. This means that it
+ takes the Zip CPU more instructions to do many of the same operations.
+ The good part of this is that it gives the Zip CPU a greater amount of
+ flexibility in its immediate operand mode, although that increased
+ flexibility isn't necessarily as valuable as one might like.
+
+\item The Zip CPU does not currently detect and trap on either illegal
+ instructions or bus errors. Attempts to access non--existent
+ memory quietly return erroneous results, rather than halting the
+ process (user mode) or halting or resetting the CPU (supervisor mode).
+
+\item The Zip CPU doesn't support out of order execution. I suppose it could
+ be modified to do so, but then it would no longer be the ``simple''
+ and low LUT count CPU it was designed to be. The two primary results
+ are that 1) loads may unnecessarily stall the CPU, even if other
+ things could be done while waiting for the load to complete, 2)
+ bus errors on stores will never be caught at the point of the error,
+ and 3) branch prediction becomes more difficult.
+
+\item Although switching to an interrupt context in the Zip CPU design doesn't
+ require a tremendous swapping of registers, in reality it still
+ does--since any task swap still requires saving and restoring all
+ 16~user registers. That's a lot of memory movement just to service
+ an interrupt.
+
+\item The Zip CPU is by no means generic: it will never handle addresses
+ larger than 32-bits (16GB) without a complete and total redesign.
+ This may limit its utility as a generic CPU in the future, although
+ as an embedded CPU within an FPGA this isn't really much of a limit
+ or restriction.
+
+\item While the Zip CPU has its own assembler, it has no linker and does not
+ (yet) support a compiler. The standard C library is an even longer
+ shot. My dream of having binutils and gcc support has not been
+ realized and at this rate may not be realized. (I've been intimidated
+ by the challenge everytime I've looked through those codes.)
+
+\item While the Wishbone Bus (B4) supports a pipelined mode with single cycle
+ execution, the Zip CPU is unable to exploit this parallelism. Instead,
+ apart from the DMA and the pipelined prefetch, all loads and stores
+ are single wishbone bus operations requiring a minimum of 3 clocks.
+ (In practice, this has turned into 7-clocks.)
+
+\iffalse
+\item There is no control over whether or not an instruction sets the
+ condition codes--certain instructions always set the condition codes,
+ other instructions never set them. This effectively limits conditional
+ instructions to a single instruction only (with two or more
+ instructions as an exception), as the first instruction that sets
+ condition codes will break the condition code chain.
+
+ {\em (A proposed change below address this.)}
+
+\item Using the CC register as a trap address was a bad idea--it limits the CC
+ registers ability to be used in future expansion, such as by adding
+ exception indication flags: bus error, floating point exception, etc.
+
+ {\em (This can be changed by a different O/S implementation of the trap
+ instruction.)}
+\item The current implementation suffers from too many stalls on any
+ branch--even if the branch is known early on.
+
+ {\em (This is addressed in proposals below.)}
+ % Addressed, 20150918
+
+\item In a similar fashion, a switch to interrupt context forces the pipeline
+ to be cleared, whereas it might make more sense to just continue
+ executing the instructions already in the pipeline while the prefetch
+ stage is working on switching to the interrupt context.
+
+ {\em (Also addressed in proposals below.)}
+ % This should happen so rarely that it is not really a problem
+\fi
+
+\end{itemize}
+
+\section{The Next Generation}
+This section could also be labeled as my ``To do'' list.
+
+Given the feedback listed above, perhaps its time to consider what changes could be made to improve the Zip CPU in the future. I offer the following as proposals:
+
+\begin{itemize}
+\item {\bf Remove the low LUT goal.} It wasn't really achieved, and the
+ proposals below will only increase the amount of logic the Zip CPU
+ requires. While I expect that the Zip CPU will always be somewhat
+ of a light weight, it will never be the smallest kid on the block.
+
+ I'm actually struggling with this idea. The whole goal of the Zip
+ CPU was to be light weight. Wouldn't it make more sense to create and
+ maintain options whereby it would remain lightweight? For example, if
+ the process accounting registers are anything but light weight, why
+ keep them? Why not instead make some compile flags that just turn them
+ off, keeping the CPU lightweight? The same holds for the prefetch
+ cache.
+
+\iffalse
+\item {\bf Adjust the Zip CPU so that conditional instructions do not set
+ flags}, although they may explicitly set condition codes if writing
+ to the CC register.
+
+ This is a simple change to the core, and may show up in new releases.
+ % Fixed, 20150918
+\fi
+
+\item The `{\tt .V}' condition was never used in any code other than my test
+ code. Suggest changing it to a `{\tt .LE}' condition, which seems
+ to be more useful.
+
+\iffalse
+\item Add in an {\bf unpredictable branch delay slot}, so that on any branch
+ the delay slot may or may not be executed before the branch.
+ Instructions that do not depend upon the branch, and that should be
+ executed were the branch not taken, could be placed into the delay
+ slot. Thus, if the branch isn't taken, we wouldn't suffer the stall,
+ whereas it wouldn't affect the timing of the branch if taken. It would
+ just do something irrelevant.
+
+ % Changes made, 20150918, make this option no longer relevant
+
+\item {\bf Re-engineer Branch Processing.} There's no reason why a {\tt BRA}
+ instruction should create five stall cycles. The decode stage, plus
+ the prefetch engine, should be able to drop this number of stalls via
+ better branch handling.
+
+ Indeed, this could turn into a simple means of branch prediction:
+ if {\tt BRA} suffered a single stall only, whereas {\tt BRA.C}
+ suffered five stalls, then {\tt BRA.!C} followed by {\tt BRA} would
+ be faster than a {\tt BRA.C} instruction. This would then allow a
+ compiler to do explicit branch optimizations.
+
+ Of course, longer branches using {\tt ADD X,PC} would still not be
+ optimized.
+
+ % DONE: 20150918 -- to include the ADD X,PC instructions
+
+\item {\bf Request bus access for Load/Store two cycles earlier.} The problem
+ here is the contention for the bus between the memory unit and the
+ prefetch unit. Currently, the memory unit must ask the prefetch
+ unit to release the bus if it is in the middle of a bus cycle. At this
+ point, the prefetch drops the {\tt STB} line on the next clock and must
+ then wait for the last {\tt ACK} before releasing the bus. If the
+ request takes one clock, dropping the strobe line the next, waiting
+ for an acknowledgement takes another, and then the bus must be idle
+ for one cycle before starting again, these extra cycles add up.
+ It should be possible to tell the prefetch stage to give up the bus
+ as soon as the decoder knows the instruction will need the bus.
+ Indeed, if done in the decode stage, this might drop the seven cycle
+ access down by two cycles.
+
+ % FIXED: 20150918
+\fi
+
+\item {\bf Consider a more traditional Instruction Cache.} The current
+ pipelined instruction cache just reads a window of memory into
+ its cache. If the CPU leaves that window, the entire cache is
+ invalidated. A more traditional cache, however, might allow
+ common subroutines to stay within the cache without invalidating the
+ entire cache structure.
+
+\iffalse
+\item {\bf Very Long Instruction Word (VLIW).} Now, to speed up operation, I
+ propose that the Zip CPU instruction set be modified towards a Very
+ Long Instruction Word (VLIW) implementation. In this implementation,
+ an instruction word may contain either one or two separate
+ instructions. The first instruction would take up the high order bits,
+ the second optional instruction the lower 16-bits. Further, I propose
+ that any of the ALU instructions (SUB through LSR) automatically have
+ a second instruction whenever their operand `B' is a register, and use
+ the full 20-bit immediate if not. This will effectively eliminate the
+ register plus immediate mode for all of these instructions.
+
+ This is the minimal required change to increase the number of
+ instructions per clock cycle. Other changes would need to take place
+ as well to support this. These include:
+ \begin{itemize}
+ \item Instruction words containing two instructions would take two
+ clocks to complete, while requiring only a single cycle
+ instruction fetch.
+ \item Instructions preceded by a label in the asseembler must always
+ start in the high order word.
+ \item VLIW's, once started, must always execute to completion. The
+ upper word may set the PC, the lower word may not. Regardless
+ of whether the upper word sets the PC, the lower word must
+ still be guaranteed to complete before the PC changes. On any
+ switch to (or from) interrupt context, both instructions must
+ complete or none of the instructions in the word shall
+ complete prior to the switch.
+ \item STEP commands and BREAK instructions will only take place after
+ the entire word is executed.
+ \end{itemize}
+
+ If done well, the assembler should be able to handle these changes
+ with the biggest impacts to the user being increased performance and
+ a loss of the register plus immediate ALU modes. (These weren't really
+ relevant for the XOR, OR, AND, etc. operations anyway.) Machine code
+ compatibility will not be maintained.
+
+ A proposed secondary instruction set might consist of: a four bit
+ operand (any of the prior instructions would be supported, with some
+ exceptions such as moves to and from user registers while in
+ supervisor mode not being supported), a 4-bit register result (PC not
+ allowed), a 3-bit conditional (identical to the conditional for the
+ upper word), a single bit for whether or not an immediate is present
+ or not, followed by either a 4-bit register or a 4-bit signed
+ immediate. The multiply instruction would steal the immediate flag to
+ be used as a sign indication, forcing both operands to be registers
+ without any immediate offsets.
+
+ {\em Initial conversion of several library functions to this secondary
+ instruction set has demonstrated little to no gain. The problem was
+ that the new instruction set was made by joining a rarely used
+ instruction (ALU with register and not immediate) with a more common
+ instruction. The utility was then limited by the utility of the rare
+ instrction, which limited the impact of the entire approach. }
+\else
+\item {\bf Very Long Instruction Word (VLIW).} The goal here would be to
+ create a new instruction set whereby two instructions would be encoded
+ in each 32--bit word. While this may speed up
+ CPU operation, it would necessitate an instruction redesign.
+\fi
+
+\end{itemize}
+
+
% Appendices
% Index
\end{document}
/doc/Makefile
16,5 → 16,5
rm $(DSRC)/spec.dvi $(DSRC)/spec.log |
rm $(DSRC)/spec.aux $(DSRC)/spec.toc |
rm $(DSRC)/spec.lot $(DSRC)/spec.lof |
rm spec.ps |
rm $(DSRC)/spec.out spec.ps |
|
/sw/lib/mpy32u.S
0,0 → 1,27
mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1 |
PUSH R2 |
PUSH R3 |
PUSH R4 |
MOV R0,R2 |
MULU R1,R2 ; R2 = Low order bits, low(R0) * low(R1) |
MOV R0,R3 |
LSR 16,R3 ; Put high order bits in lower half of R3 |
MULU R1,R3 ; R3 = Mid order bits, high(R0) * low(R1) |
LSR 16,R1 ; R1 = High order bits of R1, being done w/ low order |
MOV R1,R4 ; |
MUL R0,R4 ; R4 = Mid order bits, low(R0) * high(R1) |
LSR 16,R0 |
MULU R1,R0 ; R0 = High order bits, high(R0) * high(R1) |
ADD R3,R4 ; R4 = sum of mid order bits |
ADD.C 0x010000,R0 ; Add in the carry (if it happened) |
MOV R4,R3 |
LSR 16,R3 |
ADD R3,R0 ; R0 = high order bits plus high order mid-bits |
LSL 16,R4 |
ADD R4,R2 ; R2 = low order bits plus low order mid-bits |
ADD.C 1,R0 ; Add in the carry to R0 (if it happened) |
MOV R2,R1 ; Place low order bits into R1 |
POP R4 |
POP R3 |
POP R2 |
RET |
/sw/lib/divs.S
0,0 → 1,36
; |
; DIVS |
; |
; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1. |
; We'll call R0 (input) x, R1(input) y, result is such that |
; R0 * y + R1 = x. Now let's work through our signs with an example |
; where x = +/- 22, and y = +/- 4: |
; |
; x y |
; + + No change, just call divu |
; - + (x=-22,y= 4,R0=-5,R1=-2) |
; + - (x= 22,y=-4,R0=-5,R1= 2) |
; - - (x=-22,y=-4,R0= 5,R1=-2) |
; |
; |
; |
divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1 |
PUSH R2 |
CLR R2 ; Keep track of resulting sign in R2 |
TST -1,R0 ; Is R0 negative? |
LDI 3,R2 ; If so, resulting sign will be negative, and |
NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0)) |
TST -1,R1 ; Is R1 negative? |
XOR.LT 1,R2 ; If so, result will be opposite sign of before |
TST -1,R1 ; Need to retest since xor modified flags |
NEG.LT R1 ; Now we get R1=ABS(R1) |
JSR divu ; Do our unsigned multiply |
TST 1,R2 ; Check resulting sign |
NEG.NE R0 ; Need to flip the sign of our result |
TST 2,R2 ; Now, if R1 was originally negative |
NEG.LT R1 ; Then negate R1 |
ret_div32s: |
POP R2 |
RET |
|
|
/sw/lib/divu.S
0,0 → 1,42
; |
; |
; |
; |
divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 |
TST R1 |
BNZ divu_valid_divide |
CLR R0 ; Should be a divide by zero error / trap |
RET |
divu_valid_divide: |
PUSH R2 |
PUSH R3 |
LDI 1,R2 ; Here's where we record the bit we are working on |
CLR R3 ; Here's where we build our result |
; Our original loop rejoin point, before a touch of unrolling |
CMP R1,R0 |
BRC divu_top_bit_set |
TST -1,R1 |
BLT divu_top_bit_set |
divu_rotate_up_r1: |
LSL 1,R2 |
LSL 1,R1 |
CMP R1,R0 |
BRC divu_top_bit_set |
TST -1,R1 |
BGT divu_rotate_up_r1 |
divu_top_bit_set: |
divu_next_bit: |
CMP R1,R0 |
BRC divu_prep_next_bit |
SUB R1,R0 |
OR R2,R3 |
divu_prep_next_bit |
LSR 1,R1 |
LSR 1,R2 |
BNZ divu_next_bit |
MOV R0,R1 |
MOV R3,R0 |
POP R3 |
POP R2 |
RET |
|
/sw/lib/mpy32s.S
0,0 → 1,22
; We could build mul32s (32-bit signed multiply) as |
mpy32s: |
PUSH R2 |
CLR R2 ; Keep track of resulting sign in R2 |
TST R0 ; Is R0 negative? |
XOR.LT #1,R2 ; If so, resulting sign will be negative, and |
NEG.NZ R0 ; then we negate R0 (R0 = ABS(R0)) |
TST R1 ; Is R1 negative? |
XOR.LT #1,R2 ; If so, result will be opposite sign of before |
TST R1 ; Need to retest since xor modified flags |
NEG.LT R1 ; Now we get R1=ABS(R1) |
JSR mpy32u ; Do our unsigned multiply |
CMP R2 ; Check resulting sign |
BZ ret_mul32s ; If positive, do nothing more |
NOT R0 ; If negative, negate the result |
NOT R1 |
ADD $1,R1 |
ADD.C $1,R0 |
ret_mul32s: |
POP R2 |
RET |
|
/sw/zasm/test.S
107,6 → 107,7
clr r5 |
clr r6 |
clr r7 |
clr r8 |
clr r9 |
clr r10 |
clr r11 |
184,6 → 185,7
clr r5 |
clr r6 |
clr r7 |
clr r8 |
clr r9 |
clr r10 |
clr r11 |
209,7 → 211,7
add $32,r0 |
add $-33,r0 |
bnz test_failure |
not.z r0 |
not r0 |
bge test_failure |
junk_address: |
clrf r0 |
300,10 → 302,11
.dat __here__+0x0100000+5 |
test_start: |
ldi $0x01000,r11 |
ldi -1,r10 |
lod test_data+pc,pc |
clr r11 |
clr r10 |
noop |
cmp $0,r11 |
cmp $0,r10 |
trap.z r11 |
add $1,r0 |
add $1,r0 |
530,8 → 533,8
// Now, let's test whether or not we can handle a subroutine |
#ifdef PUSH_TEST |
reverse_bit_order: |
PUSH(R1,SP) |
PUSH(R2,SP) |
PUSH(R1,SP) ; R1 will be our loop counter |
PUSH(R2,SP) ; R2 will be our accumulator and eventual result |
LDI 32,R1 |
CLR R2 |
reverse_bit_order_loop: |
/sw/zasm/zasm.y
37,6 → 37,7
|
%{ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include "asmdata.h" |
|
419,6 → 420,7
#include <sys/stat.h> |
#include <sys/fcntl.h> |
#include <assert.h> |
#include <string> |
|
OBJFILE objcode; |
|
499,7 → 501,12
FILE *ppout; |
pid_t zpp_pid; |
int zpp_status; |
std::string inclist; |
if (NULL != getenv("ZIPINC")) |
inclist = getenv("ZIPINC"); |
|
printf("Original INCLIST = %s\n", inclist.c_str()); |
|
master_input_filename = NULL; |
|
// Find what directory zasm is in, so that we can find zpp when |
521,7 → 528,22
skp++; |
} else if (argv[argn+skp][1] == 'E') |
preprocess_only = true; |
else if (argv[argn+skp][1] == 'd') |
else if (argv[argn+skp][1] == 'I') { |
if (argv[argn+skp][2]) { |
if (inclist.size() != 0) { |
inclist += std::string(":"); |
inclist += &argv[argn+skp][2]; |
} else |
inclist = &argv[argn+skp][2]; |
} else if (argn+skp+1<argc) { |
if (inclist.size() != 0) { |
inclist += std::string(":"); |
inclist += &argv[argn+skp+1][2]; |
} else |
inclist = &argv[argn+skp+1][2]; |
argn++; |
} |
} else if (argv[argn+skp][1] == 'd') |
yydebug = 1; |
else if (argv[argn+skp][1] == 'h') { |
usage(); |
540,6 → 562,7
} |
} |
} |
printf("New INCLIST = %s\n", inclist.c_str()); |
|
if (preprocess_only) { |
objcode.open("/dev/null"); |
554,6 → 577,7
objcode.open(zout_fname); |
} |
|
setenv("ZIPINC",inclist.c_str(), 1); |
master_input_filename = NULL; |
|
if (argc > 0) { |
/sw/zasm/asmdata.cpp
378,7 → 378,10
break; |
case OP_NEG: |
if (m_cond != zp.ZIPC_ALWAYS) { |
yyerror("Illegal operation: Conditional negate. Negates cannot handle conditions"); |
LLINE *lln = new LLINE; |
lln->addline(new ILINE(zp.op_mov(m_cond,-1,m_opb,m_opb))); |
lln->addline(new ILINE(zp.op_not(m_cond,m_opb))); |
return lln; |
} else { |
LLINE *lln = new LLINE; |
lln->addline(new ILINE(zp.op_not(m_opb))); |
/sw/zasm/zpp.l
662,9 → 662,40
BUFSTACK(const char *fname) { |
m_fp = fopen(fname, "r"); |
if (!m_fp) { |
fprintf(stderr, "Cannot open %s\n", fname); |
perror("O/S Err:"); |
exit(-1); |
char *pathptr = getenv("ZIPINC"); |
if (!pathptr) { |
fprintf(stderr, "Cannot open %s\n", fname); |
perror("O/S Err:"); |
exit(-1); |
} else { |
char *dptr, *colonp; |
char *pathcpy = new char[strlen(pathptr)+8192]; |
strcpy(pathcpy, pathptr); |
|
fprintf(stderr, "ZIPINC := %s\n", pathptr); |
dptr = pathptr; |
while((!m_fp)&&(NULL != (colonp = strchr(dptr, ':')))) { |
strncpy(pathcpy, dptr, colonp-pathptr); |
strcat(pathcpy, "/"); |
strcat(pathcpy, fname); |
fprintf(stderr, "Looking for include file, %s\n", pathcpy); |
if (access(fname, R_OK)==0) |
m_fp = fopen(pathcpy, "r"); |
dptr = colonp+1; |
} if ((!m_fp)&&(*dptr)) { |
strcpy(pathcpy, dptr); |
strcat(pathcpy, "/"); |
strcat(pathcpy, fname); |
fprintf(stderr, "Looking for include file, %s\n", pathcpy); |
m_fp = fopen(pathcpy, "r"); |
} if (!m_fp) { |
fprintf(stderr, "Cannot open %s\n", fname); |
perror("O/S Err:"); |
exit(-1); |
} |
|
delete[] pathcpy; |
} |
} |
|
if (curbs) |
/sw/zasm/sys.i
44,7 → 44,7
sys.ccn equ 0x004 |
sys.ccc equ 0x002 |
sys.ccz equ 0x001 |
sys.bu.pic equ 0x000 |
sys.bus.pic equ 0x000 |
sys.bus.wdt equ 0x001 |
sys.bus.cache equ 0x002 |
sys.bus.ctrpic equ 0x003 |
120,12 → 120,10
ADD 1,SP |
#define RET LOD 1(SP),PC |
#define SAVE_USER_CONTEXT(DR,AR) \ |
MOV -16(uSP),AR \ |
MOV -15(uSP),AR \ |
MOV uPC,DR \ |
STO DR,16(AR) \ |
STO DR,15(AR) \ |
MOV uCC,DR \ |
STO DR,15(AR) \ |
MOV uSP,DR \ |
STO DR,14(AR) \ |
MOV uR12,DR \ |
STO DR,13(AR) \ |
181,10 → 179,8
LOD 13(AR),DR \ |
MOV DR,uR12 \ |
LOD 14(AR),DR \ |
MOV DR,uSP \ |
MOV DR,uCC \ |
LOD 15(AR),DR \ |
MOV DR,uCC \ |
LOD 16(AR),DR \ |
MOV DR,uPC |
#define READ_USER_TRAP(RG) \ |
MOV uCC,RG \ |
/Makefile
43,8 → 43,12
################################################################################ |
# |
.PHONY: all |
all: rtl sw bench |
all: doc rtl sw bench |
|
.PHONY: doc |
doc: |
cd doc; make |
|
.PHONY: rtl |
rtl: |
cd rtl; make |