OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu/trunk
    from Rev 8 to Rev 9
    Reverse comparison

Rev 8 → Rev 9

/bench/cpp/zippy_tb.cpp
36,6 → 36,7
//
#include <signal.h>
#include <time.h>
#include <unistd.h>
 
#include <ctype.h>
#include <ncurses.h>
62,13 → 63,13
// No particular "parameters" need definition or redefinition here.
class ZIPPY_TB : public TESTB<Vzipsystem> {
public:
unsigned long m_tx_busy_count;
unsigned long m_mem_size;
MEMSIM m_mem;
// QSPIFLASHSIM m_flash;
FILE *dbg_fp;
bool dbg_flag, bomb;
 
ZIPPY_TB(void) : m_mem(1<<20) {
ZIPPY_TB(void) : m_mem_size(1<<20), m_mem(m_mem_size) {
//dbg_fp = fopen("dbg.txt", "w");
dbg_fp = NULL;
dbg_flag = false;
186,9 → 187,9
 
ln++;
showval(ln, 1, "UTSK", m_core->v__DOT__utc_data);
showval(ln,21, "UMST", m_core->v__DOT__umc_data);
showval(ln,21, "UOST", m_core->v__DOT__uoc_data);
showval(ln,41, "UPST", m_core->v__DOT__upc_data);
showval(ln,61, "UAST", m_core->v__DOT__uac_data);
showval(ln,61, "UICT", m_core->v__DOT__uic_data);
 
ln++;
mvprintw(ln, 40, "%s %s",
727,46 → 728,8
 
// mem[0x00000] = 0xbe000010; // Halt instruction
unsigned int mptr = 0;
/*
tb->m_mem[mptr++] = 0x30000000; // 0: CLR R0
tb->m_mem[mptr++] = 0x21000000; // 1: MOV R0,R1
tb->m_mem[mptr++] = 0x22000001; // 2: MOV $1+R0,R2
tb->m_mem[mptr++] = 0x23000002; // 3: MOV $2+R0,R3
tb->m_mem[mptr++] = 0x24000022; // 4: MOV $22h+R0,R4
tb->m_mem[mptr++] = 0x25100377; // 5: MOV $377h+R0,uR5
tb->m_mem[mptr++] = 0x4e000000; // 6: NOOP
tb->m_mem[mptr++] = 0xa0120000; // 7: ADD R2,R0
tb->m_mem[mptr++] = 0xa0000020; // 8: ADD $32,R0
tb->m_mem[mptr++] = 0xa00fffdf; // 9: ADD -$33,R0
tb->m_mem[mptr++] = 0xc02fffff; // A: NOT.Z R0
tb->m_mem[mptr++] = 0xc0100000; // B: CLRF R0
tb->m_mem[mptr++] = 0x31000005; // C: LDI $5,R1
tb->m_mem[mptr++] = 0x00110000; // D: CMP R0,R1
tb->m_mem[mptr++] = 0xc0afffff; // E: NOT.LT R0
tb->m_mem[mptr++] = 0xc1cfffff; // F: NOT.GE R1
tb->m_mem[mptr++] = 0x621ffff9; // 10: LOD $-7(PC),R2
tb->m_mem[mptr++] = 0x4f13dead; // 11: LODIHI $deadh,R3
tb->m_mem[mptr++] = 0x4f03beef; // 12: LODILO $beefh,R3
tb->m_mem[mptr++] = 0x731f0002; // 13: STO R3,$2(PC)
*/
 
/*
tb->m_mem[mptr++] = zp.op_clr(zp::ZIP_R12);// 0: CLR R12
tb->m_mem[mptr++] = 0x4f1cc000; // 1: LODIHI $c000h,R12
tb->m_mem[mptr++] = 0x2c1c0000; // 2: MOV R12,uR12
tb->m_mem[mptr++] = 0x2f1f000a; // 3: MOV $12+PC,uPC
tb->m_mem[mptr++] = 0x4f108001; // 4: LODIHI $8001,R0 // Turn on trap
tb->m_mem[mptr++] = 0x4f00ffff; // 5: LODILO $ffff,R0 // interrupts
tb->m_mem[mptr++] = 0x701c0001; // 6: STO R0,$1(R12)
tb->m_mem[mptr++] = 0xbe000020; // 7: RTU // Switch to user mode
tb->m_mem[mptr++] = 0x601c0000; // 8: LOD (R12),R0 // Check the result
tb->m_mem[mptr++] = 0x00000000; // A: CMP $0,R0
tb->m_mem[mptr++] = 0x2f4f0001; // B: BNZ $1+PC
tb->m_mem[mptr++] = 0xbe000010; // C: HALT // On SUCCESS
tb->m_mem[mptr++] = 0x2f0f7fff; // D: BRA PC-1 // On FAILURE
*/
 
if (argc <= 1) {
tb->m_mem[mptr++] = zp.op_clr(zp.ZIP_R0); // 0: CLR R0
tb->m_mem[mptr++] = zp.op_mov(zp.ZIP_R0,zp.ZIP_R1); // 1: MOV R0,R1
tb->m_mem[mptr++] = zp.op_mov(1,zp.ZIP_R0,zp.ZIP_R2); // 2: MOV $1+R0,R2
937,6 → 900,20
// And, in case we miss a halt ...
tb->m_mem[mptr++] = zp.op_halt(); // HALT
 
} else {
for(int argn=1; argn<argc; argn++) {
if (access(argv[argn], R_OK)==0) {
FILE *fp = fopen(argv[argn], "r");
if (fp == NULL) {
printf("Cannot open %s\n", argv[argn]);
perror("O/S Err: ");
exit(-1);
} mptr += fread(&tb->m_mem[mptr], sizeof(ZIPI), tb->m_mem_size - mptr, fp);
fclose(fp);
}
}
}
 
tb->reset();
int chv = 'q';
const bool live_debug_mode = true;
/rtl/core/zipcpu.v
121,7 → 121,7
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_data,
// Accounting/CPU usage interface
o_mem_stall, o_pf_stall, o_alu_stall);
o_op_stall, o_pf_stall, o_i_count);
parameter RESET_ADDRESS=32'h0100000;
input i_clk, i_rst, i_interrupt;
// Debug interface -- inputs
140,30 → 140,31
input i_wb_ack, i_wb_stall;
input [31:0] i_wb_data;
// Accounting outputs ... to help us count stalls and usage
output wire o_mem_stall;
output wire o_op_stall;
output wire o_pf_stall;
output wire o_alu_stall;
output wire o_i_count;
 
// Registers
reg [31:0] regset [0:31];
 
// Condition codes
reg [3:0] flags, iflags; // (BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
wire master_ce;
wire [7:0] w_uflags, w_iflags;
reg step, gie, sleep, break_en;
reg break_en, step, gie, sleep;
 
wire [4:0] mem_wreg;
wire mem_busy, mem_rdbusy;
// The master chip enable
wire master_ce;
 
reg [31:0] pf_pc;
reg new_pc;
 
//
//
// PIPELINE STAGE #1 :: Prefetch
// Variable declarations
//
wire pf_ce, dcd_stalled;
reg [31:0] pf_pc;
reg new_pc;
 
wire dcd_stalled;
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
wire [31:0] pf_addr, pf_data;
wire [31:0] instruction, instruction_pc;
231,6 → 232,9
wire mem_ce, mem_stalled;
wire mem_valid, mem_ack, mem_stall,
mem_cyc, mem_stb, mem_we;
wire [4:0] mem_wreg;
 
wire mem_busy, mem_rdbusy;
wire [31:0] mem_addr, mem_data, mem_result;
 
 
257,7 → 261,6
//
// PIPELINE STAGE #1 :: Prefetch
// Calculate stall conditions
assign pf_ce = (~dcd_stalled);
 
//
// PIPELINE STAGE #2 :: Instruction Decode
300,6 → 303,9
//
//
`ifdef SINGLE_FETCH
wire pf_ce;
 
assign pf_ce = (~dcd_stalled);
prefetch pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
instruction, instruction_pc, instruction_gie,
pf_valid,
790,9 → 796,7
// it? Do we clear both? What if a gie instruction tries to clear
// a non-gie instruction?
always @(posedge i_clk)
if (i_rst)
upc <= RESET_ADDRESS;
else if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
upc <= wr_reg_vl;
else if ((alu_gie)&&(alu_pc_valid))
upc <= alu_pc;
823,7 → 827,6
else if ((i_halt)&&(i_dbg_we)
&&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
pf_pc <= i_dbg_data;
// else if (pf_ce)
else if (dcd_ce)
pf_pc <= pf_pc + 1;
 
865,11 → 868,7
// later evaluate how well we are doing.
//
//
assign o_mem_stall = (~i_halt)&&(~sleep)&&(opvalid)&&(mem_busy)
&&(~pf_cyc);
assign o_pf_stall = (~i_halt)&&(~sleep)&&(((pf_ce)&&(~pf_valid))
||((opvalid)&&(mem_busy)&&(pf_cyc)));
// assign o_alu_stall = (~i_halt)&&(~sleep)&&(~mem_busy)&&
// ((alu_stall)||(~alu_valid));
assign o_alu_stall = alu_pc_valid;
assign o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
assign o_pf_stall = (master_ce)&&(~pf_valid);
assign o_i_count = alu_pc_valid;
endmodule
/rtl/zipsystem.v
194,32 → 194,32
// the CPU if not halted), then read/write the data from the data
// register.
//
wire cpu_break;
wire cpu_break, dbg_cmd_write;
reg cmd_reset, cmd_halt, cmd_step;
reg [5:0] cmd_addr;
assign dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
//
initial cmd_reset = 1'b1;
always @(posedge i_clk)
cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
//
initial cmd_halt = 1'b1;
initial cmd_step = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
cmd_halt <= 1'b0;
cmd_step <= 1'b0;
cmd_reset<= 1'b0;
cmd_addr <= 6'h00;
end else if ((dbg_cyc)&&(dbg_stb)
&&(dbg_we)&&(~dbg_addr))
begin
else if (dbg_cmd_write)
cmd_halt <= dbg_idata[10];
cmd_step <= dbg_idata[ 8];
cmd_reset<= dbg_idata[ 6];
else if ((cmd_step)||(cpu_break))
cmd_halt <= 1'b1;
//
initial cmd_step = 1'b0;
always @(posedge i_clk)
cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
//
always @(posedge i_clk)
if (dbg_cmd_write)
cmd_addr <= dbg_idata[5:0];
end else if (cmd_step)
begin
cmd_halt <= 1'b1;
cmd_step <= 1'b0;
end else if (cpu_break)
cmd_halt <= 1'b1;
 
wire cpu_reset;
assign cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
 
277,7 → 277,7
//
// Here's the stuff we'll be counting ....
//
wire cpu_mem_stall, cpu_pf_stall, cpu_alu_stall;
wire cpu_op_stall, cpu_pf_stall, cpu_i_count;
 
//
// The master counters will, in general, not be reset. They'll be used
291,29 → 291,29
sys_we, sys_data,
mtc_ack, mtc_stall, mtc_data, mtc_int);
 
// Master Memory-Stall counter
wire mmc_ack, mmc_stall, mmc_int;
wire [31:0] mmc_data;
zipcounter mmstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
// Master Operand Stall counter
wire moc_ack, moc_stall, moc_int;
wire [31:0] moc_data;
zipcounter mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
(sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
sys_we, sys_data,
mmc_ack, mmc_stall, mmc_data, mmc_int);
moc_ack, moc_stall, moc_data, moc_int);
 
// Master PreFetch-Stall counter
wire mpc_ack, mpc_stall, mpc_int;
wire [31:0] mpc_data;
zipcounter mpstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
zipcounter mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
(sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
sys_we, sys_data,
mpc_ack, mpc_stall, mpc_data, mpc_int);
 
// Master ALU-Stall counter
wire mac_ack, mac_stall, mac_int;
wire [31:0] mac_data;
zipcounter mastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
// Master Instruction counter
wire mic_ack, mic_stall, mic_int;
wire [31:0] mic_data;
zipcounter mins_ctr(i_clk,(cpu_i_count), sys_cyc,
(sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
sys_we, sys_data,
mac_ack, mac_stall, mac_data, mac_int);
mic_ack, mic_stall, mic_data, mic_int);
 
//
// The user counters are different from those of the master. They will
327,45 → 327,45
sys_we, sys_data,
utc_ack, utc_stall, utc_data, utc_int);
 
// User Memory-Stall counter
wire umc_ack, umc_stall, umc_int;
wire [31:0] umc_data;
zipcounter umstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
// User Op-Stall counter
wire uoc_ack, uoc_stall, uoc_int;
wire [31:0] uoc_data;
zipcounter umstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
(sys_stb)&&(sys_addr == `USER_MSTL_CTR),
sys_we, sys_data,
umc_ack, umc_stall, umc_data, umc_int);
uoc_ack, uoc_stall, uoc_data, uoc_int);
 
// User PreFetch-Stall counter
wire upc_ack, upc_stall, upc_int;
wire [31:0] upc_data;
zipcounter upstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
zipcounter upstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
(sys_stb)&&(sys_addr == `USER_PSTL_CTR),
sys_we, sys_data,
upc_ack, upc_stall, upc_data, upc_int);
 
// User ALU-Stall counter
wire uac_ack, uac_stall, uac_int;
wire [31:0] uac_data;
zipcounter uastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
// User instruction counter
wire uic_ack, uic_stall, uic_int;
wire [31:0] uic_data;
zipcounter uins_ctr(i_clk,(cpu_i_count), sys_cyc,
(sys_stb)&&(sys_addr == `USER_ASTL_CTR),
sys_we, sys_data,
uac_ack, uac_stall, uac_data, uac_int);
uic_ack, uic_stall, uic_data, uic_int);
 
// A little bit of pre-cleanup (actr = accounting counters)
wire actr_ack, actr_stall;
wire [31:0] actr_data;
assign actr_ack = ((mtc_ack | mmc_ack | mpc_ack | mac_ack)
|(utc_ack | umc_ack | upc_ack | uac_ack));
assign actr_stall = ((mtc_stall | mmc_stall | mpc_stall | mac_stall)
|(utc_stall | umc_stall | upc_stall|uac_stall));
assign actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
|(utc_ack | uoc_ack | upc_ack | uic_ack));
assign actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
|(utc_stall | uoc_stall | upc_stall|uic_stall));
assign actr_data = ((mtc_ack) ? mtc_data
: ((mmc_ack) ? mmc_data
: ((moc_ack) ? moc_data
: ((mpc_ack) ? mpc_data
: ((mac_ack) ? mac_data
: ((mic_ack) ? mic_data
: ((utc_ack) ? utc_data
: ((umc_ack) ? umc_data
: ((uoc_ack) ? uoc_data
: ((upc_ack) ? upc_data
: uac_data)))))));
: uic_data)))))));
 
 
377,8 → 377,8
wire [7:0] ctri_vector;
wire [31:0] ctri_data;
assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
assign ctri_vector = { mtc_int, mmc_int, mpc_int, mac_int,
utc_int, umc_int, upc_int, uac_int };
assign ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
utc_int, uoc_int, upc_int, uic_int };
icontrol #(8) ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
sys_data, ctri_data, ctri_vector, ctri_int);
always @(posedge i_clk)
456,7 → 456,7
cpu_break,
cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
cpu_ack, cpu_stall, wb_data,
cpu_mem_stall, cpu_pf_stall, cpu_alu_stall);
cpu_op_stall, cpu_pf_stall, cpu_i_count);
 
// Now, arbitrate the bus ... first for the local peripherals
assign sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
/rtl/peripherals/zipjiffies.v
101,9 → 101,19
wire signed [(BW-1):0] till_when, till_wb;
assign till_when = int_when-r_counter;
assign till_wb = new_when-r_counter;
 
initial new_set = 1'b0;
always @(posedge i_clk)
// Delay things by a clock to simplify our logic
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
begin
new_set <= 1'b1;
new_when<= i_wb_data;
end else
new_set <= 1'b0;
 
initial o_int = 1'b0;
initial int_set = 1'b0;
initial new_set = 1'b0;
always @(posedge i_clk)
begin
o_int <= 1'b0;
113,19 → 123,11
int_set <= 1'b0;// Clear the interrupt
end
 
new_set <= 1'b0;
if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
begin
int_when <= new_when;
int_set <= ((int_set)||(till_wb>0));
end
// Delay things by a clock to simplify our logic
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
begin
new_set <= 1'b1;
new_when<= i_wb_data;
end
end
 
//
134,7 → 136,7
//
always @(posedge i_clk)
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
 
assign o_wb_data = r_counter;
assign o_wb_stall = 1'b0;
 
endmodule
/rtl/peripherals/ziptimer.v
4,7 → 4,7
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:
// Purpose: A lighter weight implementation of the Zip Timer.
//
// Interface:
// Two options:
22,18 → 22,13
//
//
// Control bits:
// Start_n/Stop. Writing a '0' starts the timer, '1' stops it.
// Thus, ignoring this bit sets it to start.
// (Start_n/Stop. This bit has been dropped. Writing to this
// timer any value but zero starts it. Writing a zero
// clears and stops it.)
// AutoReload. If set, then on reset the timer automatically
// loads the last set value and starts over. This is
// useful for distinguishing between a one-time interrupt
// timer, and a repetitive interval timer.
// (COUNT: If set, the timer only ticks whenever an external
// line goes high. What this external line is ... is
// not specified here. This, however, breaks my
// interface ideal of having our peripheral set not depend
// upon anything. Hence, this is an advanced option
// enabled at compile time only.)
// (INTEN. Interrupt enable--reaching zero always creates an
// interrupt, so this control bit isn't needed. The
// interrupt controller can be used to mask the interrupt.)
72,7 → 67,7
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_int);
parameter BW = 32, VW = (BW-2);
parameter BW = 32, VW = (BW-1);
input i_clk, i_rst, i_ce;
// Wishbone inputs
input i_wb_cyc, i_wb_stb, i_wb_we;
86,34 → 81,41
 
reg r_auto_reload, r_running;
reg [(VW-1):0] r_reload_value;
 
wire wb_write;
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
 
initial r_running = 1'b0;
initial r_auto_reload = 1'b0;
always @(posedge i_clk)
if (i_rst)
begin
r_running <= 1'b0;
r_auto_reload <= 1'b0;
end else if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
begin
r_running <= (~i_wb_data[(BW-1)])&&(|i_wb_data[(BW-2):0]);
r_auto_reload <= (i_wb_data[(BW-2)]);
else if (wb_write)
r_running <= (|i_wb_data[(VW-1):0]);
else if ((o_int)&&(~r_auto_reload))
r_running <= 1'b0;
 
// If setting auto-reload mode, and the value to other
// than zero, set the auto-reload value
if ((i_wb_data[(BW-2)])&&(|i_wb_data[(BW-3):0]))
r_reload_value <= i_wb_data[(BW-3):0];
end
 
always @(posedge i_clk)
if (wb_write)
r_auto_reload <= (i_wb_data[(BW-1)]);
 
// If setting auto-reload mode, and the value to other
// than zero, set the auto-reload value
always @(posedge i_clk)
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0]))
r_reload_value <= i_wb_data[(VW-1):0];
 
reg [(VW-1):0] r_value;
initial r_value = 0;
always @(posedge i_clk)
if ((r_running)&&(|r_value)&&(i_ce))
begin
if (wb_write)
r_value <= i_wb_data[(VW-1):0];
else if ((r_running)&&(i_ce)&&(~o_int))
r_value <= r_value - 1;
end else if ((r_running)&&(r_auto_reload))
else if ((r_running)&&(r_auto_reload)&&(o_int))
r_value <= r_reload_value;
else if ((~r_running)&&(i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
r_value <= i_wb_data[(VW-1):0];
 
// Set the interrupt on our last tick.
initial o_int = 1'b0;
128,6 → 130,6
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
assign o_wb_stall = 1'b0;
 
assign o_wb_data = { ~r_running, r_auto_reload, r_value };
assign o_wb_data = { r_auto_reload, r_value };
 
endmodule
/sw/zasm/zparser.cpp
84,8 → 84,8
bool ZPARSER::parse_op(const char *line, ZPARSER::ZIPA pc,
ZPARSER::ZIPI &ins, const unsigned lineno) const {
const char *sp = line;
char cpy[128], *cp = cpy, *point, *dollar, *plus, *comma,
*opc, *opb;
char cpy[128], *cp = cpy, *point, *dollar, *plus, *comma, *paren,
*opc, *opb, *opa;
ZPARSER::ZIPREG ra = ZPARSER::ZIP_Rnone, rb = ZPARSER::ZIP_Rnone;
ZIPCOND cnd = ZIPC_ALWAYS;
ZIPIMM imm = 0;
118,7 → 118,7
comma = strchr(cpy, ',');
plus = strchr(cpy, '+');
dollar= strchr(cpy, '$');
// paren = strchr(cpy, '(');
paren = strchr(cpy, '(');
if (point) *point++ = '\0';
if (comma) *comma++ = '\0';
if (plus) *plus++ = '\0';
155,7 → 155,15
while(isspace(*cp))
cp++;
opb = cp;
opa = comma;
 
if (paren) {
opb = paren+1;
if ((comma)&&(opb > comma))
opa = cp;
} else if (plus)
opb = plus;
if (dollar) {
// Figure out the base
{
195,21 → 203,19
imm = -imm;
}
}
opb = dollar;
if (plus)
opb = plus;
} else
imm = 0;
 
if (*opb) for(int i=31; i>=0; i--) {
// printf("Checking for match: \'%s\' to %s", opb, zop_regstr[i]);
// printf("%s Checking for match to opB: \'%s\' to %s", opc, opb, zop_regstr[i]);
if (NULL != strcasestr(opb, zop_regstr[i])) {
// printf(" --- Match\n");
rb = (ZIPREG)i;
break;
} // else printf(" -- nope\n");
} if (comma) for(int i=31; i>=0; i--) {
// printf("Checking for match: ,%s to %s", comma, zop_regstr[i]);
if (NULL != strcasestr(comma, zop_regstr[i])) {
} if (opa) for(int i=31; i>=0; i--) {
// printf("%s Checking for match to opA: ,%s to %s", opc, opa, zop_regstr[i]);
if (NULL != strcasestr(opa, zop_regstr[i])) {
ra = (ZIPREG)i;
// printf(" --- Match\n");
break;
280,9 → 286,10
ins = op_lod(cnd,imm,rb,ra);
else ins = op_lod(cnd,imm,ra);
} else if ((strcasecmp("STO",opc)==0)||(strcasecmp("STOR",opc)==0)) {
// printf("STO: Imm = %d, RA = %d, RB = %d\n", imm, ra, rb);
if (rb != ZIP_Rnone)
ins = op_sto(cnd,rb,imm,ra);
else ins = op_sto(cnd,rb,imm);
ins = op_sto(cnd,ra,imm,rb);
else ins = op_sto(cnd,ra,imm);
} else if (strcasecmp("SUB",opc)==0) {
if (rb != ZIP_Rnone)
ins = op_sub(cnd,imm,rb,ra);
357,27 → 364,27
ins = op_clrf(cnd, rb);
else valid = false;
} else if((strcasecmp("HALT",opc)==0)||(strcasecmp("WAIT",opc)==0)) {
if ((rb == ZIP_Rnone)&&(ra==ZIP_Rnone)&&(!comma)&&(!dollar))
if ((rb == ZIP_Rnone)&&(ra==ZIP_Rnone)&&(!opa)&&(!dollar))
ins = op_halt(cnd);
else valid = false;
} else if (strcasecmp("BUSY",opc)==0) {
if ((rb == ZIP_Rnone)&&(ra==ZIP_Rnone)&&(!comma)&&(!dollar))
if ((rb == ZIP_Rnone)&&(ra==ZIP_Rnone)&&(!opa)&&(!dollar))
ins = op_busy(cnd);
else valid = false;
} else if (strcasecmp("RTU",opc)==0) {
if ((rb == ZIP_Rnone)&&(ra==ZIP_Rnone)&&(imm==0)&&(!comma)&&(!dollar))
if ((rb == ZIP_Rnone)&&(ra==ZIP_Rnone)&&(imm==0)&&(!opa)&&(!dollar))
ins = op_rtu(cnd);
else { printf("ERRR,RTU, ra=%d,rb=%d,imm=%08x,comma=%s,dollar=%s\n",
(int)ra, (int)rb, imm, (comma)?"true":"false",
(int)ra, (int)rb, imm, (opa)?"true":"false",
(dollar)?"true":"false");
valid = false;
}
} else if (strcasecmp("JMP",opc)==0) {
if ((rb != ZIP_Rnone)&&(!comma))
if ((rb != ZIP_Rnone)&&(!opa))
ins = op_not(cnd, rb);
else valid = false;
} else if (strcasecmp("NOT",opc)==0) {
if ((rb != ZIP_Rnone)&&(ra==ZIP_Rnone)&&(!comma)&&(!dollar))
if ((rb != ZIP_Rnone)&&(ra==ZIP_Rnone)&&(!opa)&&(!dollar))
ins = op_not(cnd, rb);
else valid = false;
} else valid = false;

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