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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu
    from Rev 54 to Rev 55
    Reverse comparison

Rev 54 → Rev 55

/trunk/sw/zasm/test.S
86,6 → 86,7
#define PUSH_TEST
#define PIPELINE_STACK_TEST
#define MEM_PIPELINE_TEST
#define NOWAIT_PIPELINE_TEST // Were wait states btwn regs removed properly?
test:
#ifdef DO_TEST_ASSEMBLER
; We start out by testing our assembler. We give it some instructions, which
360,14 → 361,33
ldi $0x07000,r11
ldi $-1,r0
add $1,r0
tst $2,cc
tst sys.ccc,cc
trap.z r11
// and carry from subtraction
ldi $0x08000,r11
clr r0
sub $1,r0
tst $2,cc
tst sys.ccc,cc
trap.z r11
// Carry from right shift
clr r0 ; r0 = 0
lsr 1,r0 ; r0 = 0, c = 0
add.c 1,r0 ; r0 = 0
cmp 1,r0 ; r0 ?= 1
trap.z r11
LDI 1,r0 ; r0 = 1
lsr 1,r0 ; r0 = 0, c = 1
add.c 1,r0 ; r0 = 1
cmp 1,r0
trap.nz r11
 
ldi 0x070eca6,r0
ldi 0x0408b85,r1
ldi 0x0387653,r2
lsr 1,r0
xor.c r1,r0
cmp r2,r0
trap.nz r11
#endif
 
#ifdef LOOP_TEST
552,6 → 572,10
JSR(mem_pipeline_test,R0)
#endif // MEM_PIPELINE_TEST
 
#ifdef NOWAIT_PIPELINE_TEST
JSR(nowait_pipeline_test,R0)
#endif // NOWAIT_PIPELINE_TEST
 
// Return success / Test the trap interrupt
clr r11
trap r11
582,6 → 606,13
RET
#endif
 
; The pipeline stack test examines whether or not a series of memory commands
; can be evaluated right after the other without problems. This depends upon
; the calling routine to properly set up registers to be tested.
;
; This is also an incomplete test, as nothing is done to test how these
; pipeline reads/writes are affected by condition codes.
;
#ifdef PIPELINE_STACK_TEST
pipeline_stack_test:
SUB 13,SP
667,6 → 698,47
RETN
#endif
 
;
; Pipeline stalls have been hideous problems for me. The CPU has been modified
; with special logic to keep stages from stalling. For the most part, this
; means that ALU and memory results may be accessed either before or as they
; are written to the register file. This set of code is designed to test
; whether this bypass logic works.
#ifdef NOWAIT_PIPELINE_TEST
nowait_pipeline_test:
; Allocate for us some number of registers
;
SUB 5,SP
STO R0,1(SP)
STO R1,2(SP)
STO R2,3(SP)
STO R3,4(SP)
STO R4,5(SP)
;
; Let's start with ALU-ALU testing
; AA: result->input A
; AA: result->input B
; AA: result->input A on condition
; AA: result->input B on condition
; AA: result->input B plus offset
; AA: result->input B plus offset on condition
;
; Then we need to do ALU-Mem input testing
; (not implemented yet)
; Mem output->ALU input testing
; (not implemented yet)
; Mem output->MEM input testing
; (not implemented yet)
;
LOD 1(SP),R0
LOD 2(SP),R1
LOD 3(SP),R2
LOD 4(SP),R3
LOD 5(SP),R4
ADD 5,SP
RETN
#endif // NOWAIT_PIPELINE_TEST
 
fill 512,0
stack: // Must point to a valid word initially
word 0

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