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URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

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  • This comparison shows the changes necessary to convert path
    /zipcpu
    from Rev 65 to Rev 66
    Reverse comparison

Rev 65 → Rev 66

/trunk/rtl/zipsystem.v
82,6 → 82,8
//
///////////////////////////////////////////////////////////////////////////
//
`include "cpudefs.v"
//
// While I hate adding delays to any bus access, this next delay is required
// to make timing close in my Basys-3 design.
`define DELAY_DBG_BUS
151,6 → 153,9
// [4:0] REGISTER-ADDR
// DBGDATA
// read/writes internal registers
//
//
//
module zipsystem(i_clk, i_rst,
// Wishbone master interface from the CPU
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
161,10 → 166,13
o_ext_int,
// Wishbone slave interface for debugging purposes
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
o_dbg_ack, o_dbg_stall, o_dbg_data,
o_cpu_debug);
o_dbg_ack, o_dbg_stall, o_dbg_data
`ifdef DEBUG_SCOPE
, o_cpu_debug
`endif
);
parameter RESET_ADDRESS=24'h0100000, ADDRESS_WIDTH=24,
LGICACHE=6, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
LGICACHE=12, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
// Derived parameters
AW=ADDRESS_WIDTH;
input i_clk, i_rst;
186,7 → 194,9
output wire o_dbg_stall;
output wire [31:0] o_dbg_data;
//
`ifdef DEBUG_SCOPE
output wire [31:0] o_cpu_debug;
`endif
 
wire [31:0] ext_idata;
 
467,7 → 477,7
wire [(AW-1):0] dc_addr;
wire cpu_gbl_cyc;
assign dmac_stb = (sys_stb)&&(sys_addr[4]);
// `define INCLUDE_DMA_CONTROLLER
`define INCLUDE_DMA_CONTROLLER
`ifdef INCLUDE_DMA_CONTROLLER
wbdmac #(AW) dma_controller(i_clk,
sys_cyc, dmac_stb, sys_we,
607,8 → 617,11
cpu_we, cpu_addr, cpu_data,
cpu_ack, cpu_stall, wb_data,
cpu_err,
cpu_op_stall, cpu_pf_stall, cpu_i_count,
o_cpu_debug);
cpu_op_stall, cpu_pf_stall, cpu_i_count
`ifdef DEBUG_SCOPE
, o_cpu_debug
`endif
);
 
// Now, arbitrate the bus ... first for the local peripherals
// For the debugger to have access to the local system bus, the
/trunk/rtl/zipbones.v
41,8 → 41,11
o_ext_int,
// Wishbone slave interface for debugging purposes
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
o_dbg_ack, o_dbg_stall, o_dbg_data,
o_zip_debug);
o_dbg_ack, o_dbg_stall, o_dbg_data
`ifdef DEBUG_SCOPE
, o_zip_debug
`endif
);
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
LGICACHE=6, START_HALTED=1,
AW=ADDRESS_WIDTH;
65,7 → 68,9
output wire o_dbg_stall;
output wire [31:0] o_dbg_data;
//
`ifdef DEBUG_SCOPE
output wire [31:0] o_zip_debug;
`endif
 
//
//
165,9 → 170,12
cpu_lcl_cyc, cpu_lcl_stb,
o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_data,
i_wb_err,
cpu_op_stall, cpu_pf_stall, cpu_i_count,
o_zip_debug);
(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
cpu_op_stall, cpu_pf_stall, cpu_i_count
`ifdef DEBUG_SCOPE
, o_zip_debug
`endif
);
 
// Return debug response values
assign o_dbg_data = (~i_dbg_addr)?cmd_data :cpu_dbg_data;

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