URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
Subversion Repositories zipcpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/zipcpu
- from Rev 90 to Rev 91
- ↔ Reverse comparison
Rev 90 → Rev 91
/trunk/rtl/core/zipcpu.v
740,6 → 740,8
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
initial opvalid_div = 1'b0; |
initial opvalid_fpu = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
969,16 → 971,17
// will write to opB -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI)) |
); |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
`else |
// No stalls without pipelining, 'cause how can you have a pipeline |
// hazard without the pipeline? |
assign dcdB_stall = 1'b0; |
assign dcdF_stall = 1'b0; |
`endif |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
// |
// |
// PIPELINE STAGE #4 :: Apply Instruction |
/trunk/rtl/zipbones.v
100,6 → 100,8
wire [3:0] cpu_dbg_cc; |
assign dbg_cmd_write = (i_dbg_cyc)&&(i_dbg_stb)&&(i_dbg_we)&&(~i_dbg_addr); |
// |
// Always start us off with an initial reset |
// |
initial cmd_reset = 1'b1; |
always @(posedge i_clk) |
cmd_reset <= ((dbg_cmd_write)&&(i_dbg_data[6])); |
113,6 → 115,7
else if ((cmd_step)||(cpu_break)) |
cmd_halt <= 1'b1; |
|
initial cmd_clear_pf_cache = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
cmd_clear_pf_cache <= 1'b0; |
125,6 → 128,7
always @(posedge i_clk) |
cmd_step <= (dbg_cmd_write)&&(i_dbg_data[8]); |
// |
initial cmd_addr = 5'h0; |
always @(posedge i_clk) |
if (dbg_cmd_write) |
cmd_addr <= i_dbg_data[4:0]; |