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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.10 2003/04/07 14:58:02 simont
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// change sfr's interface.
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//
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// Revision 1.9 2003/01/13 14:14:40 simont
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// Revision 1.9 2003/01/13 14:14:40 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.8 2002/11/05 17:23:54 simont
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// Revision 1.8 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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// add module oc8051_sfr, 256 bytes internal ram
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Line 78... |
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output p;
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output p;
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output [7:0] data_out;
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output [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] data_out;
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reg [7:0] acc;
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wire wr_acc, wr2_acc, wr_bit_acc;
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//
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//
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//calculates parity
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//calculates parity
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assign p = ^data_out;
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assign p = ^acc;
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assign wr_acc = (wr_sfr==`OC8051_WRS_ACC1) | (wr & !wr_bit & (wr_addr==`OC8051_SFR_ACC));
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assign wr2_acc = (wr_sfr==`OC8051_WRS_ACC2) | (wr_sfr==`OC8051_WRS_BA);
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assign wr_bit_acc = (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_ACC));
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//
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//
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//writing to acc
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//writing to acc
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//must check if write high and correct address
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always @(wr_sfr or data2_in or wr2_acc or wr_acc or wr_bit_acc or wr_addr[2:0] or data_in or bit_in or data_out)
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begin
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if (wr2_acc)
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acc = data2_in;
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else if (wr_acc)
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acc = data_in;
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else if (wr_bit_acc)
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case (wr_addr[2:0])
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3'b000: acc = {data_out[7:1], bit_in};
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3'b001: acc = {data_out[7:2], bit_in, data_out[0]};
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3'b010: acc = {data_out[7:3], bit_in, data_out[1:0]};
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3'b011: acc = {data_out[7:4], bit_in, data_out[2:0]};
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3'b100: acc = {data_out[7:5], bit_in, data_out[3:0]};
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3'b101: acc = {data_out[7:6], bit_in, data_out[4:0]};
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3'b110: acc = {data_out[7], bit_in, data_out[5:0]};
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default: acc = {bit_in, data_out[6:0]};
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endcase
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else
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acc = data_out;
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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data_out <= #1 `OC8051_RST_ACC;
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data_out <= #1 `OC8051_RST_ACC;
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else if ((wr_sfr==`OC8051_WRS_ACC2) || (wr_sfr==`OC8051_WRS_BA))
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else
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data_out <= #1 data2_in;
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data_out <= #1 acc;
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else if ((wr_sfr==`OC8051_WRS_ACC1))
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data_out <= #1 data_in;
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else if (wr) begin
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if (!wr_bit) begin
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if (wr_addr==`OC8051_SFR_ACC)
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data_out <= #1 data_in;
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end else begin
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if (wr_addr[7:3]==`OC8051_SFR_B_ACC)
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data_out[wr_addr[2:0]] <= #1 bit_in;
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end
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end
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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