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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Diff between revs 143 and 152

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Rev 143 Rev 152
Line 44... Line 44...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.15  2003/05/07 12:31:53  simont
 
// add wire sub_result, conect it to des_acc and des1.
 
//
// Revision 1.14  2003/05/05 15:46:36  simont
// Revision 1.14  2003/05/05 15:46:36  simont
// add aditional alu destination to solve critical path.
// add aditional alu destination to solve critical path.
//
//
// Revision 1.13  2003/04/29 08:35:12  simont
// Revision 1.13  2003/04/29 08:35:12  simont
// fix bug in substraction.
// fix bug in substraction.
Line 73... Line 76...
`include "oc8051_defines.v"
`include "oc8051_defines.v"
 
 
 
 
 
 
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
module oc8051_alu (clk, rst, op_code, src1, src2, src3, srcCy, srcAc, bit_in,
                  des1, des2, des_acc, desCy, desAc, desOv);
                  des1, des2, des_acc, desCy, desAc, desOv, sub_result);
//
//
// op_code      (in)  operation code [oc8051_decoder.alu_op -r]
// op_code      (in)  operation code [oc8051_decoder.alu_op -r]
// src1         (in)  first operand [oc8051_alu_src1_sel.des]
// src1         (in)  first operand [oc8051_alu_src1_sel.des]
// src2         (in)  second operand [oc8051_alu_src2_sel.des]
// src2         (in)  second operand [oc8051_alu_src2_sel.des]
// src3         (in)  third operand [oc8051_alu_src3_sel.des]
// src3         (in)  third operand [oc8051_alu_src3_sel.des]
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input        srcCy, srcAc, bit_in, clk, rst;
input        srcCy, srcAc, bit_in, clk, rst;
input  [3:0] op_code;
input  [3:0] op_code;
input  [7:0] src1, src2, src3;
input  [7:0] src1, src2, src3;
output       desCy, desAc, desOv;
output       desCy, desAc, desOv;
output [7:0] des1, des2, des_acc;
output [7:0] des1, des2, des_acc, sub_result;
 
 
reg desCy, desAc, desOv;
reg desCy, desAc, desOv;
reg [7:0] des1, des2, des_acc;
reg [7:0] des1, des2, des_acc;
 
 
 
 
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      enable_div = 1'b0;
      enable_div = 1'b0;
    end
    end
//operation subtract
//operation subtract
    `OC8051_ALU_SUB: begin
    `OC8051_ALU_SUB: begin
      des_acc = sub_result;
      des_acc = sub_result;
      des1 = sub_result;
//      des1 = sub_result;
 
      des1 = 8'h00;
      des2 = 8'h00;
      des2 = 8'h00;
      desCy = !subc[1];
      desCy = !subc[1];
      desAc = !sub4[4];
      desAc = !sub4[4];
      desOv = !subc[1] ^ !sub8[3];
      desOv = !subc[1] ^ !sub8[3];
 
 

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