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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu.v] - Diff between revs 171 and 178
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| Rev 171 |
Rev 178 |
| Line 44... |
Line 44... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.17 2003/06/09 16:51:16 simont
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// fix bug in DA operation.
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//
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// Revision 1.16 2003/06/03 17:15:06 simont
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// Revision 1.16 2003/06/03 17:15:06 simont
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// sub_result output added.
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// sub_result output added.
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//
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//
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// Revision 1.15 2003/05/07 12:31:53 simont
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// Revision 1.15 2003/05/07 12:31:53 simont
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// add wire sub_result, conect it to des_acc and des1.
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// add wire sub_result, conect it to des_acc and des1.
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| Line 224... |
Line 227... |
des_acc = mulsrc1;
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des_acc = mulsrc1;
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des1 = src1;
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des1 = src1;
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des2 = mulsrc2;
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des2 = mulsrc2;
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desOv = mulOv;
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desOv = mulOv;
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desCy = 1'b0;
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desCy = 1'b0;
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desAc = 1'bx;
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desAc = 1'b0;
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enable_mul = 1'b1;
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enable_mul = 1'b1;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation divide
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//operation divide
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`OC8051_ALU_DIV: begin
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`OC8051_ALU_DIV: begin
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des_acc = divsrc1;
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des_acc = divsrc1;
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des1 = src1;
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des1 = src1;
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des2 = divsrc2;
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des2 = divsrc2;
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desOv = divOv;
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desOv = divOv;
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desAc = 1'bx;
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desAc = 1'b0;
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desCy = 1'b0;
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desCy = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b1;
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enable_div = 1'b1;
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end
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end
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//operation decimal adjustment
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//operation decimal adjustment
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| Line 264... |
Line 267... |
`OC8051_ALU_NOT: begin
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`OC8051_ALU_NOT: begin
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des_acc = ~src1;
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des_acc = ~src1;
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des1 = ~src1;
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des1 = ~src1;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = !srcCy;
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desCy = !srcCy;
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desAc = 1'bx;
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desAc = 1'b0;
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desOv = 1'bx;
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desOv = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation and
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//operation and
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//bit operation and
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//bit operation and
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`OC8051_ALU_AND: begin
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`OC8051_ALU_AND: begin
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des_acc = src1 & src2;
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des_acc = src1 & src2;
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des1 = src1 & src2;
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des1 = src1 & src2;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = srcCy & bit_in;
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desCy = srcCy & bit_in;
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desAc = 1'bx;
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desAc = 1'b0;
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desOv = 1'bx;
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desOv = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation xor
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//operation xor
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// bit operation xor
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// bit operation xor
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`OC8051_ALU_XOR: begin
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`OC8051_ALU_XOR: begin
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des_acc = src1 ^ src2;
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des_acc = src1 ^ src2;
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des1 = src1 ^ src2;
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des1 = src1 ^ src2;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = srcCy ^ bit_in;
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desCy = srcCy ^ bit_in;
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desAc = 1'bx;
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desAc = 1'b0;
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desOv = 1'bx;
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desOv = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation or
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//operation or
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// bit operation or
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// bit operation or
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`OC8051_ALU_OR: begin
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`OC8051_ALU_OR: begin
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des_acc = src1 | src2;
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des_acc = src1 | src2;
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des1 = src1 | src2;
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des1 = src1 | src2;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = srcCy | bit_in;
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desCy = srcCy | bit_in;
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desAc = 1'bx;
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desAc = 1'b0;
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desOv = 1'bx;
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desOv = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation rotate left
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//operation rotate left
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// bit operation cy= cy or (not ram)
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// bit operation cy= cy or (not ram)
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`OC8051_ALU_RL: begin
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`OC8051_ALU_RL: begin
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des_acc = {src1[6:0], src1[7]};
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des_acc = {src1[6:0], src1[7]};
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des1 = src1 ;
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des1 = src1 ;
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des2 = 8'h00;
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des2 = 8'h00;
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desCy = srcCy | !bit_in;
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desCy = srcCy | !bit_in;
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desAc = 1'bx;
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desAc = 1'b0;
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desOv = 1'bx;
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desOv = 1'b0;
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enable_mul = 1'b0;
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enable_mul = 1'b0;
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enable_div = 1'b0;
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enable_div = 1'b0;
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end
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end
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//operation rotate left with carry and swap nibbles
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//operation rotate left with carry and swap nibbles
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`OC8051_ALU_RLC: begin
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`OC8051_ALU_RLC: begin
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