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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_comp.v] - Diff between revs 2 and 9
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| Rev 2 |
Rev 9 |
| Line 63... |
Line 63... |
// des (in) destination from alu [oc8051_alu.des1 -r]
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// des (in) destination from alu [oc8051_alu.des1 -r]
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// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
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// eq (out) if (src1 == src2) eq = 1 [oc8051_decoder.eq]
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//
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//
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input [2:0] sel;
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input [1:0] sel;
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input b_in, cy;
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input b_in, cy;
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input [7:0] acc, ram, op2, des;
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input [7:0] acc, ram, op2, des;
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output eq;
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output eq;
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reg eq;
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reg eq;
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always @(sel or b_in or cy or acc or ram or op2 or des)
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always @(sel or b_in or cy or acc or ram or op2 or des)
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begin
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begin
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case (sel)
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case (sel)
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`OC8051_CSS_AZ : eq = (acc == 8'h00);
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`OC8051_CSS_AZ : eq = (acc == 8'h00);
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`OC8051_CSS_AR : eq = (acc == ram);
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`OC8051_CSS_AC : eq = (acc == op2);
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`OC8051_CSS_CR : eq = (op2 == ram);
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`OC8051_CSS_DES : eq = (des == 8'h00);
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`OC8051_CSS_DES : eq = (des == 8'h00);
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`OC8051_CSS_CY : eq = cy;
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`OC8051_CSS_CY : eq = cy;
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`OC8051_CSS_BIT : eq = b_in;
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`OC8051_CSS_BIT : eq = b_in;
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default: eq = 1'bx;
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default: eq = 1'bx;
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endcase
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endcase
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