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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2003/04/09 15:49:42 simont
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// Register oc8051_sfr dato output, add signal wait_data.
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//
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// Revision 1.14 2003/01/13 14:14:40 simont
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// Revision 1.14 2003/01/13 14:14:40 simont
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// replace some modules
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// replace some modules
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//
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//
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// Revision 1.13 2002/10/23 16:53:39 simont
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// Revision 1.13 2002/10/23 16:53:39 simont
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// fix bugs in instruction interface
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// fix bugs in instruction interface
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Line 103... |
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input clk, rst, eq, mem_wait, wait_data;
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input clk, rst, eq, mem_wait, wait_data;
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input [7:0] op_in;
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input [7:0] op_in;
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output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
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output wr_o, bit_addr, pc_wr, rmw, istb, src_sel3;
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output [1:0] psw_set, cy_sel, comp_sel;
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output [1:0] psw_set, cy_sel, wr_sfr_o, comp_sel;
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output [2:0] mem_act, src_sel1, src_sel2, ram_rd_sel_o, ram_wr_sel_o, pc_sel, wr_sfr_o, op1_c;
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output [2:0] mem_act, src_sel1, src_sel2, ram_rd_sel_o, ram_wr_sel_o, pc_sel, op1_c;
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output [3:0] alu_op_o;
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output [3:0] alu_op_o;
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output rd;
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output rd;
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reg rmw;
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reg rmw;
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reg src_sel3, wr, bit_addr, pc_wr;
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reg src_sel3, wr, bit_addr, pc_wr;
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reg [1:0] comp_sel, psw_set, cy_sel;
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reg [1:0] comp_sel, psw_set, cy_sel, wr_sfr;
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reg [3:0] alu_op;
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reg [3:0] alu_op;
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reg [2:0] src_sel2, mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel, wr_sfr;
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reg [2:0] src_sel2, mem_act, src_sel1, ram_wr_sel, ram_rd_sel, pc_sel;
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//
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//
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// state if 2'b00 then normal execution, sle instructin that need more than one clock
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// state if 2'b00 then normal execution, sle instructin that need more than one clock
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// op instruction buffer
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// op instruction buffer
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reg [1:0] state;
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reg [1:0] state;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= #1 `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_N;
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wr_sfr <= #1 `OC8051_WRS_N;
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end
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end
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`OC8051_DIV : begin
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`OC8051_DIV : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= #1 `OC8051_RWS_B;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_DIV;
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alu_op <= #1 `OC8051_ALU_DIV;
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wr <= #1 1'b0;
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wr <= #1 1'b1;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <= #1 `OC8051_PS_OV;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= #1 `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_BA;
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wr_sfr <= #1 `OC8051_WRS_ACC2;
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end
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end
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`OC8051_MUL : begin
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`OC8051_MUL : begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= #1 `OC8051_RWS_B;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel1 <= #1 `OC8051_AS1_ACC;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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src_sel2 <= #1 `OC8051_AS2_RAM;
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alu_op <= #1 `OC8051_ALU_MUL;
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alu_op <= #1 `OC8051_ALU_MUL;
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wr <= #1 1'b0;
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wr <= #1 1'b1;
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psw_set <= #1 `OC8051_PS_OV;
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psw_set <= #1 `OC8051_PS_OV;
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cy_sel <= #1 `OC8051_CY_0;
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cy_sel <= #1 `OC8051_CY_0;
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src_sel3 <= #1 `OC8051_AS3_DC;
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src_sel3 <= #1 `OC8051_AS3_DC;
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wr_sfr <= #1 `OC8051_WRS_BA;
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wr_sfr <= #1 `OC8051_WRS_ACC2;
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end
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end
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default begin
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default begin
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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ram_wr_sel <= #1 `OC8051_RWS_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel1 <= #1 `OC8051_AS1_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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src_sel2 <= #1 `OC8051_AS2_DC;
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